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//
// Generated by Microsoft (R) HLSL Shader Compiler 9.25.950.2675
//
// using 3Dmigoto v1.3.16 on Wed Feb 09 18:55:49 2022
//
//
// Buffer Definitions:
//
// cbuffer cbPS
// {
//
// float4 factors; // Offset: 0 Size: 16
// float4 offset; // Offset: 16 Size: 16
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// Text_Texture sampler NA NA 0 1
// Text_Texture texture float4 2d 0 1
// cbPS cbuffer NA NA 0 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_POSITION 0 xyzw 0 POS float
// TEXCOORD 0 xyzw 1 NONE float
// TEXCOORD 1 xy 2 NONE float xy
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Target 0 xyzw 0 TARGET float xyzw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c0 cb0 0 2 ( FLT, FLT, FLT, FLT)
//
//
// Sampler/Resource to DX9 shader sampler mappings:
//
// Target Sampler Source Sampler Source Resource
// -------------- --------------- ----------------
// s0 s0 t0
//
//
// Level9 shader bytecode:
//
ps_2_0
def c2, 4, 0, 0, 0
dcl t1.xy
dcl_2d s0
add r0.xy, t1, -c1
add r1.xy, t1, c1
texld r0, r0, s0
texld r1, r1, s0
texld r2, t1, s0
mov r0.z, r1.x
mov r0.y, r2.x
mad r1.xyz, r0, -c0.x, c0.y
mul r0.xyz, r0, c0.x
mad r2.xyz, c0.z, r0, c0.w
mul r1.xyz, r1, r2
mul r1.xyz, r0, r1
mad r0.xyz, r1, c2.x, r0
mov r1.xyz, r0
mov r1.w, r0.y
mov oC0, r1
// approximately 16 instruction slots used (3 texture, 13 arithmetic)
ps_4_0
dcl_constantbuffer cb0[2], immediateIndexed
dcl_sampler s0, mode_default
dcl_resource_texture2d (float,float,float,float) t0
dcl_input_ps linear v2.xy
dcl_output o0.xyzw
dcl_temps 3
add r0.xy, v2.xyxx, -cb0[1].xyxx
sample r0.xyzw, r0.xyxx, t0.xyzw, s0
add r1.xy, v2.xyxx, cb0[1].xyxx
sample r1.xyzw, r1.xyxx, t0.xyzw, s0
mov r0.z, r1.x
sample r1.xyzw, v2.xyxx, t0.xyzw, s0
mov r0.yw, r1.xxxx
mad r1.xyzw, -r0.xwzw, cb0[0].xxxx, cb0[0].yyyy
mul r0.xyzw, r0.xyzw, cb0[0].xxxx
mad r2.xyzw, cb0[0].zzzz, r0.xwzw, cb0[0].wwww
mul r1.xyzw, r1.xyzw, r2.xyzw
mul r1.xyzw, r0.xwzw, r1.xyzw
mad o0.xyzw, r1.xyzw, l(4.000000, 4.000000, 4.000000, 4.000000), r0.xyzw
ret
// Approximately 14 instruction slots used
|
