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path: root/disassembly/dwmcore_1004_10.asm
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//
// Generated by Microsoft (R) HLSL Shader Compiler 9.25.950.2675
//
//   using 3Dmigoto v1.3.16 on Wed Feb 09 18:55:49 2022
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// POSITION                 0   xyz         0     NONE   float   xyz
// TEXCOORD                 0   xyzw        1     NONE   float   xyzw
// TEXCOORD                 1   xy          2     NONE   float   xy
// TEXCOORD                 2   xy          3     NONE   float   xy
//
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_POSITION              0   xyzw        0      POS   float   xyzw
// TEXCOORD                 0   xyzw        1     NONE   float   xyzw
// TEXCOORD                 1   xy          2     NONE   float   xy
// TEXCOORD                 2     zw        2     NONE   float     zw
//
//
// Runtime generated constant mappings:
//
// Target Reg                               Constant Description
// ---------- --------------------------------------------------
// c0                              Vertex Shader position offset
//
//
// Level9 shader bytecode:
//
    vs_2_0
    def c1, 1, 0, 0, 0
    dcl_texcoord v0
    dcl_texcoord1 v1
    dcl_texcoord2 v2
    dcl_texcoord3 v3
    add oPos.xy, v0, c0
    mad oPos.zw, v0.z, c1.xyxy, c1.xyyx
    mov oT0, v1
    mov oT1.xy, v2
    mov oT1.zw, v3.xyyx

// approximately 5 instruction slots used
vs_4_0
dcl_input v0.xyz
dcl_input v1.xyzw
dcl_input v2.xy
dcl_input v3.xy
dcl_output_siv o0.xyzw, position
dcl_output o1.xyzw
dcl_output o2.xy
dcl_output o2.zw
mov o0.xyz, v0.xyzx
mov o0.w, l(1.000000)
mov o1.xyzw, v1.xyzw
mov o2.xy, v2.xyxx
mov o2.zw, v3.xxxy
ret
// Approximately 6 instruction slots used