diff options
Diffstat (limited to 'disassembly/dwmcore_2261_10.asm')
-rw-r--r-- | disassembly/dwmcore_2261_10.asm | 148 |
1 files changed, 148 insertions, 0 deletions
diff --git a/disassembly/dwmcore_2261_10.asm b/disassembly/dwmcore_2261_10.asm new file mode 100644 index 0000000..ab1e524 --- /dev/null +++ b/disassembly/dwmcore_2261_10.asm @@ -0,0 +1,148 @@ +// +// Generated by Microsoft (R) HLSL Shader Compiler 9.25.950.2675 +// +// using 3Dmigoto v1.3.16 on Wed Feb 09 18:55:48 2022 +// +// +// Buffer Definitions: +// +// cbuffer cbPSUpdateEveryCall +// { +// +// struct +// { +// +// struct +// { +// +// float4x4 mat4x4; // Offset: 0 +// float4 matRow4; // Offset: 64 +// +// } TransformColor_PS2_ConstantTable;// Offset: 0 +// +// } Data_PS; // Offset: 0 Size: 80 +// +// } +// +// +// Resource Bindings: +// +// Name Type Format Dim Slot Elements +// ------------------------------ ---------- ------- ----------- ---- -------- +// SuperSampleTextureFromInterpolatorUV1_Sampler sampler NA NA 0 1 +// SuperSampleTextureFromInterpolatorUV1_Sampler texture float4 2d 0 1 +// cbPSUpdateEveryCall cbuffer NA NA 0 1 +// +// +// +// Input signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// SV_POSITION 0 xyzw 0 POS float +// TEXCOORD 0 xyzw 1 NONE float +// TEXCOORD 1 xyzw 2 NONE float xyzw +// TEXCOORD 2 xyzw 3 NONE float xyzw +// TEXCOORD 3 xyzw 4 NONE float xyzw +// +// +// Output signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// SV_Target 0 xyzw 0 TARGET float xyzw +// +// +// Constant buffer to DX9 shader constant mappings: +// +// Target Reg Buffer Start Reg # of Regs Data Conversion +// ---------- ------- --------- --------- ---------------------- +// c0 cb0 0 5 ( FLT, FLT, FLT, FLT) +// +// +// Sampler/Resource to DX9 shader sampler mappings: +// +// Target Sampler Source Sampler Source Resource +// -------------- --------------- ---------------- +// s0 s0 t0 +// +// +// Level9 shader bytecode: +// + ps_2_0 + def c5, 0.25, 0.00313080009, 12.9200001, 0.416666657 + def c6, 1.05499995, -0.0549999997, 1, 0 + dcl t1 + dcl t2 + dcl t3 + dcl_2d s0 + mov r0.x, t1.z + mov r0.y, t1.w + mov r1.x, t2.z + mov r1.y, t2.w + texld r0, r0, s0 + texld r2, t1, s0 + texld r3, t2, s0 + texld r1, r1, s0 + add r0.xyz, r0, r2 + add r0.xyz, r3, r0 + add r0.xyz, r1, r0 + mul_sat r0.xyz, r0, c5.x + pow r1.x, r0.x, c5.w + mad r0.w, r1.x, c6.x, c6.y + add r1.x, -r0.x, c5.y + mul r0.x, r0.x, c5.z + cmp r1.x, r1.x, r0.x, r0.w + pow r2.x, r0.y, c5.w + mad r0.x, r2.x, c6.x, c6.y + add r0.w, -r0.y, c5.y + mul r0.y, r0.y, c5.z + cmp r1.y, r0.w, r0.y, r0.x + pow r2.x, r0.z, c5.w + mad r0.x, r2.x, c6.x, c6.y + add r0.y, -r0.z, c5.y + mul r0.z, r0.z, c5.z + cmp r1.z, r0.y, r0.z, r0.x + mov r1.w, c6.z + dp4 r0.x, r1, c0 + dp4 r0.y, r1, c1 + dp4 r0.z, r1, c2 + dp4 r0.w, r1, c3 + add r0, r0, c4 + mul r0, r0, t3 + mov oC0, r0 + +// approximately 41 instruction slots used (4 texture, 37 arithmetic) +ps_4_0 +dcl_constantbuffer cb0[5], immediateIndexed +dcl_sampler s0, mode_default +dcl_resource_texture2d (float,float,float,float) t0 +dcl_input_ps linear v2.xyzw +dcl_input_ps linear v3.xyzw +dcl_input_ps linear v4.xyzw +dcl_output o0.xyzw +dcl_temps 3 +sample r0.xyzw, v2.xyxx, t0.xyzw, s0 +sample r1.xyzw, v2.zwzz, t0.xyzw, s0 +add r0.xyz, r0.xyzx, r1.xyzx +sample r1.xyzw, v3.xyxx, t0.xyzw, s0 +add r0.xyz, r0.xyzx, r1.xyzx +sample r1.xyzw, v3.zwzz, t0.xyzw, s0 +add r0.xyz, r0.xyzx, r1.xyzx +mul_sat r0.xyz, r0.xyzx, l(0.250000, 0.250000, 0.250000, 0.000000) +log r1.xyz, r0.xyzx +mul r1.xyz, r1.xyzx, l(0.416666657, 0.416666657, 0.416666657, 0.000000) +exp r1.xyz, r1.xyzx +mad r1.xyz, r1.xyzx, l(1.055000, 1.055000, 1.055000, 0.000000), l(-0.055000, -0.055000, -0.055000, 0.000000) +ge r2.xyz, l(0.00313080009, 0.00313080009, 0.00313080009, 0.000000), r0.xyzx +mul r0.xyz, r0.xyzx, l(12.920000, 12.920000, 12.920000, 0.000000) +movc r0.xyz, r2.xyzx, r0.xyzx, r1.xyzx +mov r0.w, l(1.000000) +dp4 r1.x, r0.xyzw, cb0[0].xyzw +dp4 r1.y, r0.xyzw, cb0[1].xyzw +dp4 r1.z, r0.xyzw, cb0[2].xyzw +dp4 r1.w, r0.xyzw, cb0[3].xyzw +add r0.xyzw, r1.xyzw, cb0[4].xyzw +mul o0.xyzw, r0.xyzw, v4.xyzw +ret +// Approximately 23 instruction slots used |