diff options
Diffstat (limited to 'disassembly/dwmcore_2046_10.asm')
-rw-r--r-- | disassembly/dwmcore_2046_10.asm | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/disassembly/dwmcore_2046_10.asm b/disassembly/dwmcore_2046_10.asm new file mode 100644 index 0000000..2fc15bc --- /dev/null +++ b/disassembly/dwmcore_2046_10.asm @@ -0,0 +1,85 @@ +// +// Generated by Microsoft (R) HLSL Shader Compiler 9.25.950.2675 +// +// using 3Dmigoto v1.3.16 on Wed Feb 09 18:55:49 2022 +// +// +// Buffer Definitions: +// +// cbuffer cbPSUpdateEveryCall +// { +// +// struct +// { +// +// struct +// { +// +// float4 color; // Offset: 0 +// +// } SetColorValue_PS1_ConstantTable;// Offset: 0 +// +// struct +// { +// +// float4 color; // Offset: 16 +// +// } SetColorValue_PS2_ConstantTable;// Offset: 16 +// +// } Data_PS; // Offset: 0 Size: 32 +// +// } +// +// +// Resource Bindings: +// +// Name Type Format Dim Slot Elements +// ------------------------------ ---------- ------- ----------- ---- -------- +// cbPSUpdateEveryCall cbuffer NA NA 0 1 +// +// +// +// Input signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// SV_POSITION 0 xyzw 0 POS float +// TEXCOORD 0 xyzw 1 NONE float +// TEXCOORD 1 xyzw 2 NONE float xyzw +// +// +// Output signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// SV_Target 0 xyzw 0 TARGET float xyzw +// +// +// Constant buffer to DX9 shader constant mappings: +// +// Target Reg Buffer Start Reg # of Regs Data Conversion +// ---------- ------- --------- --------- ---------------------- +// c0 cb0 0 2 ( FLT, FLT, FLT, FLT) +// +// +// Level9 shader bytecode: +// + ps_2_0 + dcl t1 + mov r0.w, c0.w + mul r0.x, r0.w, c1.w + mul r0.w, r0.x, t1.w + mul r0.xyz, t1, c0 + mov oC0, r0 + +// approximately 5 instruction slots used +ps_4_0 +dcl_constantbuffer cb0[2], immediateIndexed +dcl_input_ps linear v2.xyzw +dcl_output o0.xyzw +dcl_temps 1 +mul r0.x, cb0[0].w, cb0[1].w +mul o0.w, r0.x, v2.w +mul o0.xyz, v2.xyzx, cb0[0].xyzx +ret +// Approximately 4 instruction slots used |