diff options
Diffstat (limited to 'disassembly/dwmcore_2019_10.asm')
| -rw-r--r-- | disassembly/dwmcore_2019_10.asm | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/disassembly/dwmcore_2019_10.asm b/disassembly/dwmcore_2019_10.asm new file mode 100644 index 0000000..825b8f1 --- /dev/null +++ b/disassembly/dwmcore_2019_10.asm @@ -0,0 +1,82 @@ +// +// Generated by Microsoft (R) HLSL Shader Compiler 9.25.950.2675 +// +// using 3Dmigoto v1.3.16 on Wed Feb 09 18:55:49 2022 +// +// +// Buffer Definitions: +// +// cbuffer cbPSUpdateEveryCall +// { +// +// struct +// { +// +// struct +// { +// +// float4x4 mat4x4; // Offset: 0 +// float4 matRow4; // Offset: 64 +// +// } TransformColor_PS2_ConstantTable;// Offset: 0 +// +// } Data_PS; // Offset: 0 Size: 80 +// +// } +// +// +// Resource Bindings: +// +// Name Type Format Dim Slot Elements +// ------------------------------ ---------- ------- ----------- ---- -------- +// cbPSUpdateEveryCall cbuffer NA NA 0 1 +// +// +// +// Input signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// SV_POSITION 0 xyzw 0 POS float +// TEXCOORD 0 xyzw 1 NONE float +// TEXCOORD 1 xyzw 2 NONE float xyzw +// +// +// Output signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// SV_Target 0 xyzw 0 TARGET float xyzw +// +// +// Constant buffer to DX9 shader constant mappings: +// +// Target Reg Buffer Start Reg # of Regs Data Conversion +// ---------- ------- --------- --------- ---------------------- +// c0 cb0 0 5 ( FLT, FLT, FLT, FLT) +// +// +// Level9 shader bytecode: +// + ps_2_0 + dcl t1 + dp4 r0.x, t1, c0 + dp4 r0.y, t1, c1 + dp4 r0.z, t1, c2 + dp4 r0.w, t1, c3 + add r0, r0, c4 + mov oC0, r0 + +// approximately 6 instruction slots used +ps_4_0 +dcl_constantbuffer cb0[5], immediateIndexed +dcl_input_ps linear v2.xyzw +dcl_output o0.xyzw +dcl_temps 1 +dp4 r0.x, v2.xyzw, cb0[0].xyzw +dp4 r0.y, v2.xyzw, cb0[1].xyzw +dp4 r0.z, v2.xyzw, cb0[2].xyzw +dp4 r0.w, v2.xyzw, cb0[3].xyzw +add o0.xyzw, r0.xyzw, cb0[4].xyzw +ret +// Approximately 6 instruction slots used |