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path: root/disassembly/dwmcore_1010_10.asm
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diff --git a/disassembly/dwmcore_1010_10.asm b/disassembly/dwmcore_1010_10.asm
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+++ b/disassembly/dwmcore_1010_10.asm
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+//
+// Generated by Microsoft (R) HLSL Shader Compiler 9.25.950.2675
+//
+// using 3Dmigoto v1.3.16 on Wed Feb 09 18:55:49 2022
+//
+//
+// Buffer Definitions:
+//
+// cbuffer cbVSUpdateEveryCall
+// {
+//
+// struct
+// {
+//
+// struct
+// {
+//
+// float4x4 mat4x4WorldToProjection;// Offset: 0
+//
+// } Transform_World2D_By_Matrix4x4_VS0_ConstantTable;// Offset: 0
+//
+// } Data_VS; // Offset: 0 Size: 64
+//
+// }
+//
+//
+// Resource Bindings:
+//
+// Name Type Format Dim Slot Elements
+// ------------------------------ ---------- ------- ----------- ---- --------
+// cbVSUpdateEveryCall cbuffer NA NA 0 1
+//
+//
+//
+// Input signature:
+//
+// Name Index Mask Register SysValue Format Used
+// -------------------- ----- ------ -------- -------- ------- ------
+// POSITION 0 xyz 0 NONE float xyz
+// TEXCOORD 0 xyzw 1 NONE float xyzw
+// TEXCOORD 1 xy 2 NONE float
+// TEXCOORD 2 xy 3 NONE float
+//
+//
+// Output signature:
+//
+// Name Index Mask Register SysValue Format Used
+// -------------------- ----- ------ -------- -------- ------- ------
+// SV_POSITION 0 xyzw 0 POS float xyzw
+// TEXCOORD 0 xyzw 1 NONE float xyzw
+// TEXCOORD 1 xyzw 2 NONE float xyzw
+// TEXCOORD 2 xyzw 3 NONE float xyzw
+// TEXCOORD 3 xyzw 4 NONE float xyzw
+//
+//
+// Constant buffer to DX9 shader constant mappings:
+//
+// Target Reg Buffer Start Reg # of Regs Data Conversion
+// ---------- ------- --------- --------- ----------------------
+// c1 cb0 0 4 ( FLT, FLT, FLT, FLT)
+//
+//
+// Runtime generated constant mappings:
+//
+// Target Reg Constant Description
+// ---------- --------------------------------------------------
+// c0 Vertex Shader position offset
+//
+//
+// Level9 shader bytecode:
+//
+ vs_2_0
+ def c5, 1, 0, 0, 0
+ dcl_texcoord v0
+ dcl_texcoord1 v1
+ mad r0, v0.xyzx, c5.xxxy, c5.yyyx
+ dp4 oPos.z, r0, c3
+ dp4 r1.x, r0, c1
+ dp4 r1.y, r0, c2
+ dp4 r0.x, r0, c4
+ mad oPos.xy, r0.x, c0, r1
+ mov oPos.w, r0.x
+ mov oT0, c5.x
+ mov oT1, v1
+ mov oT2, v1
+ mov oT3, v1
+
+// approximately 11 instruction slots used
+vs_4_0
+dcl_constantbuffer cb0[4], immediateIndexed
+dcl_input v0.xyz
+dcl_input v1.xyzw
+dcl_output_siv o0.xyzw, position
+dcl_output o1.xyzw
+dcl_output o2.xyzw
+dcl_output o3.xyzw
+dcl_output o4.xyzw
+dcl_temps 1
+mov r0.xyz, v0.xyzx
+mov r0.w, l(1.000000)
+dp4 o0.x, r0.xyzw, cb0[0].xyzw
+dp4 o0.y, r0.xyzw, cb0[1].xyzw
+dp4 o0.z, r0.xyzw, cb0[2].xyzw
+dp4 o0.w, r0.xyzw, cb0[3].xyzw
+mov o1.xyzw, l(1.000000,1.000000,1.000000,1.000000)
+mov o2.xyzw, v1.xyzw
+mov o3.xyzw, v1.xyzw
+mov o4.xyzw, v1.xyzw
+ret
+// Approximately 11 instruction slots used