diff options
Diffstat (limited to 'disassembly/dwmcore_1006_10.asm')
| -rw-r--r-- | disassembly/dwmcore_1006_10.asm | 107 |
1 files changed, 107 insertions, 0 deletions
diff --git a/disassembly/dwmcore_1006_10.asm b/disassembly/dwmcore_1006_10.asm new file mode 100644 index 0000000..1d4e8df --- /dev/null +++ b/disassembly/dwmcore_1006_10.asm @@ -0,0 +1,107 @@ +// +// Generated by Microsoft (R) HLSL Shader Compiler 9.25.950.2675 +// +// using 3Dmigoto v1.3.16 on Wed Feb 09 18:55:49 2022 +// +// +// +// Input signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// POSITION 0 xyz 0 NONE float xyz +// TEXCOORD 0 xyzw 1 NONE float xyzw +// TEXCOORD 1 xy 2 NONE float xy +// TEXCOORD 2 xy 3 NONE float xy +// TEXCOORD 3 xy 4 NONE float xy +// TEXCOORD 4 xy 5 NONE float xy +// TEXCOORD 5 xy 6 NONE float xy +// TEXCOORD 6 xy 7 NONE float xy +// TEXCOORD 7 xy 8 NONE float xy +// TEXCOORD 8 xy 9 NONE float xy +// +// +// Output signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// SV_POSITION 0 xyzw 0 POS float xyzw +// TEXCOORD 0 xyzw 1 NONE float xyzw +// TEXCOORD 1 xy 2 NONE float xy +// TEXCOORD 2 zw 2 NONE float zw +// TEXCOORD 3 xy 3 NONE float xy +// TEXCOORD 4 zw 3 NONE float zw +// TEXCOORD 5 xy 4 NONE float xy +// TEXCOORD 6 zw 4 NONE float zw +// TEXCOORD 7 xy 5 NONE float xy +// TEXCOORD 8 zw 5 NONE float zw +// +// +// Runtime generated constant mappings: +// +// Target Reg Constant Description +// ---------- -------------------------------------------------- +// c0 Vertex Shader position offset +// +// +// Level9 shader bytecode: +// + vs_2_0 + def c1, 1, 0, 0, 0 + dcl_texcoord v0 + dcl_texcoord1 v1 + dcl_texcoord2 v2 + dcl_texcoord3 v3 + dcl_texcoord4 v4 + dcl_texcoord5 v5 + dcl_texcoord6 v6 + dcl_texcoord7 v7 + dcl_normal v8 + dcl_normal1 v9 + add oPos.xy, v0, c0 + mad oPos.zw, v0.z, c1.xyxy, c1.xyyx + mov oT0, v1 + mov oT1.xy, v2 + mov oT1.zw, v3.xyyx + mov oT2.xy, v4 + mov oT2.zw, v5.xyyx + mov oT3.xy, v6 + mov oT3.zw, v7.xyyx + mov oT4.xy, v8 + mov oT4.zw, v9.xyyx + +// approximately 11 instruction slots used +vs_4_0 +dcl_input v0.xyz +dcl_input v1.xyzw +dcl_input v2.xy +dcl_input v3.xy +dcl_input v4.xy +dcl_input v5.xy +dcl_input v6.xy +dcl_input v7.xy +dcl_input v8.xy +dcl_input v9.xy +dcl_output_siv o0.xyzw, position +dcl_output o1.xyzw +dcl_output o2.xy +dcl_output o2.zw +dcl_output o3.xy +dcl_output o3.zw +dcl_output o4.xy +dcl_output o4.zw +dcl_output o5.xy +dcl_output o5.zw +mov o0.xyz, v0.xyzx +mov o0.w, l(1.000000) +mov o1.xyzw, v1.xyzw +mov o2.xy, v2.xyxx +mov o2.zw, v3.xxxy +mov o3.xy, v4.xyxx +mov o3.zw, v5.xxxy +mov o4.xy, v6.xyxx +mov o4.zw, v7.xxxy +mov o5.xy, v8.xyxx +mov o5.zw, v9.xxxy +ret +// Approximately 12 instruction slots used |