[BZ #6411]

2008-11-13  Ryan S. Arnold  <rsa@us.ibm.com>
	[BZ #6411]
	* sysdeps/powerpc/fpu/Makefile: Added test case tst-setcontext-fpscr.
	* sysdeps/powerpc/fpu/feholdexcpt.c (_FPU_MASK_ALL): Define to replace
	magic numbers.
	* sysdeps/powerpc/fpu/fenv_libc.h (fesetenv_register): Dynamically
	choose mtfsf insn based on PPC_FEATURE_HAS_DFP.
	(relax_fenv_state): Same as above.
	(FPSCR_29): Reserve bit in ISA 2.05.
	(FPSCR_NI): Provide define for compat.
	* sysdeps/powerpc/fpu/fesetenv.c (_FPU_MASK_ALL): Define to replace
	magic numbers.
	* sysdeps/powerpc/fpu/feupdateenv.c (_FPU_MASK_ALL): Define to replace
	magic numbers.
	* sysdeps/powerpc/fpu/tst-setcontext-fpscr.c: New file.  Test case to
	test setcontext and swapcontext with dynamic 64-bit FPSCR detection.
	* sysdeps/powerpc/powerpc32/fpu/__longjmp-common.S (__longjmp): Adjust
	access to hwcap to account for hwcap size increase to uint64_t.
	* sysdeps/powerpc/powerpc32/fpu/setjmp-common.S (__sigsetjmp ):
	Likewise.
	* sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S
	(*setcontext): Likewise.
	* sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/setcontext.S:
	New file.
	* sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/swapcontext.S:
	New file.
	* sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S
	(*setcontext): dynamically select mtfsf insn based on
	PPC_FEATURE_HAS_DFP. Adjust access to hwcap to account for hwcap size
	increase to uint64_t.
	* sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S
	(*swapcontext): dynamically select mtfsf insn based on
	PPC_FEATURE_HAS_DFP.  Adjust access to hwcap to account for hwcap size
	increase to uint64_t.
	* sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/setcontext.S:
	New file.
	* sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/swapcontext.S:
	New file.
	* sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S
	(*setcontext): dynamically select mtfsf insn based on
	PPC_FEATURE_HAS_DFP.
	* sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S
	(*swapcontext): dynamically select mtfsf insn based on
	PPC_FEATURE_HAS_DFP.

1 files changed, 48 insertions, 10 deletions

diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S b/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S
index 48e9af363d..b4e28b4813 100644
--- a/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S
+++ b/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S
@@ -1,5 +1,5 @@
 /* Switch to context.
-   Copyright (C) 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
+   Copyright (C) 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
    This file is part of the GNU C Library.
 
    The GNU C Library is free software; you can redistribute it and/or
@@ -27,6 +27,15 @@
 #include "ucontext_i.h"
 #include <asm/errno.h>
 
+	.section	".toc","aw"
+.LC__dl_hwcap:
+#ifdef SHARED
+	.tc _rtld_global_ro[TC],_rtld_global_ro
+#else
+	.tc _dl_hwcap[TC],_dl_hwcap
+#endif
+	.section ".text"
+
 #if SHLIB_COMPAT (libc, GLIBC_2_3, GLIBC_2_3_4)
 ENTRY(__novec_setcontext)
 	CALL_MCOUNT 1
@@ -62,10 +71,32 @@ ENTRY(__novec_setcontext)
   cmpdi r3,0
   bne   L(nv_error_exit)
 
+# ifdef SHARED
+/* Load _rtld-global._dl_hwcap.  */
+  ld    r5,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r5)
+# else
+  ld    r5,0(r5) /* Load extern _dl_hwcap.  */
+# endif
+
   lfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
   lfd  fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
   lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
+
+# ifdef _ARCH_PWR6
+  /* Use the extended four-operand version of the mtfsf insn.  */
+  mtfsf  0xff,fp0,1,0
+# else
+  /* Availability of DFP indicates a 64-bit FPSCR.  */
+  andi.  r6,r5,PPC_FEATURE_HAS_DFP
+  beq    5f
+  /* Use the extended four-operand version of the mtfsf insn.  */
+  mtfsf  0xff,fp0,1,0
+  b      6f
+  /* Continue to operate on the FPSCR as if it were 32-bits.  */
+5:
   mtfsf  0xff,fp0
+6:
+# endif /* _ARCH_PWR6 */
   lfd  fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
   lfd  fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
   lfd  fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
@@ -189,15 +220,7 @@ compat_symbol (libc, __novec_setcontext, setcontext, GLIBC_2_3)
 
 #endif
 
-	.section	".toc","aw"
-.LC__dl_hwcap:
-#ifdef SHARED
-	.tc _rtld_global_ro[TC],_rtld_global_ro
-#else
-	.tc _dl_hwcap[TC],_dl_hwcap
-#endif
 	.section ".text"
-
 	.machine	"altivec"
 ENTRY(__setcontext)
 	CALL_MCOUNT 1
@@ -241,7 +264,7 @@ ENTRY(__setcontext)
 # else
   ld    r5,0(r5) /* Load extern _dl_hwcap.  */
 # endif
-  andis.  r5,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
+  andis.  r6,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
   beq   L(has_no_vec)
 
   cmpdi r10,0
@@ -346,7 +369,22 @@ L(has_no_vec):
   lfd  fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
   lfd  fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
   lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
+
+# ifdef _ARCH_PWR6
+  /* Use the extended four-operand version of the mtfsf insn.  */
+  mtfsf  0xff,fp0,1,0
+# else
+  /* Availability of DFP indicates a 64-bit FPSCR.  */
+  andi.  r6,r5,PPC_FEATURE_HAS_DFP
+  beq    7f
+  /* Use the extended four-operand version of the mtfsf insn.  */
+  mtfsf  0xff,fp0,1,0
+  b      8f
+  /* Continue to operate on the FPSCR as if it were 32-bits.  */
+7:
   mtfsf  0xff,fp0
+8:
+# endif /* _ARCH_PWR6 */
   lfd  fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
   lfd  fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
   lfd  fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)