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authorUlrich Drepper <drepper@redhat.com>2008-11-17 02:49:45 +0000
committerUlrich Drepper <drepper@redhat.com>2008-11-17 02:49:45 +0000
commitedba7a54eb83c37610b15454a21d54f47ec9dee7 (patch)
tree6c32b62c4db53ba9eb080ae34ea1fee5aefcba93 /sysdeps/unix
parentf52bb4d77eee0b7805ad57c069f29b544baa2db7 (diff)
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[BZ #6411]
2008-11-13 Ryan S. Arnold <rsa@us.ibm.com> [BZ #6411] * sysdeps/powerpc/fpu/Makefile: Added test case tst-setcontext-fpscr. * sysdeps/powerpc/fpu/feholdexcpt.c (_FPU_MASK_ALL): Define to replace magic numbers. * sysdeps/powerpc/fpu/fenv_libc.h (fesetenv_register): Dynamically choose mtfsf insn based on PPC_FEATURE_HAS_DFP. (relax_fenv_state): Same as above. (FPSCR_29): Reserve bit in ISA 2.05. (FPSCR_NI): Provide define for compat. * sysdeps/powerpc/fpu/fesetenv.c (_FPU_MASK_ALL): Define to replace magic numbers. * sysdeps/powerpc/fpu/feupdateenv.c (_FPU_MASK_ALL): Define to replace magic numbers. * sysdeps/powerpc/fpu/tst-setcontext-fpscr.c: New file. Test case to test setcontext and swapcontext with dynamic 64-bit FPSCR detection. * sysdeps/powerpc/powerpc32/fpu/__longjmp-common.S (__longjmp): Adjust access to hwcap to account for hwcap size increase to uint64_t. * sysdeps/powerpc/powerpc32/fpu/setjmp-common.S (__sigsetjmp ): Likewise. * sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S (*setcontext): Likewise. * sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/setcontext.S: New file. * sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/swapcontext.S: New file. * sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S (*setcontext): dynamically select mtfsf insn based on PPC_FEATURE_HAS_DFP. Adjust access to hwcap to account for hwcap size increase to uint64_t. * sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S (*swapcontext): dynamically select mtfsf insn based on PPC_FEATURE_HAS_DFP. Adjust access to hwcap to account for hwcap size increase to uint64_t. * sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/setcontext.S: New file. * sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/swapcontext.S: New file. * sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S (*setcontext): dynamically select mtfsf insn based on PPC_FEATURE_HAS_DFP. * sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S (*swapcontext): dynamically select mtfsf insn based on PPC_FEATURE_HAS_DFP.
Diffstat (limited to 'sysdeps/unix')
-rw-r--r--sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S8
-rw-r--r--sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/setcontext.S2
-rw-r--r--sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/swapcontext.S2
-rw-r--r--sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S50
-rw-r--r--sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S60
-rw-r--r--sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/setcontext.S2
-rw-r--r--sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/swapcontext.S2
-rw-r--r--sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S58
-rw-r--r--sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S58
9 files changed, 176 insertions, 66 deletions
diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S b/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S
index c28c34664c..63e1773e22 100644
--- a/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S
+++ b/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S
@@ -157,15 +157,15 @@ ENTRY(__CONTEXT_FUNC_NAME)
# ifdef SHARED
lwz r7,_rtld_global_ro@got(r7)
mtlr r8
- lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r7)
+ lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+4(r7)
# else
lwz r7,_dl_hwcap@got(r7)
mtlr r8
- lwz r7,0(r7)
+ lwz r7,4(r7)
# endif
# else
- lis r7,_dl_hwcap@ha
- lwz r7,_dl_hwcap@l(r7)
+ lis r7,(_dl_hwcap+4)@ha
+ lwz r7,(_dl_hwcap+4)@l(r7)
# endif
andis. r7,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/setcontext.S b/sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/setcontext.S
new file mode 100644
index 0000000000..7e44cdf0a1
--- /dev/null
+++ b/sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/setcontext.S
@@ -0,0 +1,2 @@
+#define _ARCH_PWR6
+#include_next <setcontext.S>
diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/swapcontext.S b/sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/swapcontext.S
new file mode 100644
index 0000000000..616e3db872
--- /dev/null
+++ b/sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/swapcontext.S
@@ -0,0 +1,2 @@
+#define _ARCH_PWR6
+#include_next <swapcontext.S>
diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S b/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S
index 40a7a24f19..91ac4366c0 100644
--- a/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S
+++ b/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S
@@ -1,5 +1,5 @@
/* Jump to a new context powerpc32 common.
- Copyright (C) 2005, 2006 Free Software Foundation, Inc.
+ Copyright (C) 2005, 2006, 2008 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -71,33 +71,34 @@ ENTRY(__CONTEXT_FUNC_NAME)
cmpwi r3,0
bne 3f /* L(error_exit) */
-#ifdef __CONTEXT_ENABLE_FPRS
-# ifdef __CONTEXT_ENABLE_VRS
-# ifdef PIC
+#ifdef PIC
mflr r8
-# ifdef HAVE_ASM_PPC_REL16
+# ifdef HAVE_ASM_PPC_REL16
bcl 20,31,1f
1: mflr r7
addis r7,r7,_GLOBAL_OFFSET_TABLE_-1b@ha
addi r7,r7,_GLOBAL_OFFSET_TABLE_-1b@l
-# else
+# else
bl _GLOBAL_OFFSET_TABLE_@local-4
mflr r7
-# endif
-# ifdef SHARED
+# endif
+# ifdef SHARED
lwz r7,_rtld_global_ro@got(r7)
mtlr r8
- lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r7)
-# else
+ lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+4(r7)
+# else
lwz r7,_dl_hwcap@got(r7)
mtlr r8
- lwz r7,0(r7)
-# endif
-# else
- lis r7,_dl_hwcap@ha
- lwz r7,_dl_hwcap@l(r7)
-# endif
- andis. r7,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
+ lwz r7,4(r7)
+# endif
+#else
+ lis r7,(_dl_hwcap+4)@ha
+ lwz r7,(_dl_hwcap+4)@l(r7)
+#endif
+
+#ifdef __CONTEXT_ENABLE_FPRS
+# ifdef __CONTEXT_ENABLE_VRS
+ andis. r6,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
la r10,(_UC_VREGS)(r31)
beq 2f /* L(has_no_vec) */
@@ -199,7 +200,20 @@ ENTRY(__CONTEXT_FUNC_NAME)
/* Restore the floating-point registers */
lfd fp31,_UC_FREGS+(32*8)(r31)
lfd fp0,_UC_FREGS+(0*8)(r31)
- mtfsf 0xff,fp31
+# ifdef _ARCH_PWR6
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+# else
+ /* Availability of DFP indicates a 64-bit FPSCR. */
+ andi. r6,r7,PPC_FEATURE_HAS_DFP
+ beq 7f
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp31,1,0
+ b 8f
+ /* Continue to operate on the FPSCR as if it were 32-bits. */
+7: mtfsf 0xff,fp31
+8:
+# endif /* _ARCH_PWR6 */
lfd fp1,_UC_FREGS+(1*8)(r31)
lfd fp2,_UC_FREGS+(2*8)(r31)
lfd fp3,_UC_FREGS+(3*8)(r31)
diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S b/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S
index 0c7b945ed2..77c982242a 100644
--- a/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S
+++ b/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S
@@ -1,5 +1,5 @@
/* Save current context and jump to a new context.
- Copyright (C) 2005, 2006 Free Software Foundation, Inc.
+ Copyright (C) 2005, 2006, 2008 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -143,33 +143,34 @@ ENTRY(__CONTEXT_FUNC_NAME)
stfd fp30,_UC_FREGS+(30*8)(r3)
stfd fp31,_UC_FREGS+(31*8)(r3)
stfd fp0,_UC_FREGS+(32*8)(r3)
-
-# ifdef __CONTEXT_ENABLE_VRS
-# ifdef PIC
+
+# ifdef PIC
mflr r8
-# ifdef HAVE_ASM_PPC_REL16
+# ifdef HAVE_ASM_PPC_REL16
bcl 20,31,1f
1: mflr r7
addis r7,r7,_GLOBAL_OFFSET_TABLE_-1b@ha
addi r7,r7,_GLOBAL_OFFSET_TABLE_-1b@l
-# else
+# else
bl _GLOBAL_OFFSET_TABLE_@local-4
mflr r7
-# endif
-# ifdef SHARED
+# endif
+# ifdef SHARED
lwz r7,_rtld_global_ro@got(r7)
mtlr r8
- lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r7)
-# else
+ lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+4(r7)
+# else
lwz r7,_dl_hwcap@got(r7)
mtlr r8
- lwz r7,0(r7)
-# endif
-# else
- lis r7,_dl_hwcap@ha
- lwz r7,_dl_hwcap@l(r7)
+ lwz r7,4(r7)
# endif
- andis. r7,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
+# else
+ lis r7,(_dl_hwcap+4)@ha
+ lwz r7,(_dl_hwcap+4)@l(r7)
+# endif
+
+# ifdef __CONTEXT_ENABLE_VRS
+ andis. r6,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
la r10,(_UC_VREGS)(r3)
la r9,(_UC_VREGS+16)(r3)
@@ -305,8 +306,8 @@ ENTRY(__CONTEXT_FUNC_NAME)
# ifdef HAVE_ASM_PPC_REL16
bcl 20,31,5f
5: mflr r7
- addis r7,r7,_GLOBAL_OFFSET_TABLE_-1b@ha
- addi r7,r7,_GLOBAL_OFFSET_TABLE_-1b@l
+ addis r7,r7,_GLOBAL_OFFSET_TABLE_-5b@ha
+ addi r7,r7,_GLOBAL_OFFSET_TABLE_-5b@l
# else
bl _GLOBAL_OFFSET_TABLE_@local-4
mflr r7
@@ -314,14 +315,14 @@ ENTRY(__CONTEXT_FUNC_NAME)
mtlr r8
# ifdef SHARED
lwz r7,_rtld_global_ro@got(r7)
- lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r7)
+ lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+4(r7)
# else
lwz r7,_dl_hwcap@got(r7)
- lwz r7,0(r7)
+ lwz r7,4(r7)
# endif
# else
- lis r7,_dl_hwcap@ha
- lwz r7,_dl_hwcap@l(r7)
+ lis r7,(_dl_hwcap+4)@ha
+ lwz r7,(_dl_hwcap+4)@l(r7)
# endif
andis. r7,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
la r10,(_UC_VREGS)(r31)
@@ -425,7 +426,20 @@ ENTRY(__CONTEXT_FUNC_NAME)
/* Restore the floating-point registers */
lfd fp31,_UC_FREGS+(32*8)(r31)
lfd fp0,_UC_FREGS+(0*8)(r31)
- mtfsf 0xff,fp31
+# ifdef _ARCH_PWR6
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+# else
+ /* Availability of DFP indicates a 64-bit FPSCR. */
+ andi. r6,r7,PPC_FEATURE_HAS_DFP
+ beq 7f
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp31,1,0
+ b 8f
+ /* Continue to operate on the FPSCR as if it were 32-bits. */
+7: mtfsf 0xff,fp31
+8:
+#endif /* _ARCH_PWR6 */
lfd fp1,_UC_FREGS+(1*8)(r31)
lfd fp2,_UC_FREGS+(2*8)(r31)
lfd fp3,_UC_FREGS+(3*8)(r31)
diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/setcontext.S b/sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/setcontext.S
new file mode 100644
index 0000000000..7e44cdf0a1
--- /dev/null
+++ b/sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/setcontext.S
@@ -0,0 +1,2 @@
+#define _ARCH_PWR6
+#include_next <setcontext.S>
diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/swapcontext.S b/sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/swapcontext.S
new file mode 100644
index 0000000000..616e3db872
--- /dev/null
+++ b/sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/swapcontext.S
@@ -0,0 +1,2 @@
+#define _ARCH_PWR6
+#include_next <swapcontext.S>
diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S b/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S
index 48e9af363d..b4e28b4813 100644
--- a/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S
+++ b/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S
@@ -1,5 +1,5 @@
/* Switch to context.
- Copyright (C) 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
+ Copyright (C) 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -27,6 +27,15 @@
#include "ucontext_i.h"
#include <asm/errno.h>
+ .section ".toc","aw"
+.LC__dl_hwcap:
+#ifdef SHARED
+ .tc _rtld_global_ro[TC],_rtld_global_ro
+#else
+ .tc _dl_hwcap[TC],_dl_hwcap
+#endif
+ .section ".text"
+
#if SHLIB_COMPAT (libc, GLIBC_2_3, GLIBC_2_3_4)
ENTRY(__novec_setcontext)
CALL_MCOUNT 1
@@ -62,10 +71,32 @@ ENTRY(__novec_setcontext)
cmpdi r3,0
bne L(nv_error_exit)
+# ifdef SHARED
+/* Load _rtld-global._dl_hwcap. */
+ ld r5,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r5)
+# else
+ ld r5,0(r5) /* Load extern _dl_hwcap. */
+# endif
+
lfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
lfd fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
lfd fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
+
+# ifdef _ARCH_PWR6
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+# else
+ /* Availability of DFP indicates a 64-bit FPSCR. */
+ andi. r6,r5,PPC_FEATURE_HAS_DFP
+ beq 5f
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+ b 6f
+ /* Continue to operate on the FPSCR as if it were 32-bits. */
+5:
mtfsf 0xff,fp0
+6:
+# endif /* _ARCH_PWR6 */
lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
@@ -189,15 +220,7 @@ compat_symbol (libc, __novec_setcontext, setcontext, GLIBC_2_3)
#endif
- .section ".toc","aw"
-.LC__dl_hwcap:
-#ifdef SHARED
- .tc _rtld_global_ro[TC],_rtld_global_ro
-#else
- .tc _dl_hwcap[TC],_dl_hwcap
-#endif
.section ".text"
-
.machine "altivec"
ENTRY(__setcontext)
CALL_MCOUNT 1
@@ -241,7 +264,7 @@ ENTRY(__setcontext)
# else
ld r5,0(r5) /* Load extern _dl_hwcap. */
# endif
- andis. r5,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
+ andis. r6,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
beq L(has_no_vec)
cmpdi r10,0
@@ -346,7 +369,22 @@ L(has_no_vec):
lfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
lfd fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
lfd fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
+
+# ifdef _ARCH_PWR6
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+# else
+ /* Availability of DFP indicates a 64-bit FPSCR. */
+ andi. r6,r5,PPC_FEATURE_HAS_DFP
+ beq 7f
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+ b 8f
+ /* Continue to operate on the FPSCR as if it were 32-bits. */
+7:
mtfsf 0xff,fp0
+8:
+# endif /* _ARCH_PWR6 */
lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S b/sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S
index 936d641b6b..c42ccfbe44 100644
--- a/sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S
+++ b/sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S
@@ -1,5 +1,5 @@
/* Save current context and install the given one.
- Copyright (C) 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
+ Copyright (C) 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -27,7 +27,16 @@
#include "ucontext_i.h"
#include <asm/errno.h>
+ .section ".toc","aw"
+.LC__dl_hwcap:
+#ifdef SHARED
+ .tc _rtld_global_ro[TC],_rtld_global_ro
+#else
+ .tc _dl_hwcap[TC],_dl_hwcap
+#endif
+
#if SHLIB_COMPAT (libc, GLIBC_2_3, GLIBC_2_3_4)
+ .section ".text"
ENTRY(__novec_swapcontext)
CALL_MCOUNT 2
#ifdef __ASSUME_NEW_RT_SIGRETURN_SYSCALL
@@ -157,10 +166,31 @@ ENTRY(__novec_swapcontext)
cmpdi r0,0
bne L(nv_do_sigret)
+# ifdef SHARED
+/* Load _rtld-global._dl_hwcap. */
+ ld r8,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r8)
+# else
+ ld r8,0(r8) /* Load extern _dl_hwcap. */
+# endif
+
lfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
lfd fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
lfd fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
+# ifdef _ARCH_PWR6
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+# else
+ /* Availability of DFP indicates a 64-bit FPSCR. */
+ andi. r6,r8,PPC_FEATURE_HAS_DFP
+ beq 5f
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+ b 6f
+ /* Continue to operate on the FPSCR as if it were 32-bits. */
+5:
mtfsf 0xff,fp0
+6:
+#endif /* _ARCH_PWR6 */
lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
@@ -283,15 +313,7 @@ compat_symbol (libc, __novec_swapcontext, swapcontext, GLIBC_2_3)
#endif
- .section ".toc","aw"
-.LC__dl_hwcap:
-#ifdef SHARED
- .tc _rtld_global_ro[TC],_rtld_global_ro
-#else
- .tc _dl_hwcap[TC],_dl_hwcap
-#endif
.section ".text"
-
.machine "altivec"
ENTRY(__swapcontext)
CALL_MCOUNT 2
@@ -409,7 +431,7 @@ ENTRY(__swapcontext)
la r10,(SIGCONTEXT_V_RESERVE+8)(r3)
la r9,(SIGCONTEXT_V_RESERVE+24)(r3)
- andis. r8,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
+ andis. r6,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
clrrdi r10,r10,4
beq L(has_no_vec)
@@ -540,7 +562,7 @@ L(has_no_vec):
# else
ld r8,0(r8) /* Load extern _dl_hwcap. */
# endif
- andis. r8,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
+ andis. r6,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
beq L(has_no_vec2)
cmpdi r10,0
@@ -646,7 +668,21 @@ L(has_no_vec2):
lfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
lfd fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
lfd fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
+# ifdef _ARCH_PWR6
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+# else
+ /* Availability of DFP indicates a 64-bit FPSCR. */
+ andi. r6,r8,PPC_FEATURE_HAS_DFP
+ beq 7f
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+ b 8f
+ /* Continue to operate on the FPSCR as if it were 32-bits. */
+7:
mtfsf 0xff,fp0
+8:
+#endif /* _ARCH_PWR6 */
lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)