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//
// Generated by Microsoft (R) HLSL Shader Compiler 9.25.950.2675
//
// using 3Dmigoto v1.3.16 on Wed Feb 09 18:55:49 2022
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// POSITION 0 xyz 0 NONE float xyz
// TEXCOORD 0 xyz 1 NONE float xyz
// TEXCOORD 1 xyzw 2 NONE float xyzw
// TEXCOORD 2 xyzw 3 NONE float xyzw
// TEXCOORD 3 xy 4 NONE float xy
// TEXCOORD 4 xy 5 NONE float xy
// TEXCOORD 5 xy 6 NONE float xy
// TEXCOORD 6 xy 7 NONE float xy
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_POSITION 0 xyzw 0 POS float xyzw
// TEXCOORD 0 xyz 1 NONE float xyz
// TEXCOORD 1 xyzw 2 NONE float xyzw
// TEXCOORD 2 xyzw 3 NONE float xyzw
// TEXCOORD 3 xy 4 NONE float xy
// TEXCOORD 4 zw 4 NONE float zw
// TEXCOORD 5 xy 5 NONE float xy
// TEXCOORD 6 zw 5 NONE float zw
//
//
// Runtime generated constant mappings:
//
// Target Reg Constant Description
// ---------- --------------------------------------------------
// c0 Vertex Shader position offset
//
//
// Level9 shader bytecode:
//
vs_2_0
def c1, 1, 0, 0, 0
dcl_texcoord v0
dcl_texcoord1 v1
dcl_texcoord2 v2
dcl_texcoord3 v3
dcl_texcoord4 v4
dcl_texcoord5 v5
dcl_texcoord6 v6
dcl_texcoord7 v7
add oPos.xy, v0, c0
mad oPos.zw, v0.z, c1.xyxy, c1.xyyx
mov oT0.xyz, v1
mov oT1, v2
mov oT2, v3
mov oT3.xy, v4
mov oT3.zw, v5.xyyx
mov oT4.xy, v6
mov oT4.zw, v7.xyyx
// approximately 9 instruction slots used
vs_4_0
dcl_input v0.xyz
dcl_input v1.xyz
dcl_input v2.xyzw
dcl_input v3.xyzw
dcl_input v4.xy
dcl_input v5.xy
dcl_input v6.xy
dcl_input v7.xy
dcl_output_siv o0.xyzw, position
dcl_output o1.xyz
dcl_output o2.xyzw
dcl_output o3.xyzw
dcl_output o4.xy
dcl_output o4.zw
dcl_output o5.xy
dcl_output o5.zw
mov o0.xyz, v0.xyzx
mov o0.w, l(1.000000)
mov o1.xyz, v1.xyzx
mov o2.xyzw, v2.xyzw
mov o3.xyzw, v3.xyzw
mov o4.xy, v4.xyxx
mov o4.zw, v5.xxxy
mov o5.xy, v6.xyxx
mov o5.zw, v7.xxxy
ret
// Approximately 10 instruction slots used
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