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authorUlrich Drepper <drepper@redhat.com>2004-04-04 03:32:19 +0000
committerUlrich Drepper <drepper@redhat.com>2004-04-04 03:32:19 +0000
commitecb2b2fb8aca5aacdae057257891e426d2f32b2f (patch)
tree28d6187066b9429015a806e14ce72c94e4f98d5f /sysdeps
parent1e084487ab208baf7ba690536bedaec0eafd44d4 (diff)
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Update.
* sysdeps/powerpc/powerpc64/bits/atomic.h: Never use matching constraints for asm mem parameters. * sysdeps/powerpc/bits/atomic.h: Likewise.
Diffstat (limited to 'sysdeps')
-rw-r--r--sysdeps/powerpc/bits/atomic.h14
-rw-r--r--sysdeps/powerpc/powerpc64/bits/atomic.h24
2 files changed, 19 insertions, 19 deletions
diff --git a/sysdeps/powerpc/bits/atomic.h b/sysdeps/powerpc/bits/atomic.h
index 5deb797256..4b6a761b72 100644
--- a/sysdeps/powerpc/bits/atomic.h
+++ b/sysdeps/powerpc/bits/atomic.h
@@ -1,5 +1,5 @@
/* Atomic operations. PowerPC Common version.
- Copyright (C) 2003 Free Software Foundation, Inc.
+ Copyright (C) 2003, 2004 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003.
@@ -53,7 +53,7 @@ typedef uintmax_t uatomic_max_t;
#define __arch_compare_and_exchange_bool_16_acq(mem, newval, oldval) \
(abort (), 0)
-
+
#define __arch_compare_and_exchange_bool_8_rel(mem, newval, oldval) \
(abort (), 0)
@@ -116,7 +116,7 @@ typedef uintmax_t uatomic_max_t;
" bne- 1b\n" \
" " __ARCH_ACQ_INSTR \
: "=&r" (__val), "=m" (*mem) \
- : "b" (mem), "r" (value), "1" (*mem) \
+ : "b" (mem), "r" (value), "m" (*mem) \
: "cr0", "memory"); \
__val; \
})
@@ -129,7 +129,7 @@ typedef uintmax_t uatomic_max_t;
" stwcx. %3,0,%2\n" \
" bne- 1b" \
: "=&r" (__val), "=m" (*mem) \
- : "b" (mem), "r" (value), "1" (*mem) \
+ : "b" (mem), "r" (value), "m" (*mem) \
: "cr0", "memory"); \
__val; \
})
@@ -142,7 +142,7 @@ typedef uintmax_t uatomic_max_t;
" stwcx. %1,0,%3\n" \
" bne- 1b" \
: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
- : "b" (mem), "r" (value), "2" (*mem) \
+ : "b" (mem), "r" (value), "m" (*mem) \
: "cr0", "memory"); \
__val; \
})
@@ -157,7 +157,7 @@ typedef uintmax_t uatomic_max_t;
" bne- 1b\n" \
"2: " __ARCH_ACQ_INSTR \
: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
- : "b" (mem), "2" (*mem) \
+ : "b" (mem), "m" (*mem) \
: "cr0", "memory"); \
__val; \
})
@@ -173,7 +173,7 @@ typedef uintmax_t uatomic_max_t;
abort (); \
__result; \
})
-
+
#define atomic_compare_and_exchange_val_rel(mem, newval, oldval) \
({ \
__typeof (*(mem)) __result; \
diff --git a/sysdeps/powerpc/powerpc64/bits/atomic.h b/sysdeps/powerpc/powerpc64/bits/atomic.h
index 76be01edf2..16bb994601 100644
--- a/sysdeps/powerpc/powerpc64/bits/atomic.h
+++ b/sysdeps/powerpc/powerpc64/bits/atomic.h
@@ -1,5 +1,5 @@
/* Atomic operations. PowerPC64 version.
- Copyright (C) 2003 Free Software Foundation, Inc.
+ Copyright (C) 2003, 2004 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003.
@@ -61,8 +61,8 @@
__tmp != 0; \
})
-/*
- * Only powerpc64 processors support Load doubleword and reserve index (ldarx)
+/*
+ * Only powerpc64 processors support Load doubleword and reserve index (ldarx)
* and Store doubleword conditional indexed (stdcx) instructions. So here
* we define the 64-bit forms.
*/
@@ -141,7 +141,7 @@
" bne- 1b\n" \
" " __ARCH_ACQ_INSTR \
: "=&r" (__val), "=m" (*mem) \
- : "b" (mem), "r" (value), "1" (*mem) \
+ : "b" (mem), "r" (value), "m" (*mem) \
: "cr0", "memory"); \
__val; \
})
@@ -154,7 +154,7 @@
" stdcx. %3,0,%2\n" \
" bne- 1b" \
: "=&r" (__val), "=m" (*mem) \
- : "b" (mem), "r" (value), "1" (*mem) \
+ : "b" (mem), "r" (value), "m" (*mem) \
: "cr0", "memory"); \
__val; \
})
@@ -167,7 +167,7 @@
" stdcx. %1,0,%3\n" \
" bne- 1b" \
: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
- : "b" (mem), "r" (value), "2" (*mem) \
+ : "b" (mem), "r" (value), "m" (*mem) \
: "cr0", "memory"); \
__val; \
})
@@ -182,17 +182,17 @@
" bne- 1b\n" \
"2: " __ARCH_ACQ_INSTR \
: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
- : "b" (mem), "2" (*mem) \
+ : "b" (mem), "m" (*mem) \
: "cr0", "memory"); \
__val; \
})
-/*
- * All powerpc64 processors support the new "light weight" sync (lwsync).
+/*
+ * All powerpc64 processors support the new "light weight" sync (lwsync).
*/
# define atomic_read_barrier() __asm ("lwsync" ::: "memory")
-/*
- * "light weight" sync can also be used for the release barrier.
+/*
+ * "light weight" sync can also be used for the release barrier.
*/
# ifndef UP
# define __ARCH_REL_INSTR "lwsync"
@@ -200,6 +200,6 @@
/*
* Include the rest of the atomic ops macros which are common to both
- * powerpc32 and powerpc64.
+ * powerpc32 and powerpc64.
*/
#include_next <bits/atomic.h>