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authorNoah Goldstein <goldstein.w.n@gmail.com>2022-06-27 21:07:03 -0700
committerNoah Goldstein <goldstein.w.n@gmail.com>2022-06-28 08:24:56 -0700
commita3563f3f369878467dd74aeb360448119a7a4b41 (patch)
treef7d6d912e151e87145bca820ed40dea524bb3ff6 /sysdeps/x86
parentc1ada668a381e122ee37cb8be7f0637111f63ea7 (diff)
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x86: Add more feature definitions to isa-level.h
This commit doesn't change anything in itself. It is just to add definitions that will be needed by future patches.
Diffstat (limited to 'sysdeps/x86')
-rw-r--r--sysdeps/x86/isa-level.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
index f293aea906..77f9e2c0c3 100644
--- a/sysdeps/x86/isa-level.h
+++ b/sysdeps/x86/isa-level.h
@@ -67,15 +67,27 @@
/* Depending on the minimum ISA level, a feature check result can be a
compile-time constant.. */
+
+/* For CPU_FEATURE_USABLE_P. */
+
/* ISA level >= 4 guaranteed includes. */
#define AVX512F_X86_ISA_LEVEL 4
#define AVX512VL_X86_ISA_LEVEL 4
#define AVX512BW_X86_ISA_LEVEL 4
+#define AVX512DQ_X86_ISA_LEVEL 4
/* ISA level >= 3 guaranteed includes. */
#define AVX_X86_ISA_LEVEL 3
#define AVX2_X86_ISA_LEVEL 3
#define BMI2_X86_ISA_LEVEL 3
+#define MOVBE_X86_ISA_LEVEL 3
+
+/* ISA level >= 2 guaranteed includes. */
+#define SSE4_2_X86_ISA_LEVEL 2
+#define SSSE3_X86_ISA_LEVEL 2
+
+
+/* For X86_ISA_CPU_FEATURES_ARCH_P. */
/* NB: This feature is enabled when ISA level >= 3, which was disabled
for the following CPUs:
@@ -89,6 +101,9 @@
when ISA level < 3. */
#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
+/* Feature(s) enabled when ISA level >= 2. */
+#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
+
/* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
runtime checks. They differ in two ways.