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authorRichard Henderson <rth@redhat.com>2005-09-20 05:35:42 +0000
committerRichard Henderson <rth@redhat.com>2005-09-20 05:35:42 +0000
commitab209d3a5cdfe565602d4857696410bde4213ca3 (patch)
tree8676a29fee0aae02c3057c42eea57c62e82dafa0 /sysdeps/unix
parentcf56e3bb6b9b3162e646f06297be8e10ee52406c (diff)
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[BZ #1358] * sysdeps/unix/alpha/sysdep.h (inline_syscall1): Copy argument(s) to a temporary first. (inline_syscall2, inline_syscall3, inline_syscall4): Likewise. (inline_syscall5, inline_syscall6): Likewise.
2005-09-19 Richard Henderson <rth@redhat.com> [BZ #1358] * sysdeps/unix/alpha/sysdep.h (inline_syscall1): Copy argument(s) to a temporary first. (inline_syscall2, inline_syscall3, inline_syscall4): Likewise. (inline_syscall5, inline_syscall6): Likewise. * sysdeps/alpha/ldiv.S (lldiv): Add alias.
Diffstat (limited to 'sysdeps/unix')
-rw-r--r--sysdeps/unix/alpha/sysdep.h63
1 files changed, 42 insertions, 21 deletions
diff --git a/sysdeps/unix/alpha/sysdep.h b/sysdeps/unix/alpha/sysdep.h
index f9f1dd6e41..a154db8e41 100644
--- a/sysdeps/unix/alpha/sysdep.h
+++ b/sysdeps/unix/alpha/sysdep.h
@@ -242,9 +242,10 @@ __LABEL(name) \
register long _sc_0 inline_syscall_r0_asm; \
register long _sc_16 __asm__("$16"); \
register long _sc_19 __asm__("$19"); \
+ register long _tmp_16 = (long) (arg1); \
\
_sc_0 = name; \
- _sc_16 = (long) (arg1); \
+ _sc_16 = _tmp_16; \
__asm__ __volatile__ \
("callsys # %0 %1 <= %2 %3" \
: inline_syscall_r0_out_constraint (_sc_0), \
@@ -261,10 +262,12 @@ __LABEL(name) \
register long _sc_16 __asm__("$16"); \
register long _sc_17 __asm__("$17"); \
register long _sc_19 __asm__("$19"); \
+ register long _tmp_16 = (long) (arg1); \
+ register long _tmp_17 = (long) (arg2); \
\
_sc_0 = name; \
- _sc_16 = (long) (arg1); \
- _sc_17 = (long) (arg2); \
+ _sc_16 = _tmp_16; \
+ _sc_17 = _tmp_17; \
__asm__ __volatile__ \
("callsys # %0 %1 <= %2 %3 %4" \
: inline_syscall_r0_out_constraint (_sc_0), \
@@ -282,11 +285,14 @@ __LABEL(name) \
register long _sc_17 __asm__("$17"); \
register long _sc_18 __asm__("$18"); \
register long _sc_19 __asm__("$19"); \
+ register long _tmp_16 = (long) (arg1); \
+ register long _tmp_17 = (long) (arg2); \
+ register long _tmp_18 = (long) (arg3); \
\
_sc_0 = name; \
- _sc_16 = (long) (arg1); \
- _sc_17 = (long) (arg2); \
- _sc_18 = (long) (arg3); \
+ _sc_16 = _tmp_16; \
+ _sc_17 = _tmp_17; \
+ _sc_18 = _tmp_18; \
__asm__ __volatile__ \
("callsys # %0 %1 <= %2 %3 %4 %5" \
: inline_syscall_r0_out_constraint (_sc_0), \
@@ -305,12 +311,16 @@ __LABEL(name) \
register long _sc_17 __asm__("$17"); \
register long _sc_18 __asm__("$18"); \
register long _sc_19 __asm__("$19"); \
+ register long _tmp_16 = (long) (arg1); \
+ register long _tmp_17 = (long) (arg2); \
+ register long _tmp_18 = (long) (arg3); \
+ register long _tmp_19 = (long) (arg4); \
\
_sc_0 = name; \
- _sc_16 = (long) (arg1); \
- _sc_17 = (long) (arg2); \
- _sc_18 = (long) (arg3); \
- _sc_19 = (long) (arg4); \
+ _sc_16 = _tmp_16; \
+ _sc_17 = _tmp_17; \
+ _sc_18 = _tmp_18; \
+ _sc_19 = _tmp_19; \
__asm__ __volatile__ \
("callsys # %0 %1 <= %2 %3 %4 %5 %6" \
: inline_syscall_r0_out_constraint (_sc_0), \
@@ -330,13 +340,18 @@ __LABEL(name) \
register long _sc_18 __asm__("$18"); \
register long _sc_19 __asm__("$19"); \
register long _sc_20 __asm__("$20"); \
+ register long _tmp_16 = (long) (arg1); \
+ register long _tmp_17 = (long) (arg2); \
+ register long _tmp_18 = (long) (arg3); \
+ register long _tmp_19 = (long) (arg4); \
+ register long _tmp_20 = (long) (arg5); \
\
_sc_0 = name; \
- _sc_16 = (long) (arg1); \
- _sc_17 = (long) (arg2); \
- _sc_18 = (long) (arg3); \
- _sc_19 = (long) (arg4); \
- _sc_20 = (long) (arg5); \
+ _sc_16 = _tmp_16; \
+ _sc_17 = _tmp_17; \
+ _sc_18 = _tmp_18; \
+ _sc_19 = _tmp_19; \
+ _sc_20 = _tmp_20; \
__asm__ __volatile__ \
("callsys # %0 %1 <= %2 %3 %4 %5 %6 %7" \
: inline_syscall_r0_out_constraint (_sc_0), \
@@ -357,14 +372,20 @@ __LABEL(name) \
register long _sc_19 __asm__("$19"); \
register long _sc_20 __asm__("$20"); \
register long _sc_21 __asm__("$21"); \
+ register long _tmp_16 = (long) (arg1); \
+ register long _tmp_17 = (long) (arg2); \
+ register long _tmp_18 = (long) (arg3); \
+ register long _tmp_19 = (long) (arg4); \
+ register long _tmp_20 = (long) (arg5); \
+ register long _tmp_21 = (long) (arg6); \
\
_sc_0 = name; \
- _sc_16 = (long) (arg1); \
- _sc_17 = (long) (arg2); \
- _sc_18 = (long) (arg3); \
- _sc_19 = (long) (arg4); \
- _sc_20 = (long) (arg5); \
- _sc_21 = (long) (arg6); \
+ _sc_16 = _tmp_16; \
+ _sc_17 = _tmp_17; \
+ _sc_18 = _tmp_18; \
+ _sc_19 = _tmp_19; \
+ _sc_20 = _tmp_20; \
+ _sc_21 = _tmp_21; \
__asm__ __volatile__ \
("callsys # %0 %1 <= %2 %3 %4 %5 %6 %7 %8" \
: inline_syscall_r0_out_constraint (_sc_0), \