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| author | Aurelien Jarno <aurelien@aurel32.net> | 2016-06-30 21:18:34 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2016-07-01 16:36:41 +0200 |
| commit | 2cbec365663cd0e2fe21f77b1f5e20ae3ab5f538 (patch) | |
| tree | ed30c465de1490ec346b8ed458430d6b223f44aa /sysdeps/sparc/sparc64/fpu | |
| parent | f43cb35c9b3c35addc6dc0f1427caf51786ca1d2 (diff) | |
| download | glibc-2cbec365663cd0e2fe21f77b1f5e20ae3ab5f538.tar glibc-2cbec365663cd0e2fe21f77b1f5e20ae3ab5f538.tar.gz glibc-2cbec365663cd0e2fe21f77b1f5e20ae3ab5f538.tar.bz2 glibc-2cbec365663cd0e2fe21f77b1f5e20ae3ab5f538.zip | |
SPARC: fix nearbyint on sNaN input
nearbyint and nearbyintf should not trigger inexact exceptions, but
should still trigger an invalid exception for a sNaN input.
The SPARC specific implementations of these functions save the FSR at
the beginning of the function and restore it at the end to not trigger
an inexact exception. This however doesn't work for an sNaN input which
need to trigger an invalid exception. Fix that by adding a fcmp
instruction using the input value before saving FSR, so that an invalid
exception is triggered for a sNaN input.
This fixes the math/test-nearbyint-except test on SPARC.
Changelog:
* sparc/sparc32/sparcv9/fpu/s_nearbyint.S (__nearbyint): Trigger an
invalid exception for a sNaN input.
* sparc/sparc32/sparcv9/fpu/s_nearbyintf.S (__nearbyintf): Likewise.
* sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S
(__nearbyint_vis3): Likewise
* sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S
(__nearbyintf_vis3): Likewise
* sparc/sparc64/fpu/s_nearbyint.S (__nearbyint): Likewise.
* sparc/sparc64/fpu/s_nearbyintf.S (__nearbyintf): Likewise.
* sparc/sparc64/fpu/multiarch/s_nearbyint-vis3.S (__nearbyint_vis3):
Likewise.
* sparc/sparc64/fpu/multiarch/s_nearbyintf-vis3.S (__nearbyintf_vis3):
Likewise.
Diffstat (limited to 'sysdeps/sparc/sparc64/fpu')
| -rw-r--r-- | sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint-vis3.S | 1 | ||||
| -rw-r--r-- | sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf-vis3.S | 1 | ||||
| -rw-r--r-- | sysdeps/sparc/sparc64/fpu/s_nearbyint.S | 1 | ||||
| -rw-r--r-- | sysdeps/sparc/sparc64/fpu/s_nearbyintf.S | 1 |
4 files changed, 4 insertions, 0 deletions
diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint-vis3.S index fff277ae49..3180554f11 100644 --- a/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint-vis3.S +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint-vis3.S @@ -35,6 +35,7 @@ #define SIGN_BIT %f12 /* -0.0 */ ENTRY (__nearbyint_vis3) + fcmpd %fcc3, %f0, %f0 /* Check for sNaN */ stx %fsr, [%sp + STACK_BIAS + 144] sethi %hi(TWO_FIFTYTWO), %o2 sllx %o2, 32, %o2 diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf-vis3.S index c6e94ba73b..7bf7eedb9a 100644 --- a/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf-vis3.S +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf-vis3.S @@ -35,6 +35,7 @@ #define SIGN_BIT %f12 /* -0.0 */ ENTRY (__nearbyintf_vis3) + fcmps %fcc3, %f1, %f1 /* Check for sNaN */ stx %fsr, [%sp + STACK_BIAS + 144] sethi %hi(0xf8003e0), %o5 sethi %hi(TWO_TWENTYTHREE), %o2 diff --git a/sysdeps/sparc/sparc64/fpu/s_nearbyint.S b/sysdeps/sparc/sparc64/fpu/s_nearbyint.S index caf4d729e0..456c31565f 100644 --- a/sysdeps/sparc/sparc64/fpu/s_nearbyint.S +++ b/sysdeps/sparc/sparc64/fpu/s_nearbyint.S @@ -35,6 +35,7 @@ #define SIGN_BIT %f12 /* -0.0 */ ENTRY (__nearbyint) + fcmpd %fcc3, %f0, %f0 /* Check for sNaN */ stx %fsr, [%sp + STACK_BIAS + 144] sethi %hi(TWO_FIFTYTWO), %o2 sllx %o2, 32, %o2 diff --git a/sysdeps/sparc/sparc64/fpu/s_nearbyintf.S b/sysdeps/sparc/sparc64/fpu/s_nearbyintf.S index 4232eca9ad..d0d9bed3dd 100644 --- a/sysdeps/sparc/sparc64/fpu/s_nearbyintf.S +++ b/sysdeps/sparc/sparc64/fpu/s_nearbyintf.S @@ -35,6 +35,7 @@ #define SIGN_BIT %f12 /* -0.0 */ ENTRY (__nearbyintf) + fcmps %fcc3, %f1, %f1 /* Check for sNaN */ stx %fsr, [%sp + STACK_BIAS + 144] sethi %hi(0xf8003e0), %o5 sethi %hi(TWO_TWENTYTHREE), %o2 |