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| author | Anton Blanchard <anton@ozlabs.org> | 2021-07-27 15:47:50 +1000 |
|---|---|---|
| committer | Tulio Magno Quites Machado Filho <tuliom@linux.ibm.com> | 2021-08-06 16:09:59 -0300 |
| commit | f2a15dd668913c5a1388ba7e1131b25162b2ea75 (patch) | |
| tree | 0502041dd1875008f263ec0655b304acea5ff398 /sysdeps/powerpc/powerpc64/multiarch/memset.c | |
| parent | e4ca6de1bc5e4ba3f94cf0c501a293c5bc827b10 (diff) | |
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powerpc64: Check cacheline size before using optimised memset routines
A number of optimised memset routines assume the cacheline size is 128B,
so we better check before using them.
Reviewed-by: Tulio Magno Quites Machado Filho <tuliom@linux.ibm.com>
Diffstat (limited to 'sysdeps/powerpc/powerpc64/multiarch/memset.c')
| -rw-r--r-- | sysdeps/powerpc/powerpc64/multiarch/memset.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/sysdeps/powerpc/powerpc64/multiarch/memset.c b/sysdeps/powerpc/powerpc64/multiarch/memset.c index c1aa143f60..056e911699 100644 --- a/sysdeps/powerpc/powerpc64/multiarch/memset.c +++ b/sysdeps/powerpc/powerpc64/multiarch/memset.c @@ -43,16 +43,21 @@ libc_ifunc (__libc_memset, # ifdef __LITTLE_ENDIAN__ (hwcap2 & PPC_FEATURE2_ARCH_3_1 && hwcap2 & PPC_FEATURE2_HAS_ISEL - && hwcap & PPC_FEATURE_HAS_VSX) + && hwcap & PPC_FEATURE_HAS_VSX + && GLRO(dl_cache_line_size) == 128) ? __memset_power10 : # endif - (hwcap2 & PPC_FEATURE2_ARCH_2_07) + (hwcap2 & PPC_FEATURE2_ARCH_2_07 + && GLRO(dl_cache_line_size) == 128) ? __memset_power8 : - (hwcap & PPC_FEATURE_ARCH_2_06) + (hwcap & PPC_FEATURE_ARCH_2_06 + && GLRO(dl_cache_line_size) == 128) ? __memset_power7 : - (hwcap & PPC_FEATURE_ARCH_2_05) + (hwcap & PPC_FEATURE_ARCH_2_05 + && GLRO(dl_cache_line_size) == 128) ? __memset_power6 : - (hwcap & PPC_FEATURE_POWER4) + (hwcap & PPC_FEATURE_POWER4 + && GLRO(dl_cache_line_size) == 128) ? __memset_power4 : __memset_ppc); |