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| author | Anton Blanchard <anton@au1.ibm.com> | 2013-08-17 18:34:40 +0930 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2013-10-04 10:37:59 +0930 |
| commit | be1e5d311342e08ae1f8013342df27b7ded2c156 (patch) | |
| tree | ccf1ca254c3aa1392262c72de0b960eb1ec7ec21 /sysdeps/powerpc/powerpc64/__longjmp-common.S | |
| parent | fef13a78ea30d4c26d6bab48d731ebe864ee31b0 (diff) | |
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PowerPC LE setjmp/longjmp
http://sourceware.org/ml/libc-alpha/2013-08/msg00089.html
Little-endian fixes for setjmp/longjmp. When writing these I noticed
the setjmp code corrupts the non volatile VMX registers when using an
unaligned buffer. Anton fixed this, and also simplified it quite a
bit.
The current code uses boilerplate for the case where we want to store
16 bytes to an unaligned address. For that we have to do a
read/modify/write of two aligned 16 byte quantities. In our case we
are storing a bunch of back to back data (consective VMX registers),
and only the start and end of the region need the read/modify/write.
[BZ #15723]
* sysdeps/powerpc/jmpbuf-offsets.h: Comment fix.
* sysdeps/powerpc/powerpc32/fpu/__longjmp-common.S: Correct
_dl_hwcap access for little-endian.
* sysdeps/powerpc/powerpc32/fpu/setjmp-common.S: Likewise. Don't
destroy vmx regs when saving unaligned.
* sysdeps/powerpc/powerpc64/__longjmp-common.S: Correct CR load.
* sysdeps/powerpc/powerpc64/setjmp-common.S: Likewise CR save. Don't
destroy vmx regs when saving unaligned.
Diffstat (limited to 'sysdeps/powerpc/powerpc64/__longjmp-common.S')
| -rw-r--r-- | sysdeps/powerpc/powerpc64/__longjmp-common.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sysdeps/powerpc/powerpc64/__longjmp-common.S b/sysdeps/powerpc/powerpc64/__longjmp-common.S index 70c370439f..4f1e3c88d3 100644 --- a/sysdeps/powerpc/powerpc64/__longjmp-common.S +++ b/sysdeps/powerpc/powerpc64/__longjmp-common.S @@ -57,7 +57,7 @@ ENTRY (__longjmp) beq L(no_vmx) la r5,((JB_VRS)*8)(3) andi. r6,r5,0xf - lwz r0,((JB_VRSAVE)*8)(3) + lwz r0,((JB_VRSAVE)*8)(3) /* 32-bit VRSAVE. */ mtspr VRSAVE,r0 beq+ L(aligned_restore_vmx) addi r6,r5,16 @@ -153,7 +153,7 @@ L(no_vmx): lfd fp21,((JB_FPRS+7)*8)(r3) ld r22,((JB_GPRS+8)*8)(r3) lfd fp22,((JB_FPRS+8)*8)(r3) - ld r0,(JB_CR*8)(r3) + lwz r0,((JB_CR*8)+4)(r3) /* 32-bit CR. */ ld r23,((JB_GPRS+9)*8)(r3) lfd fp23,((JB_FPRS+9)*8)(r3) ld r24,((JB_GPRS+10)*8)(r3) |