diff options
| author | Will Newton <will.newton@linaro.org> | 2013-08-07 14:15:52 +0100 |
|---|---|---|
| committer | Will Newton <will.newton@linaro.org> | 2013-09-16 17:55:28 +0100 |
| commit | cd90698b541046c22544c2c057a4676368fd1d7f (patch) | |
| tree | 152f00ad520b5c8e106f821044f3b589da2a7872 /nptl/tst-cancelx4.c | |
| parent | f06dd27b0c61ea8905103c9391f0900fa896bd74 (diff) | |
| download | glibc-cd90698b541046c22544c2c057a4676368fd1d7f.tar glibc-cd90698b541046c22544c2c057a4676368fd1d7f.tar.gz glibc-cd90698b541046c22544c2c057a4676368fd1d7f.tar.bz2 glibc-cd90698b541046c22544c2c057a4676368fd1d7f.zip | |
ARM: Improve armv7 memcpy performance.
Only enter the aligned copy loop with buffers that can be 8-byte
aligned. This improves performance slightly on Cortex-A9 and
Cortex-A15 cores for large copies with buffers that are 4-byte
aligned but not 8-byte aligned.
ports/ChangeLog.arm:
2013-09-16 Will Newton <will.newton@linaro.org>
* sysdeps/arm/armv7/multiarch/memcpy_impl.S: Tighten check
on entry to aligned copy loop to improve performance.
Diffstat (limited to 'nptl/tst-cancelx4.c')
0 files changed, 0 insertions, 0 deletions