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| author | Sajan Karumanchi <sajan.karumanchi@amd.com> | 2023-08-01 15:20:55 +0000 |
|---|---|---|
| committer | Prem Mallappa <Premachandra.Mallappa@amd.com> | 2023-08-06 19:10:42 +0530 |
| commit | dcad5c8578130dec7f35fd5b0885304b59f9f543 (patch) | |
| tree | e32eda50e4f5de3a0397734892518709adeb387c /htl/pt-internal.h | |
| parent | 53850f044f65dd11efdf67a2ab214d312295d85c (diff) | |
| download | glibc-dcad5c8578130dec7f35fd5b0885304b59f9f543.tar glibc-dcad5c8578130dec7f35fd5b0885304b59f9f543.tar.gz glibc-dcad5c8578130dec7f35fd5b0885304b59f9f543.tar.bz2 glibc-dcad5c8578130dec7f35fd5b0885304b59f9f543.zip | |
x86: Fix for cache computation on AMD legacy cpus.
Some legacy AMD CPUs and hypervisors have the _cpuid_ '0x8000_001D'
set to Zero, thus resulting in zeroed-out computed cache values.
This patch reintroduces the old way of cache computation as a
fail-safe option to handle these exceptions.
Fixed 'level4_cache_size' value through handle_amd().
Reviewed-by: Premachandra Mallappa <premachandra.mallappa@amd.com>
Tested-by: Florian Weimer <fweimer@redhat.com>
Diffstat (limited to 'htl/pt-internal.h')
0 files changed, 0 insertions, 0 deletions