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| author | Harsha Jagasia <harsha.jagasia@amd.com> | 2011-03-04 23:30:08 -0500 |
|---|---|---|
| committer | Ulrich Drepper <drepper@gmail.com> | 2011-03-04 23:30:08 -0500 |
| commit | 7e4ba49cd365555ddaff2ae8bba7b912464ad6e5 (patch) | |
| tree | ec4eaf0ea436e74b584daefdceeb4ab66c52728d /ChangeLog | |
| parent | 13a804de8f3091e8ccd9b650f61becd6e1304227 (diff) | |
| download | glibc-7e4ba49cd365555ddaff2ae8bba7b912464ad6e5.tar glibc-7e4ba49cd365555ddaff2ae8bba7b912464ad6e5.tar.gz glibc-7e4ba49cd365555ddaff2ae8bba7b912464ad6e5.tar.bz2 glibc-7e4ba49cd365555ddaff2ae8bba7b912464ad6e5.zip | |
Enable SSE2 memset for AMD'supcoming Orochi processor.
This patch enables SSE2 memset for AMD's upcoming Orochi processor.
This patch also fixes the following bug:
For misaligned blocks larger than > 144 Bytes, memset branches into
the integer code path depending on the value of misalignment even if
the startup code chooses the SSE2 code path upfront, when multiarch
is enabled.
Diffstat (limited to 'ChangeLog')
| -rw-r--r-- | ChangeLog | 16 |
1 files changed, 15 insertions, 1 deletions
@@ -1,3 +1,17 @@ +2011-03-02 Harsha Jagasia <harsha.jagasia@amd.com> + Ulrich Drepper <drepper@gmail.com> + + * sysdeps/x86_64/memset.S: After aligning destination, code + branches to different locations depending on the value of + misalignment, when multiarch is enabled. Fix this. + +2011-03-02 Harsha Jagasia <harsha.jagasia@amd.com> + + * sysdeps/x86_64/cacheinfo.c (init_cacheinfo): + Set _x86_64_preferred_memory_instruction for AMD processsors. + * sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features): + Set bit_Prefer_SSE_for_memop for AMD processors. + 2011-03-04 Ulrich Drepper <drepper@gmail.com> * libio/fmemopen.c (fmemopen): Optimize a bit. @@ -12,7 +26,7 @@ 2011-02-28 Aurelien Jarno <aurelien@aurel32.net> - * sysdeps/sparc/sparc64/multiarch/memset.S(__bzero): call + * sysdeps/sparc/sparc64/multiarch/memset.S(__bzero): Call __bzero_ultra1 instead of __memset_ultra1. 2011-02-23 Andreas Schwab <schwab@redhat.com> |