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| author | H.J. Lu <hjl.tools@gmail.com> | 2016-05-19 10:02:36 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2016-05-19 10:02:36 -0700 |
| commit | de71e0421b4e267f9b6cf5a827ee5bab70226cd9 (patch) | |
| tree | 5fc28f7cded00f91262356bd505b16f986784e56 | |
| parent | 7c08d791ee4fabf96d96b66dec803602e621057c (diff) | |
| download | glibc-de71e0421b4e267f9b6cf5a827ee5bab70226cd9.tar glibc-de71e0421b4e267f9b6cf5a827ee5bab70226cd9.tar.gz glibc-de71e0421b4e267f9b6cf5a827ee5bab70226cd9.tar.bz2 glibc-de71e0421b4e267f9b6cf5a827ee5bab70226cd9.zip | |
Correct Intel processor level type mask from CPUID
Intel CPUID with EAX == 11 returns:
ECX Bits 07 - 00: Level number. Same value in ECX input.
Bits 15 - 08: Level type.
^^^^^^^^^^^^^^^^^^^^^^^^ This is level type.
Bits 31 - 16: Reserved.
Intel processor level type mask should be 0xff00, not 0xff0.
[BZ #20119]
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Correct Intel
processor level type mask for CPUID with EAX == 11.
| -rw-r--r-- | ChangeLog | 6 | ||||
| -rw-r--r-- | sysdeps/x86/cacheinfo.c | 2 |
2 files changed, 7 insertions, 1 deletions
@@ -1,5 +1,11 @@ 2016-05-19 H.J. Lu <hongjiu.lu@intel.com> + [BZ #20119] + * sysdeps/x86/cacheinfo.c (init_cacheinfo): Correct Intel + processor level type mask for CPUID with EAX == 11. + +2016-05-19 H.J. Lu <hongjiu.lu@intel.com> + * sysdeps/x86/cacheinfo.c (init_cacheinfo): Skip counting logical threads if the HTT bit is 0. * sysdeps/x86/cpu-features.h (bit_cpu_HTT): New. diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c index 1f46d9de20..020d3fd397 100644 --- a/sysdeps/x86/cacheinfo.c +++ b/sysdeps/x86/cacheinfo.c @@ -552,7 +552,7 @@ init_cacheinfo (void) __cpuid_count (11, i++, eax, ebx, ecx, edx); int shipped = ebx & 0xff; - int type = ecx & 0xff0; + int type = ecx & 0xff00; if (shipped == 0 || type == 0) break; else if (type == 0x200) |