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| author | H.J. Lu <hongjiu.lu@intel.com> | 2010-02-18 23:11:21 -0800 |
|---|---|---|
| committer | Ulrich Drepper <drepper@redhat.com> | 2010-02-18 23:11:21 -0800 |
| commit | 039c8ae6d5d54e1e677b317a0131480c6036a8e3 (patch) | |
| tree | 67aab8ac577c2e2bc62847d7f6ef320d1641f00e | |
| parent | 020ecba7fc0cde6febac28e114a56f9eb47dc871 (diff) | |
| download | glibc-039c8ae6d5d54e1e677b317a0131480c6036a8e3.tar glibc-039c8ae6d5d54e1e677b317a0131480c6036a8e3.tar.gz glibc-039c8ae6d5d54e1e677b317a0131480c6036a8e3.tar.bz2 glibc-039c8ae6d5d54e1e677b317a0131480c6036a8e3.zip | |
Use CPUID_OFFSET instead of FEATURE_OFFSET
| -rw-r--r-- | ChangeLog | 4 | ||||
| -rw-r--r-- | sysdeps/i386/i686/multiarch/memcmp.S | 2 | ||||
| -rw-r--r-- | sysdeps/i386/i686/multiarch/strcmp.S | 2 |
3 files changed, 6 insertions, 2 deletions
@@ -1,5 +1,9 @@ 2010-02-16 H.J. Lu <hongjiu.lu@intel.com> + * sysdeps/i386/i686/multiarch/memcmp.S (memcmp): Use CPUID_OFFSET + instead of FEATURE_OFFSET. + * sysdeps/i386/i686/multiarch/strcmp.S (strcmp): Likewise. + * sysdeps/i386/i686/multiarch/memcmp-sse4.S: Add alignnments. Fix one unwind info problem. diff --git a/sysdeps/i386/i686/multiarch/memcmp.S b/sysdeps/i386/i686/multiarch/memcmp.S index fa7c52a003..cf606a5959 100644 --- a/sysdeps/i386/i686/multiarch/memcmp.S +++ b/sysdeps/i386/i686/multiarch/memcmp.S @@ -58,7 +58,7 @@ ENTRY(memcmp) testl $bit_SSSE3, CPUID_OFFSET+index_SSSE3+__cpu_features jz 2f leal __memcmp_ssse3, %eax - testl $bit_SSE4_2, FEATURE_OFFSET+index_SSE4_2+__cpu_features + testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features jz 2f leal __memcmp_sse4_2, %eax 2: ret diff --git a/sysdeps/i386/i686/multiarch/strcmp.S b/sysdeps/i386/i686/multiarch/strcmp.S index 79a1fdfd43..7136d47e85 100644 --- a/sysdeps/i386/i686/multiarch/strcmp.S +++ b/sysdeps/i386/i686/multiarch/strcmp.S @@ -83,7 +83,7 @@ ENTRY(STRCMP) testl $bit_SSSE3, CPUID_OFFSET+index_SSSE3+__cpu_features jz 2f leal __STRCMP_SSSE3, %eax - testl $bit_SSE4_2, FEATURE_OFFSET+index_SSE4_2+__cpu_features + testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features jz 2f leal __STRCMP_SSE4_2, %eax 2: ret |