summaryrefslogtreecommitdiff
path: root/vpx_ports
AgeCommit message (Collapse)Author
2013-11-20Support for extended feature flags enumeration leaf in CPUID instructionErik Niemeyer
This CL fixes an overcite with the AVX2 support CL previously merged (Change-Id: Idc03f3fca4bf2d0afd33631ea1d3caf8fc34ec29) that prevented runtime execution of AVX2 code in WebM. Background: Starting with the Sandybridge processor, the CPUID instruction was enhanced to add various extended feature flag enumeration leaves. Reading these leaves requires an additional input value for the CPUID instruction which is stored in ECX. This change adds this second input value for all ARCH_X86 and ARCH_x86_64 targets to the CPUID macros, allowing checks of EBX bit 5 for AVX2 support. This capability will be required moving forward to check for future processor features. Change-Id: Ie9d872bc9ff68dad4b6578e4544e4dfd0ae26c36
2013-10-29CL for adding AVX-AVX2 support in libvpx.Erik Niemeyer
Change-Id: Idc03f3fca4bf2d0afd33631ea1d3caf8fc34ec29
2013-06-17vpx_ports/x86.h: de-dup #elif blockJames Zern
Change-Id: I052647e13dd24354888c890f6b4a987d989552ae
2013-05-01Merge "Add cpu detection for Android x86"Johann
2013-05-02Add cpu detection for Android x86changjun.yang
Change-Id: I3fe24001cda08d7322b630f65c5e3fad881f8036
2013-04-26code cleanup for arm_cpudetect.cchangjun.yang
Change-Id: I5c49a983ced45197e1035fa5615d71b0bdad4109
2013-03-05Code cleanup.Dmitry Kovalev
Removing redundant 'extern' keywords, fixing formatting and #include order, code simplification. Change-Id: I0e5fdc8009010f3f885f13b5d76859b9da511758
2013-01-31Add support for x64 and win64 yasm flags.Frank Galligan
Some projects must define only win64 for Windows 64bit builds using yasm. Change-Id: I1d09590d66a7bfc8b4412e1cc8685978ac60b748
2013-01-2564-bit Mac Chromium support for libvpx.Mark Mentovai
For 64-bit Mac Chromium, use private_extern for HIDDEN_DATA, the same as 32-bit Mac Chromium. Change-Id: Ica0fa9e48a47409facece691ae1e39327369083c
2013-01-14Use INT64_MAX instead of LLONG_MAXJohn Koleszar
These variables have the type int64_t, not long long. long long could be a larger type than 64 bits. Emulate INT64_MAX for older versions of MSVC, and remove the unreferenced vpx_ports/vpxtypes.h Change-Id: Ideaca71838fcd3849d816d5ab17aa347c97d03b0
2012-12-27Merge branch 'vp9-preview' of review:webm/libvpxJohn Koleszar
Merge the vp9-preview branch into master. Change-Id: If700b9054676f24bed9deb59050af546c1ca5296
2012-12-26Build fixes to merge vp9-preview into masterJohn Koleszar
Various fixups to resolve issues when building vp9-preview under the more stringent checks placed on the experimental branch. Change-Id: I21749de83552e1e75c799003f849e6a0f1a35b07
2012-12-20add emmintrin_compat.h for builds with gcc < 4James Zern
Change-Id: If7822e6fcd0d3568b934032322b19ba3e401df26
2012-12-11Revert "Upstream build bug for chromium"Johann
This reverts commit 8bb82fded57f6316fdfd103d565050d0f1286bc5. This is an incorrect workaround. It has been fixed in the GYP files upstream. Change-Id: If42f997747ce878b874508fdf7ae5a73a6fa1b2b
2012-11-19Upstream build bug for chromiumJohann
https://codereview.chromium.org/11413061/ The Android NDK automatically manages the include directories. Trying to do so manually for the Android GYP files can cause the wrong setjmp.h to be included. Change-Id: I5c3769f983fcbad1ed602feda781690c6e4e97b3
2012-11-15Sequester vpx_ports file listJohann
Move BUILD_LIBVPX evaluation before the include. Change-Id: I8860414c42a8161765a17bf433ff2607c0d027ca
2012-11-15support building vp8 and vp9 into a single libJohn Koleszar
Change-Id: Ib8f8a66c9fd31e508cdc9caa662192f38433aa3d
2012-11-07Rough merge of master into experimentalJohn Koleszar
Creates a merge between the master and experimental branches. Fixes a number of conflicts in the build system to allow *either* VP8 or VP9 to be built. Specifically either: $ configure --disable-vp9 $ configure --disable-vp8 --disable-unit-tests VP9 still exports its symbols and files as VP8, so that will be resolved in the next commit. Unit tests are broken in VP9, but this isn't a new issue. They are fixed upstream on origin/experimental as of this writing, but rebasing this merge proved difficult, so will tackle that in a second merge commit. Change-Id: I2b7d852c18efd58d1ebc621b8041fe0260442c21
2012-11-05vpx_ports: merge with masterJohn Koleszar
Change-Id: I25c067326153455abe1a79f8f44f70b87350e655
2012-09-25check for x32 targetsMike Frysinger
Add configure detection of the new x32 ABI as well as support in asm. Change-Id: Ic66a069599adeb81062090e3f11b71ee1fb97cb8
2012-08-20silent compiling warnings for VC9 buildYaowu Xu
Change-Id: Iaa947e640f27e6f6eaf7d845f243536bca2df513
2012-08-14Fix warnings.Christian Duvivier
Change-Id: I4b911e4173da30c164bde7ea50bc80a70fbbb745
2012-07-17Restyle codeJohn Koleszar
Approximate the Google style guide[1] so that that there's a written document to follow and tools to check compliance[2]. [1]: http://google-styleguide.googlecode.com/svn/trunk/cppguide.xml [2]: http://google-styleguide.googlecode.com/svn/trunk/cpplint/cpplint.py Change-Id: Idf40e3d8dddcc72150f6af127b13e5dab838685f
2012-06-20Clean Android build defaultsJohann
Disable unit-tests. The logging in GTest would need to be adjusted. Restructure ARM cpu detection. Flatten if-else logic. Change #if defined(HAVE_*) to #if HAVE_* because we only need to check for features that the library was actually built with. This should have been harmless, as disabled feature sets wouldn't have any features to call. Change-Id: Iea21aa42ce5f049c53ca0376d25bcd0f36f38284
2012-06-20Enables building examples with Android NDKAttila Nagy
Soft enable runtime cpu detect for armv7-android target, so that it can be disabled and remove dependency on 'cpufeatures' lib. Change the arm_cpu_caps implementation selection such that 'no rtcd' takes precedence over system type. Switch to use -mtune instead of -mcpu. NDK was complaining about -mcpu=cortex-a8 conflicting with -march=armv7-a, not sure why. Add a linker flag to fix some cortex-a8 bug, as suggested by NDK Dev Guide. Examples: Configure for armv7+neon: ./configure --target=armv7-android-gcc \ --sdk-path=/path/to/android/ndk \ --disable-runtime-cpu-detect \ --enable-realtime-only \ --disable-unit-tests ...armv7 w/o neon: ./configure --target=armv7-android-gcc \ --sdk-path=/path/to/android/ndk \ --disable-runtime-cpu-detect \ --enable-realtime-only \ --disable-neon \ --cpu=cortex-a9 \ --disable-unit-tests Change-Id: I37e2c0592745208979deec38f7658378d4bd6cfa
2012-06-11Fix pedantic compiler warningsJohn Koleszar
Allows building the library with the gcc -pedantic option, for improved portabilty. In particular, this commit removes usage of C99/C++ style single-line comments and dynamic struct initializers. This is a continuation of the work done in commit 97b766a46, which removed most of these warnings for decode only builds. Change-Id: Id453d9c1d9f44cc0381b10c3869fabb0184d5966
2012-05-23asm_*_offsets to define variables as constantsAlpha Lam
This change is to allow obj_int_extract to extract all integers in the data segment. With the const keyword these variables are forced into the .rodata segment even for zero variable value. We had a problem before that zero valueed variables would get assigned to BSS segment that fooled obj_int_extract to give incorrect values. Change-Id: Icd94f80a8ab356879894ca508bf132d20b865299
2012-05-23Make libvpx Chromium build friendlyAlpha Lam
Add PRIVATE macro for adding private_extern directive for yasm to hide global symbols. This is only enabled if -DCHROMIUM is used with YASM. Also fixed a small problem with rtcd_defs.sh to guard TEMPORAL_DENOISING. Change-Id: I9027fce3ebddcf20078293e4b86b396f21da7857
2012-05-02Add support for native Solaris compiler on x86.Timothy B. Terriberry
Original patch by Ginn Chen <ginn.chen@oracle.com> against libvpx v0.9.0. I've forward-ported it to the current version (which mostly involved removing hunks that were no longer relevant), since I've given up on getting Ginn to submit this upstream himself. Change-Id: I403c757c831c78d820ebcfe417e717b470a1d022
2012-03-15WebM Experimental Codec Branch SnapshotYaowu Xu
This is a code snapshot of experimental work currently ongoing for a next-generation codec. The codebase has been cut down considerably from the libvpx baseline. For example, we are currently only supporting VBR 2-pass rate control and have removed most of the code relating to coding speed, threading, error resilience, partitions and various other features. This is in part to make the codebase easier to work on and experiment with, but also because we want to have an open discussion about how the bitstream will be structured and partitioned and not have that conversation constrained by past work. Our basic working pattern has been to initially encapsulate experiments using configure options linked to #IF CONFIG_XXX statements in the code. Once experiments have matured and we are reasonably happy that they give benefit and can be merged without breaking other experiments, we remove the conditional compile statements and merge them in. Current changes include: * Temporal coding experiment for segments (though still only 4 max, it will likely be increased). * Segment feature experiment - to allow various bits of information to be coded at the segment level. Features tested so far include mode and reference frame information, limiting end of block offset and transform size, alongside Q and loop filter parameters, but this set is very fluid. * Support for 8x8 transform - 8x8 dct with 2nd order 2x2 haar is used in MBs using 16x16 prediction modes within inter frames. * Compound prediction (combination of signals from existing predictors to create a new predictor). * 8 tap interpolation filters and 1/8th pel motion vectors. * Loop filter modifications. * Various entropy modifications and changes to how entropy contexts and updates are handled. * Extended quantizer range matched to transform precision improvements. There are also ongoing further experiments that we hope to merge in the near future: For example, coding of motion and other aspects of the prediction signal to better support larger image formats, use of larger block sizes (e.g. 32x32 and up) and lossless non-transform based coding options (especially for key frames). It is our hope that we will be able to make regular updates and we will warmly welcome community contributions. Please be warned that, at this stage, the codebase is currently slower than VP8 stable branch as most new code has not been optimized, and even the 'C' has been deliberately written to be simple and obvious, not fast. The following graphs have the initial test results, numbers in the tables measure the compression improvement in terms of percentage. The build has the following optional experiments configured: --enable-experimental --enable-enhanced_interp --enable-uvintra --enable-high_precision_mv --enable-sixteenth_subpel_uv CIF Size clips: http://getwebm.org/tmp/cif/ HD size clips: http://getwebm.org/tmp/hd/ (stable_20120309 represents encoding results of WebM master branch build as of commit#7a15907) They were encoded using the following encode parameters: --good --cpu-used=0 -t 0 --lag-in-frames=25 --min-q=0 --max-q=63 --end-usage=0 --auto-alt-ref=1 -p 2 --pass=2 --kf-max-dist=9999 --kf-min-dist=0 --drop-frame=0 --static-thresh=0 --bias-pct=50 --minsection-pct=0 --maxsection-pct=800 --sharpness=0 --arnr-maxframes=7 --arnr-strength=3(for HD,6 for CIF) --arnr-type=3 Change-Id: I5c62ed09cfff5815a2bb34e7820d6a810c23183c
2012-03-01vpx_timer: increase resolutionJohn Koleszar
There's no useful reason to limit this timer to 1 second. Change-Id: Idd1960268624e8bdfe958d99833ae6482fdb423e
2012-02-08Add OS/2 supportsKO Myung-Hun
Change-Id: I792d5236451905eb20a8ebe444ef5b2274e4f7a4
2012-01-20Disconnect ARM tgt_isa from dsp extensionsFritz Koenig
A processor with ARMv7 instructions does not necessarily have NEON dsp extensions. This CL has the added side effect of allowing the ability to enable/disable the dsp extensions cleanly. Change-Id: Ie1e879b8fe131885bc3d4138a0acc9ffe73a36df
2012-01-18Add makefile for building libvpx for Android.Fritz Koenig
Android.mk file for using the Android NDK build system to compile. Adds option for SDK path to use the compiler that comes with android for testing compiler compliance. Change-Id: I5fd17cb76e3ed631758d3f392e62ae1a050d0d10
2012-01-06Remove symbian target and associated files.Fritz Koenig
These targets are no longer maintained. Change-Id: I923103006c439849fc015c1ac45ee7a5443ebc6d
2011-09-22Replace vpx_ports/config.h with vpx_config.hAttila Nagy
Just a clean-up. Change-Id: Iea5b6dc925dcfa7db548bc1ab1a13d26ed5a2c9a
2011-06-30Properly use GET_GOT/RESTORE_GOT when using GLOBAL().Ronald S. Bultje
This should fix binaries using PIC on x86-32. Also should fix issue 343. Change-Id: I591de3ad68c8a8bb16054bd8f987a75b4e2bad02
2011-06-08use GCC inline magicJohann
Better fix for #326. ICC happens to support the inline magic Change-Id: Ic367eea608c88d89475cb7b05d73500d2a1bc42b
2011-04-19modify SAVE_XMM for potential 64bit useJohann
the win64 abi requires saving and restoring xmm6:xmm15. currently SAVE_XMM and RESTORE XMM only allow for saving xmm6:xmm7. allow specifying the highest register used and if the stack is unaligned. Change-Id: Ica5699622ffe3346d3a486f48eef0206c51cf867
2011-04-19Merge "Add save/restore xmm registers in x86 assembly code"Johann
2011-04-18Add save/restore xmm registers in x86 assembly codeJohann
Went through the code and fixed it. Verified on Windows. Where possible, remove dependencies on xmm[67] Current code relies on pushing rbp to the stack to get 16 byte alignment. This broke when rbp wasn't pushed (vp8/encoder/x86/sad_sse3.asm). Work around this by using unaligned memory accesses. Revisit this and the offsets in vp8/encoder/x86/sad_sse3.asm in another change to SAVE_XMM. Change-Id: I5f940994d3ebfd977c3d68446cef20fd78b07877
2011-04-18Merge "Add spin-wait pause intrinsic for Windows x64 platform."Yaowu Xu
2011-03-12Fix build with xcode4 and simplify GLOBAL.Rafael Ávila de Espíndola
Without this change I get link errors in firefox's libxul. It looks like the linker expect a particular pattern for getting the GOT. This patch changes webm to use the same pattern used by the compiler. Change-Id: Iea8c2e134ad45c1dc7d221ff885a8429bfa4e057
2011-03-04Add spin-wait pause intrinsic for Windows x64 platform.Aron Rosenberg
Change-Id: I7504370c67a3c551627c6bb7e67c65f83d88b78e
2011-02-16documentation: minor cosmeticsJames Zern
- correct spelling - remove explicit file name w/\file (unnecessary when contained in the same file and prone to desync) Change-Id: I68a3960ac5ab84d0f2e5c9b2e29799f26dfccf23
2011-01-28Adds "armvX-none-rvct" targetsTero Rintaluoma
Adds following targets to configure script to support RVCT compilation without operating system support (for Profiler or bare metal images). - armv5te-none-rvct - armv6-none-rvct - armv7-none-rvct To strip OS specific parts from the code "os_support"-config was added to script and CONFIG_OS_SUPPORT flag is used in the code to exclude OS specific parts such as OS specific includes and function calls for timers and threads etc. This was done to enable RVCT compilation for profiling purposes or running the image on bare metal target with Lauterbach. Removed separate AREA directives for READONLY data in armv6 and neon assembly files to fix the RVCT compilation. Otherwise "ldr <reg>, =label" syntax would have been needed to prevent linker errors. This syntax is not supported by older gnu assemblers. Change-Id: I14f4c68529e8c27397502fbc3010a54e505ddb43
2010-10-27Full search SAD function optimization in SSE4.1Yunqing Wang
Use mpsadbw, and calculate 8 sad at once. Function list: vp8_sad16x16x8_sse4 vp8_sad16x8x8_sse4 vp8_sad8x16x8_sse4 vp8_sad8x8x8_sse4 vp8_sad4x4x8_sse4 (test clip: tulip) For best quality mode, this gave encoder a 5% performance boost. For good quality mode with speed=1, this gave encoder a 3% performance boost. Change-Id: I083b5a39d39144f88dcbccbef95da6498e490134
2010-10-25Add runtime CPU detection support for ARM.Timothy B. Terriberry
The primary goal is to allow a binary to be built which supports NEON, but can fall back to non-NEON routines, since some Android devices do not have NEON, even if they are otherwise ARMv7 (e.g., Tegra). The configure-generated flags HAVE_ARMV7, etc., are used to decide which versions of each function to build, and when CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen at run time. In order for this to work, the CFLAGS must be set to something appropriate (e.g., without -mfpu=neon for ARMv7, and with appropriate -march and -mcpu for even earlier configurations), or the native C code will not be able to run. The ASFLAGS must remain set for the most advanced instruction set required at build time, since the ARM assembler will refuse to emit them otherwise. I have not attempted to make any changes to configure to do this automatically. Doing so will probably require the addition of new configure options. Many of the hooks for RTCD on ARM were already there, but a lot of the code had bit-rotted, and a good deal of the ARM-specific code is not integrated into the RTCD structs at all. I did not try to resolve the latter, merely to add the minimal amount of protection around them to allow RTCD to work. Those functions that were called based on an ifdef at the calling site were expanded to check the RTCD flags at that site, but they should be added to an RTCD struct somewhere in the future. The functions invoked with global function pointers still are, but these should be moved into an RTCD struct for thread safety (I believe every platform currently supported has atomic pointer stores, but this is not guaranteed). The encoder's boolhuff functions did not even have _c and armv7 suffixes, and the correct version was resolved at link time. The token packing functions did have appropriate suffixes, but the version was selected with a define, with no associated RTCD struct. However, for both of these, the only armv7 instruction they actually used was rbit, and this was completely superfluous, so I reworked them to avoid it. The only non-ARMv4 instruction remaining in them is clz, which is ARMv5 (not even ARMv5TE is required). Considering that there are no ARM-specific configs which are not at least ARMv5TE, I did not try to detect these at runtime, and simply enable them for ARMv5 and above. Finally, the NEON register saving code was completely non-reentrant, since it saved the registers to a global, static variable. I moved the storage for this onto the stack. A single binary built with this code was tested on an ARM11 (ARMv6) and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder, and produced identical output, while using the correct accelerated functions on each. I did not test on any earlier processors. Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-13Add processor dectection for x86.Fritz Koenig
Use cpuid to check the vendor string against known architectures. Change-Id: I3fbd7f73638d71857a0c4a44a6275eb295fb4cef
2010-10-12GCC inline restrictions were not adequate.Fritz Koenig
=r was not restrictive enough and the compiler was not returning ebx correctly. Change-Id: I7606e384067bd5fb69189802f1ff64ccc5aa02d6
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-10 23:27:19 +0000