Age | Commit message (Collapse) | Author |
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In motion estimation stage for subpel motion, subpel variance is
computed use bilinear interpolation. The motion vector precision
used is at 1/8 pel and three bits are used to represent the x and y
subpel offsets. Based on this, the half pel check should be against
4, not 8.
Change-Id: I1f56fa1fa3f2f5e19a20d27983efe628557f170e
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there are sse2 equivalents which is a reasonable modern baseline
Removed mmx variance functions:
vpx_get_mb_ss_mmx()
vpx_get8x8var_mmx()
vpx_get4x4var_mmx()
vpx_variance4x4_mmx()
vpx_variance8x8_mmx()
vpx_mse16x16_mmx()
vpx_variance16x16_mmx()
vpx_variance16x8_mmx()
vpx_variance8x16_mmx()
Change-Id: Iffaf85344c6676a3dd337c0645a2dd5deb2f86a1
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there are sse2 equivalents which is a reasonable modern baseline
Change-Id: Ibbe536a5ad1c2cccef6bdcc75c13b3dde35a56ba
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Change-Id: I4906d1b79a2951e659995202b9fa97e2ea5cfba0
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* changes:
The subfunctions are only defined for sse2
Unlike non-hbd variance, opt2 is never used
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Change-Id: I431ea0d9abe764d110a1ba32a8cb15e2fdac8805
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This change makes the c match the assembly and removes the todo's
associated with getting this to work.
Change-Id: Ie32e9ebb584a9d60399662d8bcb71b74fbd19d1e
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Change-Id: Ibe0cc388226622561d2b4a00e5bdc1016a3c4a94
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See highbd_subpel_variance_impl_sse2.asm
Change-Id: Id13b97f4f6d189ed71cdc6d52b3c4ea63dc1da05
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Change-Id: I1d342725df332c4efc6006d9e3dcb7372c41f448
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* changes:
vp9_frame_scale_ssse3.c: make 2 functions static
vp9_pickmode.c: make function static
vp9_noise_estimate.c: make function static
vp9_aq_360.c: add missing include
vp9_idct_intrin_sse2: add missing vp9_rtcd.h include
vpx_dsp/*.[hc]: add missing vpx_dsp_rtcd.h include
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Change-Id: I103be7eee36492f8619144ce8325bc916d4975c7
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Change-Id: I05b3028a38bbc062c388eeb95e99a3fee583ae6b
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Change-Id: I1ad41c096ec86870f9aecab6fdbc3af03e972afc
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In so doing this fixes a couple of bugs:
vpx_plane_add_noise.c needed to subtract a clamp instead of add.
And the assembly (mmx sse) had assumptions that parameters were
continuous in memory which was not true.
Change-Id: I76f2c43cf54bfc838eb2edf8a443eaaa7565d7b5
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Change-Id: I12218d8331c0558c0587a66321e3ca46da7e5cc7
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Change-Id: I481eb271b082fa3497b0283f37d9b4d1f6de270c
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bits_left is in the range [0, 64 (= BD_VALUE_SIZE)] , so the narrowing
conversion should be safe.
Change-Id: I943fcd359eaad76249ee1e1fb03a2ac16945d2fd
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The product always fits in uint32_t, but the operands don't.
An optimizing compiler should generate the wraparound code.
(Verified with clang).
Change-Id: I25eb64df99152992bc898b8ccbb01d55c8d16e3c
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These blocks will never overflow since max sum is +/-255*w*h.
Change-Id: Ia2c630339fd9cfb411b56b6040ff402095f12a2e
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BUG=https://bugs.chromium.org/p/webm/issues/detail?id=1156
Change-Id: Ief0ad8d6255b0ef0f233cda153799e3c72d3dbc6
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The order of the output structure is not currently important.
BUG=https://bugs.chromium.org/p/webm/issues/detail?id=1021
Change-Id: Ibc0006d569675db6c5060c4529f5d9e73f2e96a6
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neon_asm"
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This was never hooked up for the 32x32_34 case as the neon_asm version
in 3f7c12da, when the intrinsics version was added.
Change-Id: Ic7db4ce5850c637315f9fe9e2de93a4f8cf9e320
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Change-Id: Ic6b695442e319f7582a7ee8e52a47ae3e38c7298
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* changes:
vpx_fdct16x16_1_sse2: improve load pattern
vpx_fdct16x16_1_c/msa: fix accumulator overflow
vpx_fdctNxN_1_sse2: reduce store size
dct32x32_test: add PartialTrans32x32Test, Random
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load the full row rather than doing 2 8-wide columns
Change-Id: I7a1c0cba06b0dc1ae86046410922b1efccb95c95
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tran_low_t is only signed 16-bits in non-high-bitdepth mode
Change-Id: Ie02b5caf2658e8e71f995c17dd5ce666a4d64918
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only output[0] needs to be set, store_output is more involved than a
movdqa in the high bitdepth case
Change-Id: I2cbd85d7cf74688bdf47eb767934fe42e02bff67
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Change-Id: I33a5432eda3416382e1cea06b45082c0c65faa75
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only output[0] needs to be set, the other values will be ignored in this
case.
Change-Id: I8e9692fc0d6d85700ba46f70c2e899a956023910
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tran_low_t is only 16-bits in non-high-bitdepth mode
Change-Id: Ifc06110c95e86e6d790c44250d52a538b2e9713b
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This reverts commit 9aa083d164e0d39086aa0c83f0d1a0d0f0d1ba61.
Fixes a decoder mismatch with 32bit PIC builds.
Change-Id: I94717df662834810302fe3594b38c53084a4e284
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This reverts commit 15ecdc3970462c15fdf7185d373cb52664f40c0f.
breaks 32-bit pic builds
Change-Id: I8bb1b9471a293f05ac7423aaba0339d408931b7a
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These instructions are unnecessary if the adds
are done in the correct order.
Change-Id: I4e533b8267c32e610a4b94203ad052dc9fdabd71
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the filter will be the same in this case
Change-Id: I95159bcb05bbfb71b57da741393e80cc7ffc5cff
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in non-hbd configurations; any high-bitdepth changes will be done in a
follow-up
Change-Id: Ia74e30971b744c1faab68c92fdeda1a053988c77
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Store result with one 16 byte store instead of
two 8 byte stores.
Change-Id: I43acbc5edfd6d6055a926f9b9605d47127400f09
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Change-Id: I661f64390f232826857b259e7a67e77f5a3a91ad
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Change-Id: Ic7ea79988ed0864e7ddbfeb312516bcf77eaaac1
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Change-Id: Idcf29281d617b275e3ca50f77e6d00c60992a36d
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replace with vpx_highbd_lpf_horizontal_edge_16 and
vpx_highbd_lpf_horizontal_edge_8 to avoid passing a count parameter
Change-Id: I551f8cec0fce57032cb2652584bb802e2248644d
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