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2012-02-23Supporting high precision 1/8-pel motion vectorsDeb Mukherjee
This is the initial patch for supporting 1/8th pel motion. Currently if we configure with enable-high-precision-mv, all motion vectors would default to 1/8 pel. Encode and decode syncs fine with the current code. In the next phase the code will be refactored so that we can choose the 1/8 pel mode adaptively at a frame/segment/mb level. Derf results: http://www.corp.google.com/~debargha/vp8_results/enhinterp_hpmv.html (about 0.83% better than 8-tap interpoaltion) Patch 3: Rebased. Also adding 1/16th pel interpolation for U and V Patch 4: HD results. http://www.corp.google.com/~debargha/vp8_results/enhinterp_hd_hpmv.html Seems impressive (unless I am doing something wrong). Patch 5: Added mmx/sse for bilateral filtering, as well as enforced use of c-versions of subpel filters with 8-taps and 1/16th pel; Also redesigned the 8-tap filters to reduce the cut-off in order to introduce a denoising effect. There is a new configure option sixteenth-subpel-uv which will use 1/16 th pel interpolation for uv, if the motion vectors have 1/8 pel accuracy. With the fixes the results are promising on the derf set. The enhanced interpolation option with 8-taps alone gives 3% improvement over thei derf set: http://www.corp.google.com/~debargha/vp8_results/enhinterpn.html Results on high precision mv and on the hd set are to follow. Patch 6: Adding a missing condition for CONFIG_SIXTEENTH_SUBPEL_UV in vp8/common/x86/x86_systemdependent.c Patch 7: Cleaning up various debug messages. Patch 8: Merge conflict Change-Id: I5b1d844457aefd7414a9e4e0e06c6ed38fd8cc04
2012-02-16Code simplificationPaul Wilkins
Removal of the pickinter.c and .h files and calls to this code. Removal of some code relating to real time and one pass settings though there is more to be done in this regard. However, vp8_set_speed_features() now only supports modes 0 and 1 and speeds up to 3 so rd should always be set. Change-Id: I62c0c1b6154ab499785baef310536080e87bc4d8
2011-09-20Move neon only arm functions under arm/neon.Fritz Koenig
These files don't contain generic arm code, so should only be compiled by neon. Change-Id: Ie712823aa04d4235e7cfe7a3b725e73ee4c3e564
2011-09-20Merge "NEON FDCT updated to match current C code"Johann
2011-09-20Merge "NEON walsh transform updated to match C"Johann
2011-09-20Merge "Updated ARMv6 forward transforms to match C"Johann
2011-09-20NEON FDCT updated to match current C codeTero Rintaluoma
- Removed fast_fdct4x4_neon and fast_fdct8x4_neon - Uses now short_fdct4x4 and short_fdct8x4 - Gives ~1-2% speed-up on Cortex-A8/A9 Change-Id: Ib62f2cb2080ae719f8fa1d518a3a5e71278a41ec
2011-09-20Fixed armv5te multiplicationsTero Rintaluoma
Rd and Rm registers should be different in 'mul'. This register combination results in unpredictable behaviour. GCC will give a warning and RVCT an error in this case. Restriction applies only to armv5 targets and not for armv6 and above. Change-Id: I378d17c51e1f16a6820814fbed43e115aaabb03e
2011-09-19Updated ARMv6 forward transforms to match CTero Rintaluoma
- Updated walsh transform to match C (based on Change Id24f3392) - Changed fast_fdct4x4 and 8x4 to short_fdct4x4 and 8x4 correspondingly Change-Id: I704e862f40e315b0a79997633c7bd9c347166a8e
2011-09-19NEON walsh transform updated to match CTero Rintaluoma
Modified original patch If2f07220885c4c3a0cae0dace34ea0e36124f001 according to comments. Scheduled code a little bit to prevent some interlocks. Change-Id: I338f02b881098782f82af63d97f042b85e63e902
2011-06-29clean up warnings when building arm with rtcdJohann
Change-Id: I3683cb87e9cb7c36fc22c1d70f0799c7c46a21df
2011-06-09remove one set of 16x16 variance funcationsYaowu Xu
call to this set of functions are replaced by var16x16. Change-Id: I5ff1effc6c1358ea06cda1517b88ec28ef551b0d
2011-06-06remove redundant functionsYaowu Xu
The encoder defined about 4 set of similar functions to calculate sum, variance or sse or a combination of them. This commit removed one set of these functions, get8x8var and get16x16var, where calls to the later function are replaced with var16x16 by using the fact on a 16x16 MB: variance == sse - sum*sum/256 Change-Id: I803eabd1fb3ab177780a40338cbd596dffaed267
2011-06-06Merge "neon fast quantize block pair"Johann
2011-06-01neon fast quantize block pairTero Rintaluoma
vp8_fast_quantize_b_pair_neon function added to quantize two adjacent blocks at the same time to improve performance. - Additional 3-6% speedup compared to neon optimized fast quantizer (Tanya VGA@30fps, 1Mbps stream, cpu-used=-5..-16) Change-Id: I3fcbf141e5d05e9118c38ca37310458afbabaa4e
2011-05-30adds preload for armv6 encoder asmTero Rintaluoma
Added preload instructions to armv6 encoder optimizations. About 5% average speed-up on Tegra2 for VGA@30fps sequence. Change-Id: I41d74737720fb71ce7a316f07555357822f3347e
2011-05-25Return sse value in vp8_variance SSE2 functionsYunqing Wang
Minor modification. Change-Id: I09511d38fd1451d5c4106a48acdb3f766ce59cb7
2011-05-06neon fast quantizer updatedTero Rintaluoma
vp8_fast_quantize_b_neon function updated and further optimized. - match current C implementation of fast quantizer - updated to use asm_enc_offsets for structure members - updated ads2gas scripts to handle alignment issues Change-Id: I5cbad9c460ad8ddb35d2970a8684cc620711c56d
2011-04-01Merge "Wrapper function removed from vp8_subtract_b_neon function call"Johann
2011-04-01Wrapper function removed from vp8_subtract_b_neon function callTero Rintaluoma
Address calculations moved from encodemb_arm.c file to neon optimized assembly function to save cycles in function calls. - vp8_subtract_b_neon_func replaced with vp8_subtract_b_neon that contains all needed address calculations - unnecessary file encodemb_arm.c removed - consistent with ARMv6 optimized version Change-Id: I6cbc1a2670b56c2077f59995fcf8f70786b4990b
2011-03-31Merge "ARMv6 optimized subtract functions"Johann
2011-03-29ARMv6 optimized subtract functionsTero Rintaluoma
Adds following ARMv6 optimized functions to encoder: - vp8_subtract_b_armv6 - vp8_subtract_mby_armv6 - vp8_subtract_mbuv_armv6 Gives 1-5% speed-up depending on input sequence and encoding parameters. Functions have one stall cycle inside the loop body on Cortex pipeline. Change-Id: I19cca5408b9861b96f378e818eefeb3855238639
2011-03-28Half pixel variance further optimized for ARMv6Tero Rintaluoma
Half pixel interpolations optimized in variance calculations. Separate function calls to vp8_filter_block2d_bil_x_pass_armv6 are avoided.On average, performance improvement is 6-7% for VGA@30fps sequences. Change-Id: Idb5f118a9d51548e824719d2cfe5be0fa6996628
2011-03-21ARMv6 optimized fdct4x4Tero Rintaluoma
Optimized fdct4x4 (8x4) for ARMv6 instruction set. - No interlocks in Cortex-A8 pipeline - One interlock cycle in ARM11 pipeline - About 2.16 times faster than current C-code compiled with -O3 Change-Id: I60484ecd144365da45bb68a960d30196b59952b8
2011-03-15Add vp8_variance8x8_armv6 and vp8_sub_pixel_variance8x8_armv6 functionsAttila Nagy
Change-Id: I08edaffc62514907fa5e90e1689269e467c857f5
2011-03-14Merge "Add vp8_mse16x16_armv6 function"Johann
2011-03-14Add vp8_mse16x16_armv6 functionAttila Nagy
Change-Id: I77e9f2f521a71089228f96e2db72524189364ffb
2011-03-11ARMv6 optimized quantizationTero Rintaluoma
Adds new ARMv6 optimized function vp8_fast_quantize_b_armv6 to the encoder. Change-Id: I40277ec8f82e8a6cbc453cf295a0cc9b2504b21e
2011-02-23ARMv6 optimized half pixel variance calculationsTero Rintaluoma
Adds following ARMv6 optimized functions to the encoder: - vp8_variance_halfpixvar16x16_h_armv6 - vp8_variance_halfpixvar16x16_v_armv6 - vp8_variance_halfpixvar16x16_hv_armv6 Change-Id: I1e9c2af7acd2a51b72b3845beecd990db4bebd29
2011-02-18remove unused vp8_predict_dc functionJohn Koleszar
Change-Id: I64fa47889c54cfed094a674c49ef0996d49bdd42
2011-02-17Merge "Fix relative include paths"John Koleszar
2011-02-11ARMv6 optimized sad16x16Tero Rintaluoma
Adds a new ARMv6 optimized function vp8_sad16x16_armv6 to encoder. Change-Id: Ibbd7edb8b25cb7a5b522d391b1e9a690fe150e57
2011-02-10Fix relative include pathsJohn Koleszar
Allow compiling without adding vp8/{common,encoder,decoder} to the include paths. Change-Id: Ifeb5dac351cdfadcd659736f5158b315a0030b6c
2011-02-09Adds armv6 optimized variance calculationTero Rintaluoma
Adds vp8_sub_pixel_variance16x16_armv6 function to encoder. Integrates ARMv6 optimized bilinear interpolations from vp8/common/arm/armv6 and adds new assembly file for variance16x16 calculation. - vp8_filter_block2d_bil_first_pass_armv6 (integrated) - vp8_filter_block2d_bil_second_pass_armv6 (integrated) - vp8_variance16x16_armv6 (new) - bilinearfilter_arm.h (new) Change-Id: I18a8331ce7d031ceedd6cd415ecacb0c8f3392db
2011-02-08clarify *_offsets.asm differencesJohann
it's difficult to mux the *_offsets.c files because of header conflicts. make three instead, name them consistently and partititon the contents to allow building them as required. Change-Id: I8f9768c09279f934f44b6c5b0ec363f7943bb796
2011-01-28Merge "Adds "armvX-none-rvct" targets"Johann
2011-01-28Adds "armvX-none-rvct" targetsTero Rintaluoma
Adds following targets to configure script to support RVCT compilation without operating system support (for Profiler or bare metal images). - armv5te-none-rvct - armv6-none-rvct - armv7-none-rvct To strip OS specific parts from the code "os_support"-config was added to script and CONFIG_OS_SUPPORT flag is used in the code to exclude OS specific parts such as OS specific includes and function calls for timers and threads etc. This was done to enable RVCT compilation for profiling purposes or running the image on bare metal target with Lauterbach. Removed separate AREA directives for READONLY data in armv6 and neon assembly files to fix the RVCT compilation. Otherwise "ldr <reg>, =label" syntax would have been needed to prevent linker errors. This syntax is not supported by older gnu assemblers. Change-Id: I14f4c68529e8c27397502fbc3010a54e505ddb43
2011-01-27clean up implicit declaration warnings for neonJohann
Change-Id: I6ca2d89f355839c4c770773c09fc69dcea7c1406 warning: implicit declaration of function 'vp8_variance_halfpixvar16x16_[h|v|hv]_neon' 'vp8_sub_pixel_variance16x16_neon_func'
2011-01-25Merge "move new neon subpixel function"Johann
2011-01-25Merge "Fix issue 262, vp8cx_pack_tokens_into_partitions_armv5"Johann
2011-01-25move new neon subpixel functionJohann
previously wasn't guarded with ifdef ARMV7, causing a link error with ARMV6 Change-Id: I0526858be0b5f49b2bf11e9090180b2a6c48926d
2011-01-25Fix issue 262, vp8cx_pack_tokens_into_partitions_armv5Attila Nagy
http://code.google.com/p/webm/issues/detail?id=262 Function was asuming that partitions have equal amount of mb_rows, which is not always true. Change-Id: I59ed40117fd408392a85c633beeb5340ed2f4b25
2011-01-18Modify calling of NEON code in sub-pixel searchYunqing Wang
In vp8_find_best_sub_pixel_step_iteratively(), many times xoffset and yoffset are specific values - (4,0) (0,4) and (4,4). Modified code to call simplified NEON version at these specific offsets to help with the performance. Change-Id: Iaf896a0f7aae4697bd36a49e182525dd1ef1ab4d
2010-12-28Use the fast quantizer for inter mode selectionScott LaVarnway
Use the fast quantizer for inter mode selection and the regular quantizer for the rest of the encode for good quality, speed 1. Both performance and quality were improved. The quality gains will make up for the quality loss mentioned in I9dc089007ca08129fb6c11fe7692777ebb8647b0. Change-Id: Ia90bc9cf326a7c65d60d31fa32f6465ab6984d21
2010-12-14shrink TOKENEXTRA and vp8_extra_bit_structJohann
Per John's previous change, shrink TOKENEXTRA from 20 to 8 bytes original: b7b1e6fb reverted: 41f4458a Also drop unused field from vp8_extra_bit_struct Update ARM ASM to deal with this change. In particular, Extra is signed and needs to be sign-extended when loaded. Change-Id: Ibd0ddc058432bc7bb09222d6ce4ef77e93a30b41
2010-10-27Fix half-pixel variance RTCD functionsJohn Koleszar
This patch fixes the system dependent entries for the half-pixel variance functions in both the RTCD and non-RTCD cases: - The generic C versions of these functions are now correct. Before all three cases called the hv code. - Wire up the ARM functions in RTCD mode - Created stubs for x86 to call the optimized subpixel functions with the correct parameters, rather than falling back to C code. Change-Id: I1d937d074d929e0eb93aacb1232cc5e0ad1c6184
2010-10-26Add half-pixel variance RTCD functionsJohn Koleszar
NEON has optimized 16x16 half-pixel variance functions, but they were not part of the RTCD framework. Add these functions to RTCD, so that other platforms can make use of this optimization in the future and special-case ARM code can be removed. A number of functions were taking two variance functions as parameters. These functions were changed to take a single parameter, a pointer to a struct containing all the variance functions for that block size. This provides additional flexibility for calling additional variance functions (the half-pixel special case, for example) and by initializing the table for all block sizes, we don't have to construct this function pointer table for each macroblock. Change-Id: I78289ff36b2715f9a7aa04d5f6fbe3d23acdc29c
2010-10-26make arm hex search the generic implementationJohn Koleszar
The ARM version of vp8_hex_search() is a faster implementation of the same algorithm. Since it doesn't use any ARM specific code, it can be made the default implementation. This removes a linking error. Change-Id: I77d10f2c16b2515bff4522c350004e03b7659934
2010-10-26arm: remove duplicate functionsJohn Koleszar
These functions were true duplicates of functions present in the generic code. This fixes some of the link errors when building with --enable-shared --enable-pic. Change-Id: Idff26599d510d954e439207883607ad6b74df20c
2010-10-25Add runtime CPU detection support for ARM.Timothy B. Terriberry
The primary goal is to allow a binary to be built which supports NEON, but can fall back to non-NEON routines, since some Android devices do not have NEON, even if they are otherwise ARMv7 (e.g., Tegra). The configure-generated flags HAVE_ARMV7, etc., are used to decide which versions of each function to build, and when CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen at run time. In order for this to work, the CFLAGS must be set to something appropriate (e.g., without -mfpu=neon for ARMv7, and with appropriate -march and -mcpu for even earlier configurations), or the native C code will not be able to run. The ASFLAGS must remain set for the most advanced instruction set required at build time, since the ARM assembler will refuse to emit them otherwise. I have not attempted to make any changes to configure to do this automatically. Doing so will probably require the addition of new configure options. Many of the hooks for RTCD on ARM were already there, but a lot of the code had bit-rotted, and a good deal of the ARM-specific code is not integrated into the RTCD structs at all. I did not try to resolve the latter, merely to add the minimal amount of protection around them to allow RTCD to work. Those functions that were called based on an ifdef at the calling site were expanded to check the RTCD flags at that site, but they should be added to an RTCD struct somewhere in the future. The functions invoked with global function pointers still are, but these should be moved into an RTCD struct for thread safety (I believe every platform currently supported has atomic pointer stores, but this is not guaranteed). The encoder's boolhuff functions did not even have _c and armv7 suffixes, and the correct version was resolved at link time. The token packing functions did have appropriate suffixes, but the version was selected with a define, with no associated RTCD struct. However, for both of these, the only armv7 instruction they actually used was rbit, and this was completely superfluous, so I reworked them to avoid it. The only non-ARMv4 instruction remaining in them is clz, which is ARMv5 (not even ARMv5TE is required). Considering that there are no ARM-specific configs which are not at least ARMv5TE, I did not try to detect these at runtime, and simply enable them for ARMv5 and above. Finally, the NEON register saving code was completely non-reentrant, since it saved the registers to a global, static variable. I moved the storage for this onto the stack. A single binary built with this code was tested on an ARM11 (ARMv6) and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder, and produced identical output, while using the correct accelerated functions on each. I did not test on any earlier processors. Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
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