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This reverts commit ea48370a500537906d62544ca4ed75301d79e772, reversing
changes made to 15939cb2d76c773950cda40988ede89e111872ea.
The commit was insufficiently tested and causes failures.
Change-Id: I623d6fc2cd3ae6fd42d0abab1f8eada465ae57a7
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Remove the ARCH_X86_64 constraint. No performance hit on both
big core and small core.
Change-Id: I39860b62b7a0ae4acaafdca7d68f3e5820133a81
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Remove the ARCH_X86_64 constraint.
Change-Id: I0139f8e998cc5525df55161c2054008d21ac24d4
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Remove the ARCH_X86_64 constraint.
Change-Id: I7d2545fc4f24eb352cf3e03082fc4d48d46fbb09
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Replace MMX with SSE2, reduce mem access to left neighbor,
loop unrolled.
Change-Id: I941be915af809025f121ecc6c6443f73c9903e70
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MMX replaced with SSE2, same performance.
Change-Id: I2ab8f30a71e5fadbbc172fb385093dec1e11a696
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MMX replaced with SSE2, same performance.
Change-Id: Ic57855254e26757191933c948fac6aa047fadafc
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Replace MMX with SSE2, reduce psadbw ops which may help Silvermont.
Change-Id: Ic7aec15245c9e5b2f3903dc7631f38e60be7c93d
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Change-Id: I7bc991abea383db1f86c1bb0f2e849837b54d90f
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Reallocate the xmm register usage so that no ARCH_X86_64 required.
Reduce memory access to the left neighbor by half.
Speed up by single digit on big core machine.
Change-Id: I392515ed8e8aeb02e6a717b3966b1ba13f5be990
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Relocate the function from SSSE3 to SSE2, Unroll loop from 16 to 8,
and reduce mem access to left.
Speed up by single digit in ./test_intra_pred_speed on big core
machines.
Change-Id: I2b7fc95ffc0c42145be2baca4dc77116dff1c960
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* changes:
test.mk: simplify vp8/9 checks
test.mk: regroup white box tests
test.mk: enable test_intra_pred_speed unconditionally
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Change-Id: I3ef9a9648841374ed3cc865a02053c14ad821a20
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4x4 Intra predictor implemented with MMX is replaced with SSE2.
Segfault in change 315561 when decoding vp8 is taken care of.
Change-Id: I083a7cb4eb8982954c20865160f91ebec777ec76
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This reverts commit 89a1efa4c436c58c101c8b3de866e3014be7d77a.
This causes a segfault when decoding vp8, in both 32 and 64-bit
Change-Id: Idbb9bb28ab897e1d055340497c47b49a12231367
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use CONFIG_VP[89] to protect white-box tests and drop redundant
uses of CONFIG_VP9 in variable assignments within that block
Change-Id: Id3c6cf5c7822aa161b19768b295f58829a1c6447
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vp8/9/10/multi-config/unconditional
Change-Id: I7970575e997da0b68c6c54741a221fbba5ad0b08
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Relocate the function from SSSE3 to SSE2, Unroll loop from 8 to 4,
and reduce mem access to left.
Speed up by >20% in ./test_intra_pred_speed.
Change-Id: Ie48229c2e32404706b722442942c84983bda74cc
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Relocate the function from SSSE3 to SSE2, Unroll loop from 4 to 2,
and reduce mem access to left.
Speed up by >20% in ./test_intra_pred_speed.
Change-Id: Ib9f1846819783b6e05e2a310c930eb844b2b4d2e
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8x8 Intra predictor implemented with MMX is replaced with SSE2.
Change-Id: I0c90e7c1e1e6942489ac2bfe58903b728aac7a52
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4x4 Intra predictor implemented with MMX is replaced with SSE2.
Change-Id: Id57da2a7c38832d0356bc998790fc1989d39eafc
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Relocate h_predictor_4x4 from SSSE3 to SSE2 with XMM registers.
Speed up by ~25% in ./test_intra_pred_speed.
Change-Id: I64e14c13b482a471449be3559bfb0da45cf88d9d
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vpx_dsp is currently included in all configurations
Change-Id: If3253a87d27f3e1abc94fbfe76f978c1172f3762
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* changes:
add vp9_satd_neon
fix vp9_satd_sse2
vp9_satd: return an int
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Always round sum error and sum square error toward zero in variance
calculations. This prevents variance from becoming negative.
Avoiding rounding variance at all might be better but would be far
more invasive.
Change-Id: Icf24e0e75ff94952fc026ba6a4d26adf8d373f1c
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~60-65% faster at the function level across block sizes
Change-Id: Iaf8cbe95731c43fdcbf68256e44284ba51a93893
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Change-Id: Ic0ec32c1d7f7c08c9f956592dccbfd9060b1f624
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accumulate satd in 32-bits
+ add unit test
Change-Id: I6748183df3662ddb9d635f9641f9586f2fd38ad5
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the final sum may use up to 26 bits
+ add a unit test
+ disable the sse2 as the result will rollover; this will be fixed in a
future commit
Change-Id: I2a49811dfaa06abfd9fa1e1e65ed7cd68e4c97ce
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tm_predictor_4x4 is implemented with SSE2 using XMM registers.
Speed up by ~25% in ./test_intra_pred_speed.
Change-Id: I25074b78d476a2cb17f81cf654bdfd80df2070e0
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Change-Id: I5a4f1f7b9de20fbfc28cb743dcd29c0eeca736f8
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Temporary fix to make sure it always passes.
Change-Id: I56a0529986ad7049b6090f871c14e9e06d573d5f
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Change-Id: I635e37f81237e9703d7d9a11ed76a043f4ec6eb0
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Change-Id: I9bfa80de73847d9be88b6ce9865d7bb5fafaaa57
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The unit test requires a longer clip which is already in the repo.
Change-Id: Ic42e8d83e636fafd20d485a7f5f8422835319245
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For 1 pass CBR mode: increase waiting time after key frame
before we start sampling rate control behavior for determining
resize. This change need to disable one internal resize(DownUp)
temporally since it requires a longer clip to do so.
Change-Id: If21beda1be23f169ee541ab4dd642f718347887a
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this helps some toolchains (vs9) resolve the type of the parameter
Change-Id: I8c83b86da53b1783cd18c0f765b67ba33da91d72
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this helps some toolchains (vs9) resolve the type of the parameter
Change-Id: Ic53b2ed5fbce05c5b5e633b4a4ef9ea75c55360a
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this helps some toolchains (vs9) resolve the type of the parameter
Change-Id: I4acc8a844d1e55b766f66482bd6d32998174d70f
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-l -> -sl, renamed in:
be3b08d [svc] Temporal svc with two pass rate control
Change-Id: I5a7b179b33d94e20e54825090659156dece928c0
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Current threshold is little too strict.
Change-Id: I99ec1409d095e0c2fd3b7ab398742cabcc05700b
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this avoids redefining vpx_codec_vp9_dx, vpx_codec_vp9_dx_algo in
vp9_encoder_parms_get_to_decoder.cc
Change-Id: I3b89e7a62497227ee32419f1a7d30e4c10a13c05
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Refer to doc "vp9-test-vectors".
BUG=https://code.google.com/p/webm/issues/detail?id=1086
Change-Id: I523d1f39141a3a86f113604cbdb9cd41cc2d6470
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