Age | Commit message (Collapse) | Author |
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This commit adds a new configure option:
--enable-better-hw-compatibility
The purpose of the configure option is to provide information on known
hardware decoder implementation bugs, so encoder implementers may
choose to implement their encoders in a way to avoid triggering these
decoder bugs.
The WebM team were made aware of that a number of hardware decoders
have trouble in handling the combination of scaled frame reference
frame and 8x4 or 4x8 partitions. This commit added asserts to vp9
decoder, so when built with above configure option, the decoder can
assert if an input bitstream triggers such decoder bug.
Change-Id: I386204cfa80ed16b50ebde57f886121ed76200bf
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Add function to compute skin map for a given block, as its
used in several places (cyclic refresh, noise estimation, and denoising).
Change-Id: Ied622908df43b6927f7fafc6c019d1867f2a24eb
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Set initial values for these parameters in the vp9_init_layer_context().
This also fixes an issue in the svc-bypass mode when frame flags are
passed via the vpx_codec_encode().
Change-Id: I0968f04672f8d3d2fe2cea6b8a23f79f80d7a8b1
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Otherwise, per-segment lossless might mean that some segments are not
lossless and they could still want to use another mode. The per-block
tx points remain uncoded on blocks where (per the segment id) the Q
value implies lossless.
Change-Id: If210206ab1fe3dd11976797370c77f961f13dfa0
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Change-Id: Ic23c10b6d2a9fed3abe69c6bf10e910832444f2c
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* changes:
Code clean of highbd_tm_predictor_16x16
Code clean of highbd_dc_predictor_32x32
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Remove the ARCH_X86_64 constraint. No performance hit on both
big core and small core.
Change-Id: I39860b62b7a0ae4acaafdca7d68f3e5820133a81
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Remove the ARCH_X86_64 constraint.
Change-Id: I0139f8e998cc5525df55161c2054008d21ac24d4
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Remove the ARCH_X86_64 constraint.
Change-Id: I7d2545fc4f24eb352cf3e03082fc4d48d46fbb09
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For coding block sizes <=16X16, if the block is determined to be skin,
then always allow for that block to be candidate for refresh. So if that
block happens to be on the boost segment(s), segment won't get reset to 0
and delta-q will be applied.
PSNR/SSIM metrics neutral (little/no change) on RTC clips.
Speed increase small/negligible (< 1%).
Some visual improvement on faces in a few RTC clips.
Change-Id: I6bf0fce6f39d820b491ce05d7c017ad168fce7d6
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reduce the register count by 1 to avoid xmm6 and unnecessarily
penalizing the other users of the base macro
Change-Id: I59605c9a41a31c1b74f67ec06a40d1a7f92c4699
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Replace MMX with SSE2, reduce mem access to left neighbor,
loop unrolled.
Change-Id: I941be915af809025f121ecc6c6443f73c9903e70
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MMX replaced with SSE2, same performance.
Change-Id: I2ab8f30a71e5fadbbc172fb385093dec1e11a696
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MMX replaced with SSE2, same performance.
Change-Id: Ic57855254e26757191933c948fac6aa047fadafc
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In 32-bit build with --enable-shared, there is a lot of
register pressure and register src_strideq is reused.
The code needs to use the stack based version of src_stride,
but this doesn't compile when used in an lea instruction.
This patch also fixes a related segmentation fault caused by the
implementation using src_strideq even though it has been
reused.
This patch also fixes the HBD subpel variance tests that fail
when compiled without disable-optimizations.
These failures were caused by local variables in the assembler
routines colliding with the caller's stack frame.
Change-Id: Ice9d4dafdcbdc6038ad5ee7c1c09a8f06deca362
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H/V intra mode was only enabled for bsize < 16x16,
enable it also for bsize=16x16.
Metrics are neutral with this change:
Overall very small gain (0.1%), small visual gain on some RTC clips.
Change-Id: Ib2d7a44382433bfc11cf324aa3cc5c382ea9e088
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Replace MMX with SSE2, reduce psadbw ops which may help Silvermont.
Change-Id: Ic7aec15245c9e5b2f3903dc7631f38e60be7c93d
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Change-Id: I3ec08e10d9ebf6d8b8a03004a320523f926e5cc4
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This also fixes a compiling error under --enable-vp9_highbitdepth.
Change-Id: I9d1dcb95d3336d797eb3c23a4702c30b04355357
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Change-Id: I1a9635a9948458e6c83f5b58764b7e720d98e2ea
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Change-Id: I837551bdf87197bee8a193353bb31f4cff794787
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* changes:
Fixed interval, fixed Q 1 pass test patch.
1 pass VBR mode bug fix.
Fixed interval, fixed Q 1 pass test patch.
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This reverts commit e15fedb9258251bbb07def57e49e2bd1e0c4c538.
Change-Id: Ibf2bce008c727a9754f88814b7630095fa7b8253
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For testing implemented a fixed pattern and delta, 1 pass,
fixed Q, low delay mode.
This has not in any way been tuned or optimized.
Change-Id: Icf9b57c3bb16cc5c0726d5229009212af36eb6d9
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(copied from VP9)
The one pass VBR mode selects a Q range based on a
moving average of recent Q values. This calculation
should have been excluding arf overlay frames as these
are usually coded at the highest allowed value. Their
inclusion skews the average and can cause it to drift
upwards even when the clip as a whole is undershooting.
As such it can undermine correct adaptation of the allowed
Q range especially for easy content.
Change-Id: I9e12da84e12917e836b6e53ca4dfe4f150b9efb1
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For testing implemented a fixed pattern and delta, 1 pass,
fixed Q, low delay mode.
This has not in any way been tuned or optimized.
Change-Id: Idf5ee179b277fa15d07a97f14f2ce5bbaae80a04
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The one pass VBR mode selects a Q range based on a
moving average of recent Q values. This calculation
should have been excluding arf overlay frames as these
are usually coded at the highest allowed value. Their
inclusion skews the average and can cause it to drift
upwards even when the clip as a whole is undershooting.
As such it can undermine correct adaptation of the allowed
Q range especially for easy content.
Change-Id: I7d10fe4227262376aa2dc2a7aec0f1fd82bf11f9
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The culprit is on the decode side xd->lossless[i] setup was in wrong
location where segment features are not yet decoded.
Also on the encoder side, transform mode was not set consistently
between when tx_mode is selected and how tx_mode is enforced in
tx size selection.
Change-Id: I4c4c32188fda7530cadab9b46d4201f33f7ceca3
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