Age | Commit message (Collapse) | Author |
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Fix the valgrind error due to access uninitialized
memory in loopfilter.
Change-Id: I52fccf5ede845ee1f4c13d3bd909b8f220c0bdff
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This reverts commit 511d218c60b9b6c1ab9383db746815e907af0359.
In current form intrinsics break borg build.
Change-Id: Ied37936af841250ecff449802e69a3d3761c91b9
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Cleanups on frame refresh flags and external overrides.
Change-Id: Ia6a56fe1bde906b1dc3fcbf4ef1c7b207cd2df2d
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Under a configuration change, where the bitrate suddenly decreases,
the buffer level may be larger than maximum allowed (for that first frame to be encoded after change_config).
This change keeps it clipped to its maximum level.
Change-Id: I4d0b5b3d1fd8148600dd39e02bd630c9464baba5
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1. Made speed choices to be progressive
2. Adjusted rt speed settings to achieve better speed/quality
Overall, rt-5 gained 2.5% in compression/quality, encoding time of 720p
niklas clip goes from 137,052ms to 121,874ms
Change-Id: Ia6e7e1e15225395a868a2f1059c3db8e266e1600
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This commit further optimizes SSE2 operations in the second 1-D
inverse 16x16 DCT, with (<10) non-zero coefficients. The average
runtime of this module goes down from 779 cycles -> 725 cycles.
Change-Id: Iac31b123640d9b1e8f906e770702936b71f0ba7f
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Optimizing all SSSE3 assembly for convolution:
1. vp9_filter_block1d4_h8_sse2
2. vp9_filter_block1d8_h8_sse2
3. vp9_filter_block1d16_h8_sse2
4. vp9_filter_block1d4_v8_sse2
5. vp9_filter_block1d8_v8_sse2
6. vp9_filter_block1d16_v8_sse2
my optimization include:
-processing 2x8 elements in one 128 bit register instead of processing
8 elements in one 128 bit register.
-removing unecessary loads.
This optimization gives between 2.4% user level gain for 480p input
and 1.6% user level gain for 720p.
This Optimization done only for 64bit.
Change-Id: Icb586dc0c938b56699864fcee6c52fd43b36b969
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Add bilinearpredict_neon_intrinsics.c
- vp8_bilinear_predict4x4_neon
- vp8_bilinear_predict8x4_neon
- vp8_bilinear_predict8x8_neon
- vp8_bilinear_predict16x16_neon
Change-Id: I33dfa502881219841b442dda32b73220e51b716b
Signed-off-by: James Yu <james.yu@linaro.org>
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On Windows this fails with:
error C2440: 'initializing': cannot convert from int_mv to uint32_t
Change-Id: I51630efd0e83a0ce620c91aa7859dd6fc1572e99
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Change-Id: If7d3958653104f3e170853e931f8489de3ecf3cc
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Change-Id: Ib3212832953a3445fc5f021af0e1de7886f09b4f
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Move the code outside the conditions. The test sources themselves are
also required for Visual Studio.
Change-Id: Id5e93ebc7369e1807eba0b9dc4f7d0f18033d794
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This commit is the first patch optimizing SSE2 implementation of inverse
16x16 DCT with <10 non-zero coefficients. It focused on the first 1-D (row)
transformation. It exploits the fact that only top-left 4x4 block contains
non-zero coefficients, in a 2-D inverse 16x16 DCT with <10 coeffients.
The average runtime of idct16x16_10 unit is reduced from
883 cycles -> 779 cycles (12% faster).
For pedestrian_area_1080p 300 frames at 4000 kbps, the speed 2 runtime goes
down from 310651 ms -> 305910 ms. The decoding speed goes up from
80.37 fps -> 80.87 fps.
Change-Id: Ic6f3ac5a637a76c07ba73ddaafe318a699fea645
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Change-Id: Ib1d9628d2b538b6dc27b0db1fa7f40f70ff2072f
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Change-Id: I0c42a729038d0f4cb7bc07f587d066fcb1dfe9d9
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Change-Id: I6cdd670d66288dbd66228f38bba6b30502d25362
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Change-Id: I54513dc3b3321e0c0bb6b15ea5c34085ed80b4a4
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For systems without __builtin_clz() or _BitScanReverse(), taken from libwep
Change-Id: Iead257efc1772c466c79e1dc0356ed571d38d43e
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More intra optimizations will be added.
Change-Id: I33ae8d93f6002bf7b64cc2669602d9e6bfa5a6e8
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Optimizing the variance functions: vp9_variance16x16, vp9_variance32x32,
vp9_variance64x64, vp9_variance32x16, vp9_variance64x32,
vp9_mse16x16 by migrating to AVX2
some of the functions were optimized by processing 32 elements instead of 16.
some of the functions were optimized by processing 2 loop strides of 16
elements in a single 256 bit register
This optimization gives between 2.4% - 2.7% user level performance gain
and 42% function level gain.
Change-Id: I265ae08a2b0196057a224a86450153ef3aebd85d
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Change-Id: I44eb44eb3f36c05d916ef140ef42cc84f72f99ec
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Change-Id: I28e9cf9347acd7279df3b841863a248479633265
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Fix miss alignment of the frames contributing to the
error score and bit allocation for gf/arf groups.
Initial results slightly +.
Change-Id: Ie508bdcfdac52e592d48e1f13e01b3551b523deb
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