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2015-08-03VPX: Add rtcd support for scaling.Scott LaVarnway
Change-Id: If34bfb0d918967445aea7dc30cd7b55ebfedb1f2
2015-08-02Add _dspr2 to local function namesJingning Han
It avoids symbol conflicts between function names of various implementation versions. Change-Id: Iad79ebcb8e289457801812a7745c8380b5b06a46
2015-08-03Merge "Factor out mips/msa inverse transform implementations"Jingning Han
2015-08-02Merge "Add x86inc flag guard to inv_txfm_sse2.asm"Jingning Han
2015-08-02Add x86inc flag guard to inv_txfm_sse2.asmJingning Han
Fix the VS build failure. Change-Id: I4fb9d1c83980c4b52d5a848a9cb02ec72493dccb
2015-08-01vpx_convolve_copy_sse2: fix win64James Zern
xmm6-7 need to be stored Change-Id: I6c51559598d335946ec91be6246b49589c63b724
2015-08-01Factor out mips/msa inverse transform implementationsJingning Han
Move mips/msa inverse transform implementations from vp9 folder to vpx_dsp. Change-Id: Ic4cf3f05247c3c63db7b532a0e5000017a962391
2015-08-01Merge "Use precise header files in inverse transform msa implementations"Jingning Han
2015-08-01Merge "Factor inverse transform functions into vpx_dsp"Jingning Han
2015-08-01Merge "mips msa vp8 temporal filter optimization"Parag Salasakar
2015-08-01Merge "Add dynamic range notes to vp9_vector_var_c"Jingning Han
2015-07-31Merge "Turn off simple_model_rd_from_var at speed 4."Aℓex Converse
2015-07-31Add dynamic range notes to vp9_vector_var_cJingning Han
Change-Id: If536ad31046ecd9e2ecd9c21f52f8192c8153ad7
2015-07-31Use precise header files in inverse transform msa implementationsJingning Han
Change-Id: Ie8a79d9e2837842c3f60776b661cd42782b108d5
2015-07-31Merge "VP9_COPY_CONVOLVE_SSE2 optimization"James Zern
2015-07-31Factor inverse transform functions into vpx_dspJingning Han
This commit moves the module inverse transform functions from vp9 to vpx_dsp folder. The hybrid transform wrapper functions stay in the vp9 folder, since it involves codec-specific data structures. Change-Id: Ib066367c953d3d024c73ba65157bbd70a95c9ef8
2015-07-31Turn off simple_model_rd_from_var at speed 4.Alex Converse
This got erroneously changed during the refactor. This fixes SvcTest.TwoPassEncode2TemporalLayersWithMultipleFrameContextsAndTiles. Change-Id: Ifa5ab0e098396c5e2d10478db87df256eadfa4c7
2015-07-31Merge changes Iecdbbc34,I8b4db93fJames Zern
* changes: Android.mk: fix *_rtcd.h deps for armeabi-v7a Android.mk: add a dep on vpx_config.asm for x86_64
2015-07-31VP9_COPY_CONVOLVE_SSE2 optimizationScott LaVarnway
This function suffers from a couple problems in small core(tablets): -The load of the next iteration is blocked by the store of previous iteration -4k aliasing (between future store and older loads) -current small core machine are in-order machine and because of it the store will spin the rehabQ until the load is finished fixed by: - prefetching 2 lines ahead - unroll copy of 2 rows of block - pre-load all xmm regiters before the loop, final stores after the loop The function is optimized by: copy_convolve_sse2 64x64 - 16% copy_convolve_sse2 32x32 - 52% copy_convolve_sse2 16x16 - 6% copy_convolve_sse2 8x8 - 2.5% copy_convolve_sse2 4x4 - 2.7% credit goes to Tom Craver(tom.r.craver@intel.com) and Ilya Albrekht(ilya.albrekht@intel.com) Change-Id: I63d3428799c50b2bf7b5677c8268bacb9fc29671
2015-07-31Merge "Fix compiler warning in mips/dspr2"Jingning Han
2015-07-31Merge "Compute skippable inside the block_rd_txfm loop."Aℓex Converse
2015-07-31Fix compiler warning in mips/dspr2Jingning Han
This commit fixes the mix declaration and definition warning when mips/dspr2 is turned on. Change-Id: I633d6fe42368b9ac35b106786ebac6969ad53552
2015-07-31Merge changes Ic1ce346a,Ic0b4e92cAℓex Converse
* changes: Simplify model_rd_for_sb HBD ifdefs Simplify dist_block HBD ifdefs
2015-07-31Compute skippable inside the block_rd_txfm loop.Alex Converse
Change-Id: Iaa43aeeb7a2074495e00cdb83bb551c3f13d3ed2
2015-07-31Merge "Refactor mips/dspr2 on convolution."Zoe Liu
2015-07-31Merge "Code refactor on InterpKernel"Zoe Liu
2015-07-31Simplify model_rd_for_sb HBD ifdefsAlex Converse
Change-Id: Ic1ce346a053800ae3b2d77178f46e6a388357f6d
2015-07-31Simplify dist_block HBD ifdefsAlex Converse
Change-Id: Ic0b4e92cbaf813bcca8a8e9052c936c2e025e114
2015-07-31Merge "Short circuit rate_block in block_rd_txfm."Aℓex Converse
2015-07-31Refactor mips/dspr2 on convolution.Zoe Liu
Change-Id: If59a39d5a92c261537342726f94bb7f7f26dfff3
2015-07-31Code refactor on InterpKernelZoe Liu
It in essence refactors the code for both the interpolation filtering and the convolution. This change includes the moving of all the files as well as the changing of the code from vp9_ prefix to vpx_ prefix accordingly, for underneath architectures: (1) x86; (2) arm/neon; and (3) mips/msa. The work on mips/drsp2 will be done in a separate change list. Change-Id: Ic3ce7fb7f81210db7628b373c73553db68793c46
2015-07-31Give skip_txfm constants names.Alex Converse
This is using a define instead of an enum to keep byte packing. Change-Id: I3abb07c8bfe377e19be4531b624af7b7b4207792
2015-07-31Short circuit rate_block in block_rd_txfm.Alex Converse
Don't run rate_block (cost_coeffs) if distortion alone is enough to surpass best_rd. This decreases 2nd pass runtime on HD at speed 2 by about 2%. There is zero effect on output if tx_cache is removed. Change-Id: Ia3b1cc77bfbe6ee988c395fde06c0eb92940b784
2015-07-31mips msa vp8 temporal filter optimizationParag Salasakar
average improvement ~2x-3x Change-Id: I05593bed583234dc7809aaec6cab82773a29505d
2015-07-31mips msa vp8 block subtract optimizationParag Salasakar
average improvement ~2x-3x Change-Id: I30abf4c92cddcc9e87b7a40d4106076e1ec701c2
2015-07-31Merge "mips msa vp8 quantize optimization"Parag Salasakar
2015-07-30Remove tx cache and speed up tx size selectionYunqing Wang
1. The RD scores obtained during the tx size selection were stored in the tx cache, and used to help make the tx decision for the following frames. This wasn't used anymore in VP9 encoder. Recovered the related decision making code from 1.5+ years ago, and borg tests didn't show any quality gain. This patch removed it to lower the complexity. 2. An optimization was done after the above refactoring. If the tx_mode is not TX_MODE_SELECT, we only need to test the chosen tx size instead of all posible tx sizes. This gave a 1.5% average speed gain at speed 2, and a 1% average speed gain at speed 3. Change-Id: Id8cd650e066a8cef33829d8c15388a8138adc78c
2015-07-30Merge "Convert simple_model_rd_from_var from a speed check to a speed feature."Aℓex Converse
2015-07-30Merge "Exclude vpx intra prediction functions in vp8-only build"Hui Su
2015-07-30Convert simple_model_rd_from_var from a speed check to a speed feature.Alex Converse
Change-Id: I8877025e172fff29bc4e270790211463b676b4d7
2015-07-30Exclude vpx intra prediction functions in vp8-only buildhui su
Currently vp8 is not using the intra prediction functions in vpx_dsp. Change-Id: I1522b5f5cb12a81999fb126cf7c62c70259e7a52
2015-07-30Android.mk: fix *_rtcd.h deps for armeabi-v7aJames Zern
strip '.neon' so *_rtcd.h depends on the correct file Change-Id: Iecdbbc34c9ce5c6d0a4b466332d52f4e6a0cb128
2015-07-30mips msa vp8 quantize optimizationParag Salasakar
average improvement ~2x-3x Change-Id: I6fc37191bf9cb5a67e1af9787d0d27659c17bdba
2015-07-30Cleanup rdcost_block_argsAlex Converse
Change-Id: I9d613cbe9e76b5dd15e935878ef9fd04521690ba
2015-07-30Merge "Clean up some casts."Aℓex Converse
2015-07-30Merge "Cosmetics - Fix header file order in unit tests"Jingning Han
2015-07-29Cosmetics - Fix header file order in unit testsJingning Han
Change-Id: I9582a8d74990125b71e8fe620f7f3f2585a30798
2015-07-30mips msa vp8 fdct optimizationParag Salasakar
average improvement ~2x-4x Change-Id: Id0bc600440f7ef53348f585ebadb1ac6869e9a00
2015-07-30Merge "mips msa vp8 post proc optimization"Parag Salasakar
2015-07-30Merge "Comment zcoeff_blk."Aℓex Converse
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