diff options
Diffstat (limited to 'vp8')
| -rw-r--r-- | vp8/common/common.h | 8 | ||||
| -rw-r--r-- | vp8/common/mips/msa/idct_msa.c | 12 | ||||
| -rw-r--r-- | vp8/common/mips/msa/loopfilter_filters_msa.c | 24 | ||||
| -rw-r--r-- | vp8/common/mips/msa/sixtap_filter_msa.c | 16 | ||||
| -rw-r--r-- | vp8/common/mips/msa/vp8_macros_msa.h | 460 | ||||
| -rw-r--r-- | vp8/encoder/mcomp.c | 36 | ||||
| -rw-r--r-- | vp8/encoder/mips/msa/dct_msa.c | 8 | ||||
| -rw-r--r-- | vp8/encoder/mips/msa/temporal_filter_msa.c | 2 |
8 files changed, 283 insertions, 283 deletions
diff --git a/vp8/common/common.h b/vp8/common/common.h index 8c5cff675..2c30e8d6c 100644 --- a/vp8/common/common.h +++ b/vp8/common/common.h @@ -24,18 +24,18 @@ extern "C" { /* Only need this for fixed-size arrays, for structs just assign. */ #define vp8_copy(Dest, Src) \ - do { \ + { \ assert(sizeof(Dest) == sizeof(Src)); \ memcpy(Dest, Src, sizeof(Src)); \ - } while (0) + } /* Use this for variably-sized arrays. */ #define vp8_copy_array(Dest, Src, N) \ - do { \ + { \ assert(sizeof(*(Dest)) == sizeof(*(Src))); \ memcpy(Dest, Src, (N) * sizeof(*(Src))); \ - } while (0) + } #define vp8_zero(Dest) memset(&(Dest), 0, sizeof(Dest)); diff --git a/vp8/common/mips/msa/idct_msa.c b/vp8/common/mips/msa/idct_msa.c index fdc3f5c89..efad0c29f 100644 --- a/vp8/common/mips/msa/idct_msa.c +++ b/vp8/common/mips/msa/idct_msa.c @@ -16,14 +16,14 @@ static const int32_t cospi8sqrt2minus1 = 20091; static const int32_t sinpi8sqrt2 = 35468; #define TRANSPOSE_TWO_4x4_H(in0, in1, in2, in3, out0, out1, out2, out3) \ - do { \ + { \ v8i16 s4_m, s5_m, s6_m, s7_m; \ \ TRANSPOSE8X4_SH_SH(in0, in1, in2, in3, s4_m, s5_m, s6_m, s7_m); \ ILVR_D2_SH(s6_m, s4_m, s7_m, s5_m, out0, out2); \ out1 = (v8i16)__msa_ilvl_d((v2i64)s6_m, (v2i64)s4_m); \ out3 = (v8i16)__msa_ilvl_d((v2i64)s7_m, (v2i64)s5_m); \ - } while (0) + } #define EXPAND_TO_H_MULTIPLY_SINPI8SQRT2_PCK_TO_W(in) \ ({ \ @@ -43,7 +43,7 @@ static const int32_t sinpi8sqrt2 = 35468; }) #define VP8_IDCT_1D_H(in0, in1, in2, in3, out0, out1, out2, out3) \ - do { \ + { \ v8i16 a1_m, b1_m, c1_m, d1_m; \ v8i16 c_tmp1_m, c_tmp2_m, d_tmp1_m, d_tmp2_m; \ v8i16 const_cospi8sqrt2minus1_m; \ @@ -62,10 +62,10 @@ static const int32_t sinpi8sqrt2 = 35468; d_tmp2_m = EXPAND_TO_H_MULTIPLY_SINPI8SQRT2_PCK_TO_W(in3); \ d1_m = d_tmp1_m + d_tmp2_m; \ BUTTERFLY_4(a1_m, b1_m, c1_m, d1_m, out0, out1, out2, out3); \ - } while (0) + } #define VP8_IDCT_1D_W(in0, in1, in2, in3, out0, out1, out2, out3) \ - do { \ + { \ v4i32 a1_m, b1_m, c1_m, d1_m; \ v4i32 c_tmp1_m, c_tmp2_m, d_tmp1_m, d_tmp2_m; \ v4i32 const_cospi8sqrt2minus1_m, sinpi8_sqrt2_m; \ @@ -81,7 +81,7 @@ static const int32_t sinpi8sqrt2 = 35468; d_tmp2_m = (in3 * sinpi8_sqrt2_m) >> 16; \ d1_m = d_tmp1_m + d_tmp2_m; \ BUTTERFLY_4(a1_m, b1_m, c1_m, d1_m, out0, out1, out2, out3); \ - } while (0) + } static void idct4x4_addblk_msa(int16_t *input, uint8_t *pred, int32_t pred_stride, uint8_t *dest, diff --git a/vp8/common/mips/msa/loopfilter_filters_msa.c b/vp8/common/mips/msa/loopfilter_filters_msa.c index 642fe96c8..98a4fc09a 100644 --- a/vp8/common/mips/msa/loopfilter_filters_msa.c +++ b/vp8/common/mips/msa/loopfilter_filters_msa.c @@ -13,7 +13,7 @@ #include "vp8/common/mips/msa/vp8_macros_msa.h" #define VP8_SIMPLE_MASK(p1, p0, q0, q1, b_limit, mask) \ - do { \ + { \ v16u8 p1_a_sub_q1, p0_a_sub_q0; \ \ p0_a_sub_q0 = __msa_asub_u_b(p0, q0); \ @@ -22,10 +22,10 @@ p0_a_sub_q0 = __msa_adds_u_b(p0_a_sub_q0, p0_a_sub_q0); \ mask = __msa_adds_u_b(p0_a_sub_q0, p1_a_sub_q1); \ mask = ((v16u8)mask <= b_limit); \ - } while (0) + } #define VP8_LPF_FILTER4_4W(p1, p0, q0, q1, mask, hev) \ - do { \ + { \ v16i8 p1_m, p0_m, q0_m, q1_m, filt, q0_sub_p0, t1, t2; \ const v16i8 cnst4b = __msa_ldi_b(4); \ const v16i8 cnst3b = __msa_ldi_b(3); \ @@ -57,10 +57,10 @@ q1 = __msa_xori_b((v16u8)q1_m, 0x80); \ p1_m = __msa_adds_s_b(p1_m, filt); \ p1 = __msa_xori_b((v16u8)p1_m, 0x80); \ - } while (0) + } #define VP8_SIMPLE_FILT(p1_in, p0_in, q0_in, q1_in, mask) \ - do { \ + { \ v16i8 p1_m, p0_m, q0_m, q1_m, filt, filt1, filt2; \ v16i8 q0_sub_p0; \ const v16i8 cnst4b = __msa_ldi_b(4); \ @@ -85,10 +85,10 @@ p0_m = __msa_adds_s_b(p0_m, filt2); \ q0_in = __msa_xori_b((v16u8)q0_m, 0x80); \ p0_in = __msa_xori_b((v16u8)p0_m, 0x80); \ - } while (0) + } #define VP8_MBFILTER(p2, p1, p0, q0, q1, q2, mask, hev) \ - do { \ + { \ v16i8 p2_m, p1_m, p0_m, q2_m, q1_m, q0_m; \ v16i8 u, filt, t1, t2, filt_sign, q0_sub_p0; \ v8i16 filt_r, filt_l, u_r, u_l; \ @@ -163,12 +163,12 @@ p0_m = __msa_adds_s_b(p0_m, u); \ q0 = __msa_xori_b((v16u8)q0_m, 0x80); \ p0 = __msa_xori_b((v16u8)p0_m, 0x80); \ - } while (0) + } #define LPF_MASK_HEV(p3_in, p2_in, p1_in, p0_in, q0_in, q1_in, q2_in, q3_in, \ limit_in, b_limit_in, thresh_in, hev_out, mask_out, \ flat_out) \ - do { \ + { \ v16u8 p3_asub_p2_m, p2_asub_p1_m, p1_asub_p0_m, q1_asub_q0_m; \ v16u8 p1_asub_q1_m, p0_asub_q0_m, q3_asub_q2_m, q2_asub_q1_m; \ \ @@ -193,10 +193,10 @@ mask_out = __msa_max_u_b(q2_asub_q1_m, mask_out); \ mask_out = (limit_in) < (v16u8)mask_out; \ mask_out = __msa_xori_b(mask_out, 0xff); \ - } while (0) + } #define VP8_ST6x1_UB(in0, in0_idx, in1, in1_idx, pdst, stride) \ - do { \ + { \ uint16_t tmp0_h; \ uint32_t tmp0_w; \ \ @@ -204,7 +204,7 @@ tmp0_h = __msa_copy_u_h((v8i16)in1, in1_idx); \ SW(tmp0_w, pdst); \ SH(tmp0_h, pdst + stride); \ - } while (0) + } static void loop_filter_horizontal_4_dual_msa(uint8_t *src, int32_t pitch, const uint8_t *b_limit0_ptr, diff --git a/vp8/common/mips/msa/sixtap_filter_msa.c b/vp8/common/mips/msa/sixtap_filter_msa.c index 46f301c91..b0affcff0 100644 --- a/vp8/common/mips/msa/sixtap_filter_msa.c +++ b/vp8/common/mips/msa/sixtap_filter_msa.c @@ -51,7 +51,7 @@ static const uint8_t vp8_mc_filt_mask_arr[16 * 3] = { #define HORIZ_6TAP_4WID_4VECS_FILT(src0, src1, src2, src3, mask0, mask1, \ mask2, filt0, filt1, filt2, out0, out1) \ - do { \ + { \ v16i8 vec0_m, vec1_m, vec2_m, vec3_m, vec4_m, vec5_m; \ \ VSHF_B2_SB(src0, src1, src2, src3, mask0, mask0, vec0_m, vec1_m); \ @@ -60,12 +60,12 @@ static const uint8_t vp8_mc_filt_mask_arr[16 * 3] = { DPADD_SB2_SH(vec2_m, vec3_m, filt1, filt1, out0, out1); \ VSHF_B2_SB(src0, src1, src2, src3, mask2, mask2, vec4_m, vec5_m); \ DPADD_SB2_SH(vec4_m, vec5_m, filt2, filt2, out0, out1); \ - } while (0) + } #define HORIZ_6TAP_8WID_4VECS_FILT(src0, src1, src2, src3, mask0, mask1, \ mask2, filt0, filt1, filt2, out0, out1, \ out2, out3) \ - do { \ + { \ v16i8 vec0_m, vec1_m, vec2_m, vec3_m, vec4_m, vec5_m, vec6_m, vec7_m; \ \ VSHF_B2_SB(src0, src0, src1, src1, mask0, mask0, vec0_m, vec1_m); \ @@ -80,7 +80,7 @@ static const uint8_t vp8_mc_filt_mask_arr[16 * 3] = { out0, out1, out2, out3); \ DPADD_SB4_SH(vec4_m, vec5_m, vec6_m, vec7_m, filt2, filt2, filt2, filt2, \ out0, out1, out2, out3); \ - } while (0) + } #define FILT_4TAP_DPADD_S_H(vec0, vec1, filt0, filt1) \ ({ \ @@ -108,18 +108,18 @@ static const uint8_t vp8_mc_filt_mask_arr[16 * 3] = { #define HORIZ_4TAP_4WID_4VECS_FILT(src0, src1, src2, src3, mask0, mask1, \ filt0, filt1, out0, out1) \ - do { \ + { \ v16i8 vec0_m, vec1_m, vec2_m, vec3_m; \ \ VSHF_B2_SB(src0, src1, src2, src3, mask0, mask0, vec0_m, vec1_m); \ DOTP_SB2_SH(vec0_m, vec1_m, filt0, filt0, out0, out1); \ VSHF_B2_SB(src0, src1, src2, src3, mask1, mask1, vec2_m, vec3_m); \ DPADD_SB2_SH(vec2_m, vec3_m, filt1, filt1, out0, out1); \ - } while (0) + } #define HORIZ_4TAP_8WID_4VECS_FILT(src0, src1, src2, src3, mask0, mask1, \ filt0, filt1, out0, out1, out2, out3) \ - do { \ + { \ v16i8 vec0_m, vec1_m, vec2_m, vec3_m; \ \ VSHF_B2_SB(src0, src0, src1, src1, mask0, mask0, vec0_m, vec1_m); \ @@ -130,7 +130,7 @@ static const uint8_t vp8_mc_filt_mask_arr[16 * 3] = { VSHF_B2_SB(src2, src2, src3, src3, mask1, mask1, vec2_m, vec3_m); \ DPADD_SB4_SH(vec0_m, vec1_m, vec2_m, vec3_m, filt1, filt1, filt1, filt1, \ out0, out1, out2, out3); \ - } while (0) + } static void common_hz_6t_4x4_msa(uint8_t *RESTRICT src, int32_t src_stride, uint8_t *RESTRICT dst, int32_t dst_stride, diff --git a/vp8/common/mips/msa/vp8_macros_msa.h b/vp8/common/mips/msa/vp8_macros_msa.h index 4c446a762..14f83799f 100644 --- a/vp8/common/mips/msa/vp8_macros_msa.h +++ b/vp8/common/mips/msa/vp8_macros_msa.h @@ -85,7 +85,7 @@ #endif // (__mips == 64) #define SH(val, pdst) \ - do { \ + { \ uint8_t *pdst_m = (uint8_t *)(pdst); \ const uint16_t val_m = (val); \ \ @@ -93,10 +93,10 @@ \ : [pdst_m] "=m"(*pdst_m) \ : [val_m] "r"(val_m)); \ - } while (0) + } #define SW(val, pdst) \ - do { \ + { \ uint8_t *pdst_m = (uint8_t *)(pdst); \ const uint32_t val_m = (val); \ \ @@ -104,10 +104,10 @@ \ : [pdst_m] "=m"(*pdst_m) \ : [val_m] "r"(val_m)); \ - } while (0) + } #define SD(val, pdst) \ - do { \ + { \ uint8_t *pdst_m = (uint8_t *)(pdst); \ const uint64_t val_m = (val); \ \ @@ -115,7 +115,7 @@ \ : [pdst_m] "=m"(*pdst_m) \ : [val_m] "r"(val_m)); \ - } while (0) + } #else // !(__mips_isa_rev >= 6) #define LW(psrc) \ ({ \ @@ -161,7 +161,7 @@ }) #endif // (__mips == 64) #define SH(val, pdst) \ - do { \ + { \ uint8_t *pdst_m = (uint8_t *)(pdst); \ const uint16_t val_m = (val); \ \ @@ -169,10 +169,10 @@ \ : [pdst_m] "=m"(*pdst_m) \ : [val_m] "r"(val_m)); \ - } while (0) + } #define SW(val, pdst) \ - do { \ + { \ uint8_t *pdst_m = (uint8_t *)(pdst); \ const uint32_t val_m = (val); \ \ @@ -180,10 +180,10 @@ \ : [pdst_m] "=m"(*pdst_m) \ : [val_m] "r"(val_m)); \ - } while (0) + } #define SD(val, pdst) \ - do { \ + { \ uint8_t *pdst_m1 = (uint8_t *)(pdst); \ uint32_t val0_m, val1_m; \ \ @@ -192,7 +192,7 @@ \ SW(val0_m, pdst_m1); \ SW(val1_m, pdst_m1 + 4); \ - } while (0) + } #endif // (__mips_isa_rev >= 6) /* Description : Load 4 words with stride @@ -204,12 +204,12 @@ Load word in 'out3' from (psrc + 3 * stride) */ #define LW4(psrc, stride, out0, out1, out2, out3) \ - do { \ + { \ out0 = LW((psrc)); \ out1 = LW((psrc) + stride); \ out2 = LW((psrc) + 2 * stride); \ out3 = LW((psrc) + 3 * stride); \ - } while (0) + } /* Description : Load double words with stride Arguments : Inputs - psrc, stride @@ -218,15 +218,15 @@ Load double word in 'out1' from (psrc + stride) */ #define LD2(psrc, stride, out0, out1) \ - do { \ + { \ out0 = LD((psrc)); \ out1 = LD((psrc) + stride); \ - } while (0) + } #define LD4(psrc, stride, out0, out1, out2, out3) \ - do { \ + { \ LD2((psrc), stride, out0, out1); \ LD2((psrc) + 2 * stride, stride, out2, out3); \ - } while (0) + } /* Description : Store 4 words with stride Arguments : Inputs - in0, in1, in2, in3, pdst, stride @@ -236,12 +236,12 @@ Store word from 'in3' to (pdst + 3 * stride) */ #define SW4(in0, in1, in2, in3, pdst, stride) \ - do { \ + { \ SW(in0, (pdst)); \ SW(in1, (pdst) + stride); \ SW(in2, (pdst) + 2 * stride); \ SW(in3, (pdst) + 3 * stride); \ - } while (0) + } /* Description : Store 4 double words with stride Arguments : Inputs - in0, in1, in2, in3, pdst, stride @@ -251,12 +251,12 @@ Store double word from 'in3' to (pdst + 3 * stride) */ #define SD4(in0, in1, in2, in3, pdst, stride) \ - do { \ + { \ SD(in0, (pdst)); \ SD(in1, (pdst) + stride); \ SD(in2, (pdst) + 2 * stride); \ SD(in3, (pdst) + 3 * stride); \ - } while (0) + } /* Description : Load vectors with 16 byte elements with stride Arguments : Inputs - psrc, stride @@ -266,43 +266,43 @@ Load 16 byte elements in 'out1' from (psrc + stride) */ #define LD_B2(RTYPE, psrc, stride, out0, out1) \ - do { \ + { \ out0 = LD_B(RTYPE, (psrc)); \ out1 = LD_B(RTYPE, (psrc) + stride); \ - } while (0) + } #define LD_UB2(...) LD_B2(v16u8, __VA_ARGS__) #define LD_SB2(...) LD_B2(v16i8, __VA_ARGS__) #define LD_B3(RTYPE, psrc, stride, out0, out1, out2) \ - do { \ + { \ LD_B2(RTYPE, (psrc), stride, out0, out1); \ out2 = LD_B(RTYPE, (psrc) + 2 * stride); \ - } while (0) + } #define LD_UB3(...) LD_B3(v16u8, __VA_ARGS__) #define LD_SB3(...) LD_B3(v16i8, __VA_ARGS__) #define LD_B4(RTYPE, psrc, stride, out0, out1, out2, out3) \ - do { \ + { \ LD_B2(RTYPE, (psrc), stride, out0, out1); \ LD_B2(RTYPE, (psrc) + 2 * stride, stride, out2, out3); \ - } while (0) + } #define LD_UB4(...) LD_B4(v16u8, __VA_ARGS__) #define LD_SB4(...) LD_B4(v16i8, __VA_ARGS__) #define LD_B5(RTYPE, psrc, stride, out0, out1, out2, out3, out4) \ - do { \ + { \ LD_B4(RTYPE, (psrc), stride, out0, out1, out2, out3); \ out4 = LD_B(RTYPE, (psrc) + 4 * stride); \ - } while (0) + } #define LD_UB5(...) LD_B5(v16u8, __VA_ARGS__) #define LD_SB5(...) LD_B5(v16i8, __VA_ARGS__) #define LD_B8(RTYPE, psrc, stride, out0, out1, out2, out3, out4, out5, out6, \ out7) \ - do { \ + { \ LD_B4(RTYPE, (psrc), stride, out0, out1, out2, out3); \ LD_B4(RTYPE, (psrc) + 4 * stride, stride, out4, out5, out6, out7); \ - } while (0) + } #define LD_UB8(...) LD_B8(v16u8, __VA_ARGS__) #define LD_SB8(...) LD_B8(v16i8, __VA_ARGS__) @@ -313,17 +313,17 @@ Load 8 halfword elements in 'out1' from (psrc + stride) */ #define LD_H2(RTYPE, psrc, stride, out0, out1) \ - do { \ + { \ out0 = LD_H(RTYPE, (psrc)); \ out1 = LD_H(RTYPE, (psrc) + (stride)); \ - } while (0) + } #define LD_SH2(...) LD_H2(v8i16, __VA_ARGS__) #define LD_H4(RTYPE, psrc, stride, out0, out1, out2, out3) \ - do { \ + { \ LD_H2(RTYPE, (psrc), stride, out0, out1); \ LD_H2(RTYPE, (psrc) + 2 * stride, stride, out2, out3); \ - } while (0) + } #define LD_SH4(...) LD_H4(v8i16, __VA_ARGS__) /* Description : Load 2 vectors of signed word elements with stride @@ -332,10 +332,10 @@ Return Type - signed word */ #define LD_SW2(psrc, stride, out0, out1) \ - do { \ + { \ out0 = LD_SW((psrc)); \ out1 = LD_SW((psrc) + stride); \ - } while (0) + } /* Description : Store vectors of 16 byte elements with stride Arguments : Inputs - in0, in1, pdst, stride @@ -343,25 +343,25 @@ Store 16 byte elements from 'in1' to (pdst + stride) */ #define ST_B2(RTYPE, in0, in1, pdst, stride) \ - do { \ + { \ ST_B(RTYPE, in0, (pdst)); \ ST_B(RTYPE, in1, (pdst) + stride); \ - } while (0) + } #define ST_UB2(...) ST_B2(v16u8, __VA_ARGS__) #define ST_B4(RTYPE, in0, in1, in2, in3, pdst, stride) \ - do { \ + { \ ST_B2(RTYPE, in0, in1, (pdst), stride); \ ST_B2(RTYPE, in2, in3, (pdst) + 2 * stride, stride); \ - } while (0) + } #define ST_UB4(...) ST_B4(v16u8, __VA_ARGS__) #define ST_SB4(...) ST_B4(v16i8, __VA_ARGS__) #define ST_B8(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride) \ - do { \ + { \ ST_B4(RTYPE, in0, in1, in2, in3, pdst, stride); \ ST_B4(RTYPE, in4, in5, in6, in7, (pdst) + 4 * stride, stride); \ - } while (0) + } #define ST_UB8(...) ST_B8(v16u8, __VA_ARGS__) /* Description : Store vectors of 8 halfword elements with stride @@ -370,10 +370,10 @@ Store 8 halfword elements from 'in1' to (pdst + stride) */ #define ST_H2(RTYPE, in0, in1, pdst, stride) \ - do { \ + { \ ST_H(RTYPE, in0, (pdst)); \ ST_H(RTYPE, in1, (pdst) + stride); \ - } while (0) + } #define ST_SH2(...) ST_H2(v8i16, __VA_ARGS__) /* Description : Store vectors of word elements with stride @@ -382,10 +382,10 @@ Store 4 word elements from 'in1' to (pdst + stride) */ #define ST_SW2(in0, in1, pdst, stride) \ - do { \ + { \ ST_SW(in0, (pdst)); \ ST_SW(in1, (pdst) + stride); \ - } while (0) + } /* Description : Store 2x4 byte block to destination memory from input vector Arguments : Inputs - in, stidx, pdst, stride @@ -399,7 +399,7 @@ the GP register and stored to (pdst + 3 * stride) */ #define ST2x4_UB(in, stidx, pdst, stride) \ - do { \ + { \ uint16_t out0_m, out1_m, out2_m, out3_m; \ uint8_t *pblk_2x4_m = (uint8_t *)(pdst); \ \ @@ -412,7 +412,7 @@ SH(out1_m, pblk_2x4_m + stride); \ SH(out2_m, pblk_2x4_m + 2 * stride); \ SH(out3_m, pblk_2x4_m + 3 * stride); \ - } while (0) + } /* Description : Store 4x4 byte block to destination memory from input vector Arguments : Inputs - in0, in1, pdst, stride @@ -426,7 +426,7 @@ GP register and stored to (pdst + 3 * stride) */ #define ST4x4_UB(in0, in1, idx0, idx1, idx2, idx3, pdst, stride) \ - do { \ + { \ uint32_t out0_m, out1_m, out2_m, out3_m; \ uint8_t *pblk_4x4_m = (uint8_t *)(pdst); \ \ @@ -436,14 +436,14 @@ out3_m = __msa_copy_u_w((v4i32)in1, idx3); \ \ SW4(out0_m, out1_m, out2_m, out3_m, pblk_4x4_m, stride); \ - } while (0) + } #define ST4x8_UB(in0, in1, pdst, stride) \ - do { \ + { \ uint8_t *pblk_4x8 = (uint8_t *)(pdst); \ \ ST4x4_UB(in0, in0, 0, 1, 2, 3, pblk_4x8, stride); \ ST4x4_UB(in1, in1, 0, 1, 2, 3, pblk_4x8 + 4 * stride, stride); \ - } while (0) + } /* Description : Store 8x1 byte block to destination memory from input vector Arguments : Inputs - in, pdst @@ -451,12 +451,12 @@ GP register and stored to (pdst) */ #define ST8x1_UB(in, pdst) \ - do { \ + { \ uint64_t out0_m; \ \ out0_m = __msa_copy_u_d((v2i64)in, 0); \ SD(out0_m, pdst); \ - } while (0) + } /* Description : Store 8x2 byte block to destination memory from input vector Arguments : Inputs - in, pdst, stride @@ -466,7 +466,7 @@ GP register and stored to (pdst + stride) */ #define ST8x2_UB(in, pdst, stride) \ - do { \ + { \ uint64_t out0_m, out1_m; \ uint8_t *pblk_8x2_m = (uint8_t *)(pdst); \ \ @@ -475,7 +475,7 @@ \ SD(out0_m, pblk_8x2_m); \ SD(out1_m, pblk_8x2_m + stride); \ - } while (0) + } /* Description : Store 8x4 byte block to destination memory from input vectors @@ -490,7 +490,7 @@ GP register and stored to (pdst + 3 * stride) */ #define ST8x4_UB(in0, in1, pdst, stride) \ - do { \ + { \ uint64_t out0_m, out1_m, out2_m, out3_m; \ uint8_t *pblk_8x4_m = (uint8_t *)(pdst); \ \ @@ -500,7 +500,7 @@ out3_m = __msa_copy_u_d((v2i64)in1, 1); \ \ SD4(out0_m, out1_m, out2_m, out3_m, pblk_8x4_m, stride); \ - } while (0) + } /* Description : Immediate number of elements to slide with zero Arguments : Inputs - in0, in1, slide_val @@ -510,12 +510,12 @@ value specified in the 'slide_val' */ #define SLDI_B2_0(RTYPE, in0, in1, out0, out1, slide_val) \ - do { \ + { \ v16i8 zero_m = { 0 }; \ \ out0 = (RTYPE)__msa_sldi_b((v16i8)zero_m, (v16i8)in0, slide_val); \ out1 = (RTYPE)__msa_sldi_b((v16i8)zero_m, (v16i8)in1, slide_val); \ - } while (0) + } #define SLDI_B2_0_UB(...) SLDI_B2_0(v16u8, __VA_ARGS__) /* Description : Immediate number of elements to slide @@ -526,17 +526,17 @@ value specified in the 'slide_val' */ #define SLDI_B2(RTYPE, in0_0, in0_1, in1_0, in1_1, out0, out1, slide_val) \ - do { \ + { \ out0 = (RTYPE)__msa_sldi_b((v16i8)in0_0, (v16i8)in1_0, slide_val); \ out1 = (RTYPE)__msa_sldi_b((v16i8)in0_1, (v16i8)in1_1, slide_val); \ - } while (0) + } #define SLDI_B3(RTYPE, in0_0, in0_1, in0_2, in1_0, in1_1, in1_2, out0, out1, \ out2, slide_val) \ - do { \ + { \ SLDI_B2(RTYPE, in0_0, in0_1, in1_0, in1_1, out0, out1, slide_val); \ out2 = (RTYPE)__msa_sldi_b((v16i8)in0_2, (v16i8)in1_2, slide_val); \ - } while (0) + } #define SLDI_B3_UH(...) SLDI_B3(v8u16, __VA_ARGS__) /* Description : Shuffle byte vector elements as per mask vector @@ -547,20 +547,20 @@ 'out0' as per control vector 'mask0' */ #define VSHF_B2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_vshf_b((v16i8)mask0, (v16i8)in1, (v16i8)in0); \ out1 = (RTYPE)__msa_vshf_b((v16i8)mask1, (v16i8)in3, (v16i8)in2); \ - } while (0) + } #define VSHF_B2_UB(...) VSHF_B2(v16u8, __VA_ARGS__) #define VSHF_B2_SB(...) VSHF_B2(v16i8, __VA_ARGS__) #define VSHF_B2_UH(...) VSHF_B2(v8u16, __VA_ARGS__) #define VSHF_B3(RTYPE, in0, in1, in2, in3, in4, in5, mask0, mask1, mask2, \ out0, out1, out2) \ - do { \ + { \ VSHF_B2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1); \ out2 = (RTYPE)__msa_vshf_b((v16i8)mask2, (v16i8)in5, (v16i8)in4); \ - } while (0) + } #define VSHF_B3_SB(...) VSHF_B3(v16i8, __VA_ARGS__) /* Description : Shuffle halfword vector elements as per mask vector @@ -571,10 +571,10 @@ 'out0' as per control vector 'mask0' */ #define VSHF_H2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_vshf_h((v8i16)mask0, (v8i16)in1, (v8i16)in0); \ out1 = (RTYPE)__msa_vshf_h((v8i16)mask1, (v8i16)in3, (v8i16)in2); \ - } while (0) + } #define VSHF_H2_SH(...) VSHF_H2(v8i16, __VA_ARGS__) /* Description : Dot product of byte vector elements @@ -588,18 +588,18 @@ are added together and written to the 'out0' vector */ #define DOTP_UB2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_dotp_u_h((v16u8)mult0, (v16u8)cnst0); \ out1 = (RTYPE)__msa_dotp_u_h((v16u8)mult1, (v16u8)cnst1); \ - } while (0) + } #define DOTP_UB2_UH(...) DOTP_UB2(v8u16, __VA_ARGS__) #define DOTP_UB4(RTYPE, mult0, mult1, mult2, mult3, cnst0, cnst1, cnst2, \ cnst3, out0, out1, out2, out3) \ - do { \ + { \ DOTP_UB2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1); \ DOTP_UB2(RTYPE, mult2, mult3, cnst2, cnst3, out2, out3); \ - } while (0) + } #define DOTP_UB4_UH(...) DOTP_UB4(v8u16, __VA_ARGS__) /* Description : Dot product of byte vector elements @@ -613,18 +613,18 @@ are added together and written to the 'out0' vector */ #define DOTP_SB2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_dotp_s_h((v16i8)mult0, (v16i8)cnst0); \ out1 = (RTYPE)__msa_dotp_s_h((v16i8)mult1, (v16i8)cnst1); \ - } while (0) + } #define DOTP_SB2_SH(...) DOTP_SB2(v8i16, __VA_ARGS__) #define DOTP_SB4(RTYPE, mult0, mult1, mult2, mult3, cnst0, cnst1, cnst2, \ cnst3, out0, out1, out2, out3) \ - do { \ + { \ DOTP_SB2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1); \ DOTP_SB2(RTYPE, mult2, mult3, cnst2, cnst3, out2, out3); \ - } while (0) + } #define DOTP_SB4_SH(...) DOTP_SB4(v8i16, __VA_ARGS__) /* Description : Dot product of halfword vector elements @@ -638,17 +638,17 @@ are added together and written to the 'out0' vector */ #define DOTP_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_dotp_s_w((v8i16)mult0, (v8i16)cnst0); \ out1 = (RTYPE)__msa_dotp_s_w((v8i16)mult1, (v8i16)cnst1); \ - } while (0) + } #define DOTP_SH4(RTYPE, mult0, mult1, mult2, mult3, cnst0, cnst1, cnst2, \ cnst3, out0, out1, out2, out3) \ - do { \ + { \ DOTP_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1); \ DOTP_SH2(RTYPE, mult2, mult3, cnst2, cnst3, out2, out3); \ - } while (0) + } #define DOTP_SH4_SW(...) DOTP_SH4(v4i32, __VA_ARGS__) /* Description : Dot product of word vector elements @@ -662,10 +662,10 @@ are added together and written to the 'out0' vector */ #define DOTP_SW2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_dotp_s_d((v4i32)mult0, (v4i32)cnst0); \ out1 = (RTYPE)__msa_dotp_s_d((v4i32)mult1, (v4i32)cnst1); \ - } while (0) + } #define DOTP_SW2_SD(...) DOTP_SW2(v2i64, __VA_ARGS__) /* Description : Dot product & addition of byte vector elements @@ -679,18 +679,18 @@ are added to the 'out0' vector */ #define DPADD_SB2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_dpadd_s_h((v8i16)out0, (v16i8)mult0, (v16i8)cnst0); \ out1 = (RTYPE)__msa_dpadd_s_h((v8i16)out1, (v16i8)mult1, (v16i8)cnst1); \ - } while (0) + } #define DPADD_SB2_SH(...) DPADD_SB2(v8i16, __VA_ARGS__) #define DPADD_SB4(RTYPE, mult0, mult1, mult2, mult3, cnst0, cnst1, cnst2, \ cnst3, out0, out1, out2, out3) \ - do { \ + { \ DPADD_SB2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1); \ DPADD_SB2(RTYPE, mult2, mult3, cnst2, cnst3, out2, out3); \ - } while (0) + } #define DPADD_SB4_SH(...) DPADD_SB4(v8i16, __VA_ARGS__) /* Description : Dot product & addition of halfword vector elements @@ -704,18 +704,18 @@ are added to the 'out0' vector */ #define DPADD_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_dpadd_s_w((v4i32)out0, (v8i16)mult0, (v8i16)cnst0); \ out1 = (RTYPE)__msa_dpadd_s_w((v4i32)out1, (v8i16)mult1, (v8i16)cnst1); \ - } while (0) + } #define DPADD_SH2_SW(...) DPADD_SH2(v4i32, __VA_ARGS__) #define DPADD_SH4(RTYPE, mult0, mult1, mult2, mult3, cnst0, cnst1, cnst2, \ cnst3, out0, out1, out2, out3) \ - do { \ + { \ DPADD_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1); \ DPADD_SH2(RTYPE, mult2, mult3, cnst2, cnst3, out2, out3); \ - } while (0) + } #define DPADD_SH4_SW(...) DPADD_SH4(v4i32, __VA_ARGS__) /* Description : Dot product & addition of double word vector elements @@ -729,10 +729,10 @@ are added to the 'out0' vector */ #define DPADD_SD2(RTYPE, mult0, mult1, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_dpadd_s_d((v2i64)out0, (v4i32)mult0, (v4i32)mult0); \ out1 = (RTYPE)__msa_dpadd_s_d((v2i64)out1, (v4i32)mult1, (v4i32)mult1); \ - } while (0) + } #define DPADD_SD2_SD(...) DPADD_SD2(v2i64, __VA_ARGS__) /* Description : Clips all signed halfword elements of input vector @@ -751,15 +751,15 @@ out_m; \ }) #define CLIP_SH2_0_255(in0, in1) \ - do { \ + { \ in0 = CLIP_SH_0_255(in0); \ in1 = CLIP_SH_0_255(in1); \ - } while (0) + } #define CLIP_SH4_0_255(in0, in1, in2, in3) \ - do { \ + { \ CLIP_SH2_0_255(in0, in1); \ CLIP_SH2_0_255(in2, in3); \ - } while (0) + } /* Description : Clips all signed word elements of input vector between 0 & 255 @@ -826,10 +826,10 @@ halfword result is written to 'out0' */ #define HADD_UB2(RTYPE, in0, in1, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_hadd_u_h((v16u8)in0, (v16u8)in0); \ out1 = (RTYPE)__msa_hadd_u_h((v16u8)in1, (v16u8)in1); \ - } while (0) + } #define HADD_UB2_UH(...) HADD_UB2(v8u16, __VA_ARGS__) /* Description : Horizontal subtraction of unsigned byte vector elements @@ -841,10 +841,10 @@ halfword result is written to 'out0' */ #define HSUB_UB2(RTYPE, in0, in1, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_hsub_u_h((v16u8)in0, (v16u8)in0); \ out1 = (RTYPE)__msa_hsub_u_h((v16u8)in1, (v16u8)in1); \ - } while (0) + } #define HSUB_UB2_SH(...) HSUB_UB2(v8i16, __VA_ARGS__) /* Description : Horizontal subtraction of signed halfword vector elements @@ -856,10 +856,10 @@ word result is written to 'out0' */ #define HSUB_UH2(RTYPE, in0, in1, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_hsub_s_w((v8i16)in0, (v8i16)in0); \ out1 = (RTYPE)__msa_hsub_s_w((v8i16)in1, (v8i16)in1); \ - } while (0) + } #define HSUB_UH2_SW(...) HSUB_UH2(v4i32, __VA_ARGS__) /* Description : Set element n input vector to GPR value @@ -869,10 +869,10 @@ Details : Set element 0 in vector 'out' to value specified in 'in0' */ #define INSERT_D2(RTYPE, in0, in1, out) \ - do { \ + { \ out = (RTYPE)__msa_insert_d((v2i64)out, 0, in0); \ out = (RTYPE)__msa_insert_d((v2i64)out, 1, in1); \ - } while (0) + } #define INSERT_D2_SB(...) INSERT_D2(v16i8, __VA_ARGS__) /* Description : Interleave even byte elements from vectors @@ -883,10 +883,10 @@ and written to 'out0' */ #define ILVEV_B2(RTYPE, in0, in1, in2, in3, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_ilvev_b((v16i8)in1, (v16i8)in0); \ out1 = (RTYPE)__msa_ilvev_b((v16i8)in3, (v16i8)in2); \ - } while (0) + } #define ILVEV_B2_UB(...) ILVEV_B2(v16u8, __VA_ARGS__) #define ILVEV_B2_SH(...) ILVEV_B2(v8i16, __VA_ARGS__) #define ILVEV_B2_SD(...) ILVEV_B2(v2i64, __VA_ARGS__) @@ -899,10 +899,10 @@ and written to 'out0' */ #define ILVEV_H2(RTYPE, in0, in1, in2, in3, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_ilvev_h((v8i16)in1, (v8i16)in0); \ out1 = (RTYPE)__msa_ilvev_h((v8i16)in3, (v8i16)in2); \ - } while (0) + } #define ILVEV_H2_UB(...) ILVEV_H2(v16u8, __VA_ARGS__) #define ILVEV_H2_SH(...) ILVEV_H2(v8i16, __VA_ARGS__) @@ -914,10 +914,10 @@ and written to 'out0' */ #define ILVEV_W2(RTYPE, in0, in1, in2, in3, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_ilvev_w((v4i32)in1, (v4i32)in0); \ out1 = (RTYPE)__msa_ilvev_w((v4i32)in3, (v4i32)in2); \ - } while (0) + } #define ILVEV_W2_SD(...) ILVEV_W2(v2i64, __VA_ARGS__) /* Description : Interleave even double word elements from vectors @@ -928,10 +928,10 @@ and written to 'out0' */ #define ILVEV_D2(RTYPE, in0, in1, in2, in3, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_ilvev_d((v2i64)in1, (v2i64)in0); \ out1 = (RTYPE)__msa_ilvev_d((v2i64)in3, (v2i64)in2); \ - } while (0) + } #define ILVEV_D2_UB(...) ILVEV_D2(v16u8, __VA_ARGS__) /* Description : Interleave left half of byte elements from vectors @@ -942,20 +942,20 @@ and written to 'out0'. */ #define ILVL_B2(RTYPE, in0, in1, in2, in3, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_ilvl_b((v16i8)in0, (v16i8)in1); \ out1 = (RTYPE)__msa_ilvl_b((v16i8)in2, (v16i8)in3); \ - } while (0) + } #define ILVL_B2_UB(...) ILVL_B2(v16u8, __VA_ARGS__) #define ILVL_B2_SB(...) ILVL_B2(v16i8, __VA_ARGS__) #define ILVL_B2_SH(...) ILVL_B2(v8i16, __VA_ARGS__) #define ILVL_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, \ out2, out3) \ - do { \ + { \ ILVL_B2(RTYPE, in0, in1, in2, in3, out0, out1); \ ILVL_B2(RTYPE, in4, in5, in6, in7, out2, out3); \ - } while (0) + } #define ILVL_B4_SB(...) ILVL_B4(v16i8, __VA_ARGS__) #define ILVL_B4_SH(...) ILVL_B4(v8i16, __VA_ARGS__) @@ -967,10 +967,10 @@ interleaved and written to 'out0'. */ #define ILVL_H2(RTYPE, in0, in1, in2, in3, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_ilvl_h((v8i16)in0, (v8i16)in1); \ out1 = (RTYPE)__msa_ilvl_h((v8i16)in2, (v8i16)in3); \ - } while (0) + } #define ILVL_H2_SH(...) ILVL_H2(v8i16, __VA_ARGS__) #define ILVL_H2_SW(...) ILVL_H2(v4i32, __VA_ARGS__) @@ -982,10 +982,10 @@ and written to 'out0'. */ #define ILVL_W2(RTYPE, in0, in1, in2, in3, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_ilvl_w((v4i32)in0, (v4i32)in1); \ out1 = (RTYPE)__msa_ilvl_w((v4i32)in2, (v4i32)in3); \ - } while (0) + } #define ILVL_W2_SH(...) ILVL_W2(v8i16, __VA_ARGS__) /* Description : Interleave right half of byte elements from vectors @@ -996,10 +996,10 @@ and written to out0. */ #define ILVR_B2(RTYPE, in0, in1, in2, in3, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_ilvr_b((v16i8)in0, (v16i8)in1); \ out1 = (RTYPE)__msa_ilvr_b((v16i8)in2, (v16i8)in3); \ - } while (0) + } #define ILVR_B2_UB(...) ILVR_B2(v16u8, __VA_ARGS__) #define ILVR_B2_SB(...) ILVR_B2(v16i8, __VA_ARGS__) #define ILVR_B2_SH(...) ILVR_B2(v8i16, __VA_ARGS__) @@ -1007,10 +1007,10 @@ #define ILVR_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, \ out2, out3) \ - do { \ + { \ ILVR_B2(RTYPE, in0, in1, in2, in3, out0, out1); \ ILVR_B2(RTYPE, in4, in5, in6, in7, out2, out3); \ - } while (0) + } #define ILVR_B4_UB(...) ILVR_B4(v16u8, __VA_ARGS__) #define ILVR_B4_SB(...) ILVR_B4(v16i8, __VA_ARGS__) #define ILVR_B4_UH(...) ILVR_B4(v8u16, __VA_ARGS__) @@ -1025,27 +1025,27 @@ interleaved and written to 'out0'. */ #define ILVR_H2(RTYPE, in0, in1, in2, in3, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_ilvr_h((v8i16)in0, (v8i16)in1); \ out1 = (RTYPE)__msa_ilvr_h((v8i16)in2, (v8i16)in3); \ - } while (0) + } #define ILVR_H2_SH(...) ILVR_H2(v8i16, __VA_ARGS__) #define ILVR_H2_SW(...) ILVR_H2(v4i32, __VA_ARGS__) #define ILVR_H4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, \ out2, out3) \ - do { \ + { \ ILVR_H2(RTYPE, in0, in1, in2, in3, out0, out1); \ ILVR_H2(RTYPE, in4, in5, in6, in7, out2, out3); \ - } while (0) + } #define ILVR_H4_SH(...) ILVR_H4(v8i16, __VA_ARGS__) #define ILVR_H4_SW(...) ILVR_H4(v4i32, __VA_ARGS__) #define ILVR_W2(RTYPE, in0, in1, in2, in3, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_ilvr_w((v4i32)in0, (v4i32)in1); \ out1 = (RTYPE)__msa_ilvr_w((v4i32)in2, (v4i32)in3); \ - } while (0) + } #define ILVR_W2_SH(...) ILVR_W2(v8i16, __VA_ARGS__) /* Description : Interleave right half of double word elements from vectors @@ -1056,20 +1056,20 @@ interleaved and written to 'out0'. */ #define ILVR_D2(RTYPE, in0, in1, in2, in3, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_ilvr_d((v2i64)(in0), (v2i64)(in1)); \ out1 = (RTYPE)__msa_ilvr_d((v2i64)(in2), (v2i64)(in3)); \ - } while (0) + } #define ILVR_D2_UB(...) ILVR_D2(v16u8, __VA_ARGS__) #define ILVR_D2_SB(...) ILVR_D2(v16i8, __VA_ARGS__) #define ILVR_D2_SH(...) ILVR_D2(v8i16, __VA_ARGS__) #define ILVR_D4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, \ out2, out3) \ - do { \ + { \ ILVR_D2(RTYPE, in0, in1, in2, in3, out0, out1); \ ILVR_D2(RTYPE, in4, in5, in6, in7, out2, out3); \ - } while (0) + } #define ILVR_D4_SB(...) ILVR_D4(v16i8, __VA_ARGS__) #define ILVR_D4_UB(...) ILVR_D4(v16u8, __VA_ARGS__) @@ -1081,28 +1081,28 @@ interleaved and written to 'out0' */ #define ILVRL_B2(RTYPE, in0, in1, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_ilvr_b((v16i8)in0, (v16i8)in1); \ out1 = (RTYPE)__msa_ilvl_b((v16i8)in0, (v16i8)in1); \ - } while (0) + } #define ILVRL_B2_UB(...) ILVRL_B2(v16u8, __VA_ARGS__) #define ILVRL_B2_SB(...) ILVRL_B2(v16i8, __VA_ARGS__) #define ILVRL_B2_UH(...) ILVRL_B2(v8u16, __VA_ARGS__) #define ILVRL_B2_SH(...) ILVRL_B2(v8i16, __VA_ARGS__) #define ILVRL_H2(RTYPE, in0, in1, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_ilvr_h((v8i16)in0, (v8i16)in1); \ out1 = (RTYPE)__msa_ilvl_h((v8i16)in0, (v8i16)in1); \ - } while (0) + } #define ILVRL_H2_SH(...) ILVRL_H2(v8i16, __VA_ARGS__) #define ILVRL_H2_SW(...) ILVRL_H2(v4i32, __VA_ARGS__) #define ILVRL_W2(RTYPE, in0, in1, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_ilvr_w((v4i32)in0, (v4i32)in1); \ out1 = (RTYPE)__msa_ilvl_w((v4i32)in0, (v4i32)in1); \ - } while (0) + } #define ILVRL_W2_UB(...) ILVRL_W2(v16u8, __VA_ARGS__) #define ILVRL_W2_SH(...) ILVRL_W2(v8i16, __VA_ARGS__) #define ILVRL_W2_SW(...) ILVRL_W2(v4i32, __VA_ARGS__) @@ -1116,10 +1116,10 @@ 'max_val' are written in place */ #define MAXI_SH2(RTYPE, in0, in1, max_val) \ - do { \ + { \ in0 = (RTYPE)__msa_maxi_s_h((v8i16)in0, (max_val)); \ in1 = (RTYPE)__msa_maxi_s_h((v8i16)in1, (max_val)); \ - } while (0) + } #define MAXI_SH2_SH(...) MAXI_SH2(v8i16, __VA_ARGS__) /* Description : Saturate the halfword element values to the max @@ -1133,10 +1133,10 @@ The results are written in place */ #define SAT_UH2(RTYPE, in0, in1, sat_val) \ - do { \ + { \ in0 = (RTYPE)__msa_sat_u_h((v8u16)in0, sat_val); \ in1 = (RTYPE)__msa_sat_u_h((v8u16)in1, sat_val); \ - } while (0) + } #define SAT_UH2_SH(...) SAT_UH2(v8i16, __VA_ARGS__) /* Description : Saturate the halfword element values to the max @@ -1150,17 +1150,17 @@ The results are written in place */ #define SAT_SH2(RTYPE, in0, in1, sat_val) \ - do { \ + { \ in0 = (RTYPE)__msa_sat_s_h((v8i16)in0, sat_val); \ in1 = (RTYPE)__msa_sat_s_h((v8i16)in1, sat_val); \ - } while (0) + } #define SAT_SH2_SH(...) SAT_SH2(v8i16, __VA_ARGS__) #define SAT_SH4(RTYPE, in0, in1, in2, in3, sat_val) \ - do { \ + { \ SAT_SH2(RTYPE, in0, in1, sat_val); \ SAT_SH2(RTYPE, in2, in3, sat_val); \ - } while (0) + } #define SAT_SH4_SH(...) SAT_SH4(v8i16, __VA_ARGS__) /* Description : Indexed halfword element values are replicated to all @@ -1173,18 +1173,18 @@ Valid index range for halfword operation is 0-7 */ #define SPLATI_H2(RTYPE, in, idx0, idx1, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_splati_h((v8i16)in, idx0); \ out1 = (RTYPE)__msa_splati_h((v8i16)in, idx1); \ - } while (0) + } #define SPLATI_H2_SB(...) SPLATI_H2(v16i8, __VA_ARGS__) #define SPLATI_H2_SH(...) SPLATI_H2(v8i16, __VA_ARGS__) #define SPLATI_H3(RTYPE, in, idx0, idx1, idx2, out0, out1, out2) \ - do { \ + { \ SPLATI_H2(RTYPE, in, idx0, idx1, out0, out1); \ out2 = (RTYPE)__msa_splati_h((v8i16)in, idx2); \ - } while (0) + } #define SPLATI_H3_SB(...) SPLATI_H3(v16i8, __VA_ARGS__) #define SPLATI_H3_SH(...) SPLATI_H3(v8i16, __VA_ARGS__) @@ -1200,10 +1200,10 @@ Valid index range for word operation is 0-3 */ #define SPLATI_W2(RTYPE, in, stidx, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_splati_w((v4i32)in, stidx); \ out1 = (RTYPE)__msa_splati_w((v4i32)in, (stidx + 1)); \ - } while (0) + } #define SPLATI_W2_SW(...) SPLATI_W2(v4i32, __VA_ARGS__) /* Description : Pack even byte elements of vector pairs @@ -1215,10 +1215,10 @@ half of 'out0'. */ #define PCKEV_B2(RTYPE, in0, in1, in2, in3, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_pckev_b((v16i8)in0, (v16i8)in1); \ out1 = (RTYPE)__msa_pckev_b((v16i8)in2, (v16i8)in3); \ - } while (0) + } #define PCKEV_B2_SB(...) PCKEV_B2(v16i8, __VA_ARGS__) #define PCKEV_B2_UB(...) PCKEV_B2(v16u8, __VA_ARGS__) #define PCKEV_B2_SH(...) PCKEV_B2(v8i16, __VA_ARGS__) @@ -1226,10 +1226,10 @@ #define PCKEV_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, \ out2, out3) \ - do { \ + { \ PCKEV_B2(RTYPE, in0, in1, in2, in3, out0, out1); \ PCKEV_B2(RTYPE, in4, in5, in6, in7, out2, out3); \ - } while (0) + } #define PCKEV_B4_SB(...) PCKEV_B4(v16i8, __VA_ARGS__) #define PCKEV_B4_UB(...) PCKEV_B4(v16u8, __VA_ARGS__) #define PCKEV_B4_SH(...) PCKEV_B4(v8i16, __VA_ARGS__) @@ -1243,18 +1243,18 @@ right half of 'out0'. */ #define PCKEV_H2(RTYPE, in0, in1, in2, in3, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_pckev_h((v8i16)in0, (v8i16)in1); \ out1 = (RTYPE)__msa_pckev_h((v8i16)in2, (v8i16)in3); \ - } while (0) + } #define PCKEV_H2_SH(...) PCKEV_H2(v8i16, __VA_ARGS__) #define PCKEV_H4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, \ out2, out3) \ - do { \ + { \ PCKEV_H2(RTYPE, in0, in1, in2, in3, out0, out1); \ PCKEV_H2(RTYPE, in4, in5, in6, in7, out2, out3); \ - } while (0) + } #define PCKEV_H4_SH(...) PCKEV_H4(v8i16, __VA_ARGS__) /* Description : Pack even double word elements of vector pairs @@ -1266,10 +1266,10 @@ half of 'out0'. */ #define PCKEV_D2(RTYPE, in0, in1, in2, in3, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_pckev_d((v2i64)in0, (v2i64)in1); \ out1 = (RTYPE)__msa_pckev_d((v2i64)in2, (v2i64)in3); \ - } while (0) + } #define PCKEV_D2_UB(...) PCKEV_D2(v16u8, __VA_ARGS__) #define PCKEV_D2_SH(...) PCKEV_D2(v8i16, __VA_ARGS__) @@ -1282,10 +1282,10 @@ the right half of 'out0'. */ #define PCKOD_D2(RTYPE, in0, in1, in2, in3, out0, out1) \ - do { \ + { \ out0 = (RTYPE)__msa_pckod_d((v2i64)in0, (v2i64)in1); \ out1 = (RTYPE)__msa_pckod_d((v2i64)in2, (v2i64)in3); \ - } while (0) + } #define PCKOD_D2_UB(...) PCKOD_D2(v16u8, __VA_ARGS__) #define PCKOD_D2_SH(...) PCKOD_D2(v8i16, __VA_ARGS__) @@ -1297,40 +1297,40 @@ logically xor'ed with 128 and the result is stored in-place. */ #define XORI_B2_128(RTYPE, in0, in1) \ - do { \ + { \ in0 = (RTYPE)__msa_xori_b((v16u8)in0, 128); \ in1 = (RTYPE)__msa_xori_b((v16u8)in1, 128); \ - } while (0) + } #define XORI_B2_128_UB(...) XORI_B2_128(v16u8, __VA_ARGS__) #define XORI_B2_128_SB(...) XORI_B2_128(v16i8, __VA_ARGS__) #define XORI_B3_128(RTYPE, in0, in1, in2) \ - do { \ + { \ XORI_B2_128(RTYPE, in0, in1); \ in2 = (RTYPE)__msa_xori_b((v16u8)in2, 128); \ - } while (0) + } #define XORI_B3_128_SB(...) XORI_B3_128(v16i8, __VA_ARGS__) #define XORI_B4_128(RTYPE, in0, in1, in2, in3) \ - do { \ + { \ XORI_B2_128(RTYPE, in0, in1); \ XORI_B2_128(RTYPE, in2, in3); \ - } while (0) + } #define XORI_B4_128_UB(...) XORI_B4_128(v16u8, __VA_ARGS__) #define XORI_B4_128_SB(...) XORI_B4_128(v16i8, __VA_ARGS__) #define XORI_B5_128(RTYPE, in0, in1, in2, in3, in4) \ - do { \ + { \ XORI_B3_128(RTYPE, in0, in1, in2); \ XORI_B2_128(RTYPE, in3, in4); \ - } while (0) + } #define XORI_B5_128_SB(...) XORI_B5_128(v16i8, __VA_ARGS__) #define XORI_B8_128(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7) \ - do { \ + { \ XORI_B4_128(RTYPE, in0, in1, in2, in3); \ XORI_B4_128(RTYPE, in4, in5, in6, in7); \ - } while (0) + } #define XORI_B8_128_SB(...) XORI_B8_128(v16i8, __VA_ARGS__) /* Description : Shift left all elements of vector (generic for all data types) @@ -1341,12 +1341,12 @@ the result is written in-place. */ #define SLLI_4V(in0, in1, in2, in3, shift) \ - do { \ + { \ in0 = in0 << shift; \ in1 = in1 << shift; \ in2 = in2 << shift; \ in3 = in3 << shift; \ - } while (0) + } /* Description : Arithmetic shift right all elements of vector (generic for all data types) @@ -1357,12 +1357,12 @@ the result is written in-place. 'shift' is a GP variable. */ #define SRA_4V(in0, in1, in2, in3, shift) \ - do { \ + { \ in0 = in0 >> shift; \ in1 = in1 >> shift; \ in2 = in2 >> shift; \ in3 = in3 >> shift; \ - } while (0) + } /* Description : Shift right arithmetic rounded words Arguments : Inputs - in0, in1, shift @@ -1375,16 +1375,16 @@ 'shift' is a vector. */ #define SRAR_W2(RTYPE, in0, in1, shift) \ - do { \ + { \ in0 = (RTYPE)__msa_srar_w((v4i32)in0, (v4i32)shift); \ in1 = (RTYPE)__msa_srar_w((v4i32)in1, (v4i32)shift); \ - } while (0) + } #define SRAR_W4(RTYPE, in0, in1, in2, in3, shift) \ - do { \ + { \ SRAR_W2(RTYPE, in0, in1, shift); \ SRAR_W2(RTYPE, in2, in3, shift); \ - } while (0) + } #define SRAR_W4_SW(...) SRAR_W4(v4i32, __VA_ARGS__) /* Description : Shift right arithmetic rounded (immediate) @@ -1397,32 +1397,32 @@ 'shift' is an immediate value. */ #define SRARI_H2(RTYPE, in0, in1, shift) \ - do { \ + { \ in0 = (RTYPE)__msa_srari_h((v8i16)in0, shift); \ in1 = (RTYPE)__msa_srari_h((v8i16)in1, shift); \ - } while (0) + } #define SRARI_H2_UH(...) SRARI_H2(v8u16, __VA_ARGS__) #define SRARI_H2_SH(...) SRARI_H2(v8i16, __VA_ARGS__) #define SRARI_H4(RTYPE, in0, in1, in2, in3, shift) \ - do { \ + { \ SRARI_H2(RTYPE, in0, in1, shift); \ SRARI_H2(RTYPE, in2, in3, shift); \ - } while (0) + } #define SRARI_H4_UH(...) SRARI_H4(v8u16, __VA_ARGS__) #define SRARI_H4_SH(...) SRARI_H4(v8i16, __VA_ARGS__) #define SRARI_W2(RTYPE, in0, in1, shift) \ - do { \ + { \ in0 = (RTYPE)__msa_srari_w((v4i32)in0, shift); \ in1 = (RTYPE)__msa_srari_w((v4i32)in1, shift); \ - } while (0) + } #define SRARI_W4(RTYPE, in0, in1, in2, in3, shift) \ - do { \ + { \ SRARI_W2(RTYPE, in0, in1, shift); \ SRARI_W2(RTYPE, in2, in3, shift); \ - } while (0) + } #define SRARI_W4_SW(...) SRARI_W4(v4i32, __VA_ARGS__) /* Description : Multiplication of pairs of vectors @@ -1432,15 +1432,15 @@ and the result is written to 'out0' */ #define MUL2(in0, in1, in2, in3, out0, out1) \ - do { \ + { \ out0 = in0 * in1; \ out1 = in2 * in3; \ - } while (0) + } #define MUL4(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, out2, out3) \ - do { \ + { \ MUL2(in0, in1, in2, in3, out0, out1); \ MUL2(in4, in5, in6, in7, out2, out3); \ - } while (0) + } /* Description : Addition of 2 pairs of vectors Arguments : Inputs - in0, in1, in2, in3 @@ -1449,15 +1449,15 @@ to 'out0'. */ #define ADD2(in0, in1, in2, in3, out0, out1) \ - do { \ + { \ out0 = in0 + in1; \ out1 = in2 + in3; \ - } while (0) + } #define ADD4(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, out2, out3) \ - do { \ + { \ ADD2(in0, in1, in2, in3, out0, out1); \ ADD2(in4, in5, in6, in7, out2, out3); \ - } while (0) + } /* Description : Subtraction of 2 pairs of vectors Arguments : Inputs - in0, in1, in2, in3 @@ -1466,17 +1466,17 @@ written to 'out0'. */ #define SUB2(in0, in1, in2, in3, out0, out1) \ - do { \ + { \ out0 = in0 - in1; \ out1 = in2 - in3; \ - } while (0) + } #define SUB4(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, out2, out3) \ - do { \ + { \ out0 = in0 - in1; \ out1 = in2 - in3; \ out2 = in4 - in5; \ out3 = in6 - in7; \ - } while (0) + } /* Description : Sign extend halfword elements from right half of the vector Arguments : Input - in (halfword vector) @@ -1487,12 +1487,12 @@ 4 word elements keeping sign intact */ #define UNPCK_R_SH_SW(in, out) \ - do { \ + { \ v8i16 sign_m; \ \ sign_m = __msa_clti_s_h((v8i16)in, 0); \ out = (v4i32)__msa_ilvr_h(sign_m, (v8i16)in); \ - } while (0) + } /* Description : Zero extend unsigned byte elements to halfword elements Arguments : Input - in (unsigned byte vector) @@ -1502,11 +1502,11 @@ Zero extended left half of vector is returned in 'out1' */ #define UNPCK_UB_SH(in, out0, out1) \ - do { \ + { \ v16i8 zero_m = { 0 }; \ \ ILVRL_B2_SH(zero_m, in, out0, out1); \ - } while (0) + } /* Description : Sign extend halfword elements from input vector and return the result in pair of vectors @@ -1520,12 +1520,12 @@ generate 4 signed word elements in 'out1' */ #define UNPCK_SH_SW(in, out0, out1) \ - do { \ + { \ v8i16 tmp_m; \ \ tmp_m = __msa_clti_s_h((v8i16)in, 0); \ ILVRL_H2_SW(tmp_m, in, out0, out1); \ - } while (0) + } /* Description : Butterfly of 4 input vectors Arguments : Inputs - in0, in1, in2, in3 @@ -1533,13 +1533,13 @@ Details : Butterfly operation */ #define BUTTERFLY_4(in0, in1, in2, in3, out0, out1, out2, out3) \ - do { \ + { \ out0 = in0 + in3; \ out1 = in1 + in2; \ \ out2 = in1 - in2; \ out3 = in0 - in3; \ - } while (0) + } /* Description : Transpose input 8x8 byte block Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7 @@ -1548,7 +1548,7 @@ */ #define TRANSPOSE8x8_UB(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, out0, \ out1, out2, out3, out4, out5, out6, out7) \ - do { \ + { \ v16i8 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \ v16i8 tmp4_m, tmp5_m, tmp6_m, tmp7_m; \ \ @@ -1560,7 +1560,7 @@ ILVRL_W2(RTYPE, tmp7_m, tmp5_m, out4, out6); \ SLDI_B2_0(RTYPE, out0, out2, out1, out3, 8); \ SLDI_B2_0(RTYPE, out4, out6, out5, out7, 8); \ - } while (0) + } #define TRANSPOSE8x8_UB_UB(...) TRANSPOSE8x8_UB(v16u8, __VA_ARGS__) /* Description : Transpose 16x4 block into 4x16 with byte elements in vectors @@ -1572,7 +1572,7 @@ #define TRANSPOSE16x4_UB_UB(in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, \ in10, in11, in12, in13, in14, in15, out0, out1, \ out2, out3) \ - do { \ + { \ v2i64 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \ \ ILVEV_W2_SD(in0, in4, in8, in12, tmp0_m, tmp1_m); \ @@ -1595,7 +1595,7 @@ tmp1_m = (v2i64)__msa_ilvod_b((v16i8)tmp3_m, (v16i8)tmp2_m); \ out1 = (v16u8)__msa_ilvev_h((v8i16)tmp1_m, (v8i16)tmp0_m); \ out3 = (v16u8)__msa_ilvod_h((v8i16)tmp1_m, (v8i16)tmp0_m); \ - } while (0) + } /* Description : Transpose 16x8 block into 8x16 with byte elements in vectors Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7, @@ -1606,7 +1606,7 @@ #define TRANSPOSE16x8_UB_UB(in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, \ in10, in11, in12, in13, in14, in15, out0, out1, \ out2, out3, out4, out5, out6, out7) \ - do { \ + { \ v16u8 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \ v16u8 tmp4_m, tmp5_m, tmp6_m, tmp7_m; \ \ @@ -1643,7 +1643,7 @@ tmp3_m = (v16u8)__msa_ilvod_h((v8i16)tmp7_m, (v8i16)tmp6_m); \ out3 = (v16u8)__msa_ilvev_w((v4i32)tmp3_m, (v4i32)tmp2_m); \ out7 = (v16u8)__msa_ilvod_w((v4i32)tmp3_m, (v4i32)tmp2_m); \ - } while (0) + } /* Description : Transpose 4x4 block with half word elements in vectors Arguments : Inputs - in0, in1, in2, in3 @@ -1651,14 +1651,14 @@ Return Type - signed halfword */ #define TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, out0, out1, out2, out3) \ - do { \ + { \ v8i16 s0_m, s1_m; \ \ ILVR_H2_SH(in1, in0, in3, in2, s0_m, s1_m); \ ILVRL_W2_SH(s1_m, s0_m, out0, out2); \ out1 = (v8i16)__msa_ilvl_d((v2i64)out0, (v2i64)out0); \ out3 = (v8i16)__msa_ilvl_d((v2i64)out0, (v2i64)out2); \ - } while (0) + } /* Description : Transpose 8x4 block with half word elements in vectors Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7 @@ -1666,14 +1666,14 @@ Return Type - signed halfword */ #define TRANSPOSE8X4_SH_SH(in0, in1, in2, in3, out0, out1, out2, out3) \ - do { \ + { \ v8i16 tmp0_m, tmp1_m, tmp2_m, tmp3_m; \ \ ILVR_H2_SH(in1, in0, in3, in2, tmp0_m, tmp1_m); \ ILVL_H2_SH(in1, in0, in3, in2, tmp2_m, tmp3_m); \ ILVR_W2_SH(tmp1_m, tmp0_m, tmp3_m, tmp2_m, out0, out2); \ ILVL_W2_SH(tmp1_m, tmp0_m, tmp3_m, tmp2_m, out1, out3); \ - } while (0) + } /* Description : Transpose 4x4 block with word elements in vectors Arguments : Inputs - in0, in1, in2, in3 @@ -1681,7 +1681,7 @@ Return Type - signed word */ #define TRANSPOSE4x4_SW_SW(in0, in1, in2, in3, out0, out1, out2, out3) \ - do { \ + { \ v4i32 s0_m, s1_m, s2_m, s3_m; \ \ ILVRL_W2_SW(in1, in0, s0_m, s1_m); \ @@ -1691,7 +1691,7 @@ out1 = (v4i32)__msa_ilvl_d((v2i64)s2_m, (v2i64)s0_m); \ out2 = (v4i32)__msa_ilvr_d((v2i64)s3_m, (v2i64)s1_m); \ out3 = (v4i32)__msa_ilvl_d((v2i64)s3_m, (v2i64)s1_m); \ - } while (0) + } /* Description : Dot product and addition of 3 signed halfword input vectors Arguments : Inputs - in0, in1, in2, coeff0, coeff1, coeff2 @@ -1737,11 +1737,11 @@ Arguments : Inputs - in0, in1, pdst */ #define PCKEV_ST_SB(in0, in1, pdst) \ - do { \ + { \ v16i8 tmp_m; \ tmp_m = __msa_pckev_b((v16i8)in1, (v16i8)in0); \ ST_SB(tmp_m, (pdst)); \ - } while (0) + } /* Description : Horizontal 2 tap filter kernel code Arguments : Inputs - in0, in1, mask, coeff, shift diff --git a/vp8/encoder/mcomp.c b/vp8/encoder/mcomp.c index fd9810e1e..999d6e851 100644 --- a/vp8/encoder/mcomp.c +++ b/vp8/encoder/mcomp.c @@ -800,24 +800,24 @@ int vp8_find_best_half_pixel_step(MACROBLOCK *x, BLOCK *b, BLOCKD *d, } #define CHECK_BOUNDS(range) \ - do { \ + { \ all_in = 1; \ all_in &= ((br - range) >= x->mv_row_min); \ all_in &= ((br + range) <= x->mv_row_max); \ all_in &= ((bc - range) >= x->mv_col_min); \ all_in &= ((bc + range) <= x->mv_col_max); \ - } while (0) + } #define CHECK_POINT \ - do { \ + { \ if (this_mv.as_mv.col < x->mv_col_min) continue; \ if (this_mv.as_mv.col > x->mv_col_max) continue; \ if (this_mv.as_mv.row < x->mv_row_min) continue; \ if (this_mv.as_mv.row > x->mv_row_max) continue; \ - } while (0) + } #define CHECK_BETTER \ - do { \ + { \ if (thissad < bestsad) { \ thissad += \ mvsad_err_cost(&this_mv, &fcenter_mv, mvsadcost, sad_per_bit); \ @@ -826,7 +826,7 @@ int vp8_find_best_half_pixel_step(MACROBLOCK *x, BLOCK *b, BLOCKD *d, best_site = i; \ } \ } \ - } while (0) + } static const MV next_chkpts[6][3] = { { { -2, 0 }, { -1, -2 }, { 1, -2 } }, { { -1, -2 }, { 1, -2 }, { 2, 0 } }, @@ -903,7 +903,7 @@ int vp8_hex_search(MACROBLOCK *x, BLOCK *b, BLOCKD *d, int_mv *ref_mv, #endif /* hex search */ - CHECK_BOUNDS(2); + CHECK_BOUNDS(2) if (all_in) { for (i = 0; i < 6; ++i) { @@ -912,17 +912,17 @@ int vp8_hex_search(MACROBLOCK *x, BLOCK *b, BLOCKD *d, int_mv *ref_mv, this_offset = base_offset + (this_mv.as_mv.row * in_what_stride) + this_mv.as_mv.col; thissad = vfp->sdf(what, what_stride, this_offset, in_what_stride); - CHECK_BETTER; + CHECK_BETTER } } else { for (i = 0; i < 6; ++i) { this_mv.as_mv.row = br + hex[i].row; this_mv.as_mv.col = bc + hex[i].col; - CHECK_POINT; + CHECK_POINT this_offset = base_offset + (this_mv.as_mv.row * in_what_stride) + this_mv.as_mv.col; thissad = vfp->sdf(what, what_stride, this_offset, in_what_stride); - CHECK_BETTER; + CHECK_BETTER } } @@ -936,7 +936,7 @@ int vp8_hex_search(MACROBLOCK *x, BLOCK *b, BLOCKD *d, int_mv *ref_mv, for (j = 1; j < hex_range; ++j) { best_site = -1; - CHECK_BOUNDS(2); + CHECK_BOUNDS(2) if (all_in) { for (i = 0; i < 3; ++i) { @@ -945,17 +945,17 @@ int vp8_hex_search(MACROBLOCK *x, BLOCK *b, BLOCKD *d, int_mv *ref_mv, this_offset = base_offset + (this_mv.as_mv.row * (in_what_stride)) + this_mv.as_mv.col; thissad = vfp->sdf(what, what_stride, this_offset, in_what_stride); - CHECK_BETTER; + CHECK_BETTER } } else { for (i = 0; i < 3; ++i) { this_mv.as_mv.row = br + next_chkpts[k][i].row; this_mv.as_mv.col = bc + next_chkpts[k][i].col; - CHECK_POINT; + CHECK_POINT this_offset = base_offset + (this_mv.as_mv.row * (in_what_stride)) + this_mv.as_mv.col; thissad = vfp->sdf(what, what_stride, this_offset, in_what_stride); - CHECK_BETTER; + CHECK_BETTER } } @@ -977,7 +977,7 @@ int vp8_hex_search(MACROBLOCK *x, BLOCK *b, BLOCKD *d, int_mv *ref_mv, cal_neighbors: for (j = 0; j < dia_range; ++j) { best_site = -1; - CHECK_BOUNDS(1); + CHECK_BOUNDS(1) if (all_in) { for (i = 0; i < 4; ++i) { @@ -986,17 +986,17 @@ cal_neighbors: this_offset = base_offset + (this_mv.as_mv.row * (in_what_stride)) + this_mv.as_mv.col; thissad = vfp->sdf(what, what_stride, this_offset, in_what_stride); - CHECK_BETTER; + CHECK_BETTER } } else { for (i = 0; i < 4; ++i) { this_mv.as_mv.row = br + neighbors[i].row; this_mv.as_mv.col = bc + neighbors[i].col; - CHECK_POINT; + CHECK_POINT this_offset = base_offset + (this_mv.as_mv.row * (in_what_stride)) + this_mv.as_mv.col; thissad = vfp->sdf(what, what_stride, this_offset, in_what_stride); - CHECK_BETTER; + CHECK_BETTER } } diff --git a/vp8/encoder/mips/msa/dct_msa.c b/vp8/encoder/mips/msa/dct_msa.c index fe281d2d0..308466755 100644 --- a/vp8/encoder/mips/msa/dct_msa.c +++ b/vp8/encoder/mips/msa/dct_msa.c @@ -12,7 +12,7 @@ #include "vp8/common/mips/msa/vp8_macros_msa.h" #define TRANSPOSE4x4_H(in0, in1, in2, in3, out0, out1, out2, out3) \ - do { \ + { \ v8i16 s0_m, s1_m, tp0_m, tp1_m, tp2_m, tp3_m; \ \ ILVR_H2_SH(in2, in0, in3, in1, s0_m, s1_m); \ @@ -21,15 +21,15 @@ ILVRL_H2_SH(s1_m, s0_m, tp2_m, tp3_m); \ PCKEV_D2_SH(tp2_m, tp0_m, tp3_m, tp1_m, out0, out2); \ PCKOD_D2_SH(tp2_m, tp0_m, tp3_m, tp1_m, out1, out3); \ - } while (0) + } #define SET_DOTP_VALUES(coeff, val0, val1, val2, const1, const2) \ - do { \ + { \ v8i16 tmp0_m; \ \ SPLATI_H3_SH(coeff, val0, val1, val2, tmp0_m, const1, const2); \ ILVEV_H2_SH(tmp0_m, const1, const2, tmp0_m, const1, const2); \ - } while (0) + } #define RET_1_IF_NZERO_H(in0) \ ({ \ diff --git a/vp8/encoder/mips/msa/temporal_filter_msa.c b/vp8/encoder/mips/msa/temporal_filter_msa.c index cc6bab5d5..fb83f07bd 100644 --- a/vp8/encoder/mips/msa/temporal_filter_msa.c +++ b/vp8/encoder/mips/msa/temporal_filter_msa.c @@ -62,7 +62,7 @@ static void temporal_filter_apply_16size_msa( mod3_w = diff1_l & mod3_w; MUL4(mod0_w, filter_wt, mod1_w, filter_wt, mod2_w, filter_wt, mod3_w, filter_wt, mod0_w, mod1_w, mod2_w, mod3_w); - PCKEV_H2_SH(mod1_w, mod0_w, mod3_w, mod2_w, mod0_h, mod1_h); + PCKEV_H2_SH(mod1_w, mod0_w, mod3_w, mod2_w, mod0_h, mod1_h) ADD2(mod0_h, cnt0, mod1_h, cnt1, mod0_h, mod1_h); ST_SH2(mod0_h, mod1_h, cnt, 8); cnt += 16; |