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author | Jerome Jiang <jianj@google.com> | 2018-08-13 11:01:31 -0700 |
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committer | Jerome Jiang <jianj@google.com> | 2018-08-14 10:55:31 -0700 |
commit | b4e783da577bc3631a48e071b67931b7833ec651 (patch) | |
tree | d9578867d140b3ed4ed66d4e60a6423b476a3493 /vp9/encoder/vp9_multi_thread.c | |
parent | f1d44c1f45bb0828ef4a683ad42544b3c6fc3af1 (diff) | |
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vp9: fix memory alloc for adaptive_rd_thresh_row_mt.
When the feature is enabled and the memory is not available, allocate
it. There was a case where speed feature changed in the middle of stream
but the number of tiles stayed the same, memory was not re-allocated.
Another case is where speed for base layer is different than that of
higher quality layers (same resolution). Removed the speed constraints
forcing base layer using same speed setting.
Thus the memory for adaptive_rd_thresh_row_mt stayed NULL but the
feature was enabled.
Add an end to end test to cover this case.
Change-Id: I2f1f802ef98a554571b30094d3600b9439228457
Diffstat (limited to 'vp9/encoder/vp9_multi_thread.c')
-rw-r--r-- | vp9/encoder/vp9_multi_thread.c | 27 |
1 files changed, 19 insertions, 8 deletions
diff --git a/vp9/encoder/vp9_multi_thread.c b/vp9/encoder/vp9_multi_thread.c index 381edca99..c8a80563a 100644 --- a/vp9/encoder/vp9_multi_thread.c +++ b/vp9/encoder/vp9_multi_thread.c @@ -50,6 +50,20 @@ void *vp9_enc_grp_get_next_job(MultiThreadHandle *multi_thread_ctxt, return job_info; } +void vp9_row_mt_alloc_rd_thresh(VP9_COMP *const cpi, + TileDataEnc *const this_tile) { + VP9_COMMON *const cm = &cpi->common; + const int sb_rows = + (mi_cols_aligned_to_sb(cm->mi_rows) >> MI_BLOCK_SIZE_LOG2) + 1; + int i; + + this_tile->row_base_thresh_freq_fact = + (int *)vpx_calloc(sb_rows * BLOCK_SIZES * MAX_MODES, + sizeof(*(this_tile->row_base_thresh_freq_fact))); + for (i = 0; i < sb_rows * BLOCK_SIZES * MAX_MODES; i++) + this_tile->row_base_thresh_freq_fact[i] = RD_THRESH_INIT_FACT; +} + void vp9_row_mt_mem_alloc(VP9_COMP *cpi) { struct VP9Common *cm = &cpi->common; MultiThreadHandle *multi_thread_ctxt = &cpi->multi_thread_ctxt; @@ -83,14 +97,11 @@ void vp9_row_mt_mem_alloc(VP9_COMP *cpi) { TileDataEnc *this_tile = &cpi->tile_data[tile_col]; vp9_row_mt_sync_mem_alloc(&this_tile->row_mt_sync, cm, jobs_per_tile_col); if (cpi->sf.adaptive_rd_thresh_row_mt) { - const int sb_rows = - (mi_cols_aligned_to_sb(cm->mi_rows) >> MI_BLOCK_SIZE_LOG2) + 1; - int i; - this_tile->row_base_thresh_freq_fact = - (int *)vpx_calloc(sb_rows * BLOCK_SIZES * MAX_MODES, - sizeof(*(this_tile->row_base_thresh_freq_fact))); - for (i = 0; i < sb_rows * BLOCK_SIZES * MAX_MODES; i++) - this_tile->row_base_thresh_freq_fact[i] = RD_THRESH_INIT_FACT; + if (this_tile->row_base_thresh_freq_fact != NULL) { + vpx_free(this_tile->row_base_thresh_freq_fact); + this_tile->row_base_thresh_freq_fact = NULL; + } + vp9_row_mt_alloc_rd_thresh(cpi, this_tile); } } |