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| author | hkuang <hkuang@google.com> | 2013-08-16 10:54:56 -0700 |
|---|---|---|
| committer | hkuang <hkuang@google.com> | 2013-08-16 10:54:56 -0700 |
| commit | df0715204cccc9d9652bf43eb6fc164cca6a0fe4 (patch) | |
| tree | b5f77519cbe1e9336286aa38f45cff3b6fadfdb7 /vp9/common/arm/neon | |
| parent | bba68342ce173d6db654da900f21c6e708dbc4c6 (diff) | |
| download | libvpx-df0715204cccc9d9652bf43eb6fc164cca6a0fe4.tar libvpx-df0715204cccc9d9652bf43eb6fc164cca6a0fe4.tar.gz libvpx-df0715204cccc9d9652bf43eb6fc164cca6a0fe4.tar.bz2 libvpx-df0715204cccc9d9652bf43eb6fc164cca6a0fe4.zip | |
Reduce instructions of idct4x4.
Change-Id: Ia26a2526804e7e2f656b0051618a615fca8fc79d
Diffstat (limited to 'vp9/common/arm/neon')
| -rw-r--r-- | vp9/common/arm/neon/vp9_short_idct4x4_add_neon.asm | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/vp9/common/arm/neon/vp9_short_idct4x4_add_neon.asm b/vp9/common/arm/neon/vp9_short_idct4x4_add_neon.asm index 433032237..adc17fc97 100644 --- a/vp9/common/arm/neon/vp9_short_idct4x4_add_neon.asm +++ b/vp9/common/arm/neon/vp9_short_idct4x4_add_neon.asm @@ -81,17 +81,15 @@ ; input[1] * cospi_24_64 - input[3] * cospi_8_64; ; input[1] * cospi_8_64 + input[3] * cospi_24_64; vmull.s16 q15, d17, d22 - vmull.s16 q0, d19, d20 vmull.s16 q1, d17, d20 - vmull.s16 q2, d19, d22 - vsub.s32 q3, q15, q0 - vadd.s32 q8, q1, q2 + vmlsl.s16 q15, d19, d20 + vmlal.s16 q1, d19, d22 ; dct_const_round_shift vqrshrn.s32 d26, q13, #14 vqrshrn.s32 d27, q14, #14 - vqrshrn.s32 d29, q3, #14 - vqrshrn.s32 d28, q8, #14 + vqrshrn.s32 d29, q15, #14 + vqrshrn.s32 d28, q1, #14 ; stage 2 ; output[0] = step[0] + step[3]; @@ -132,17 +130,15 @@ ; input[1] * cospi_24_64 - input[3] * cospi_8_64; ; input[1] * cospi_8_64 + input[3] * cospi_24_64; vmull.s16 q15, d17, d22 - vmull.s16 q0, d19, d20 vmull.s16 q1, d17, d20 - vmull.s16 q2, d19, d22 - vsub.s32 q3, q15, q0 - vadd.s32 q8, q1, q2 + vmlsl.s16 q15, d19, d20 + vmlal.s16 q1, d19, d22 ; dct_const_round_shift vqrshrn.s32 d26, q13, #14 vqrshrn.s32 d27, q14, #14 - vqrshrn.s32 d29, q3, #14 - vqrshrn.s32 d28, q8, #14 + vqrshrn.s32 d29, q15, #14 + vqrshrn.s32 d28, q1, #14 ; stage 2 ; output[0] = step[0] + step[3]; |