// // Generated by Microsoft (R) HLSL Shader Compiler 9.25.950.2675 // // using 3Dmigoto v1.3.16 on Wed Feb 09 18:55:48 2022 // // // Resource Bindings: // // Name Type Format Dim Slot Elements // ------------------------------ ---------- ------- ----------- ---- -------- // SuperSampleTextureFromInterpolatorUV1_Sampler sampler NA NA 0 1 // SampleTextureFromInterpolatorUV2_Sampler sampler NA NA 1 1 // SuperSampleTextureFromInterpolatorUV1_Sampler texture float4 2d 0 1 // SampleTextureFromInterpolatorUV2_Sampler texture float4 2d 1 1 // // // // Input signature: // // Name Index Mask Register SysValue Format Used // -------------------- ----- ------ -------- -------- ------- ------ // SV_POSITION 0 xyzw 0 POS float // TEXCOORD 0 xyzw 1 NONE float // TEXCOORD 1 xyzw 2 NONE float xyzw // TEXCOORD 2 xyzw 3 NONE float xyzw // TEXCOORD 3 xy 4 NONE float xy // TEXCOORD 4 xyzw 5 NONE float w // // // Output signature: // // Name Index Mask Register SysValue Format Used // -------------------- ----- ------ -------- -------- ------- ------ // SV_Target 0 xyzw 0 TARGET float xyzw // // // Sampler/Resource to DX9 shader sampler mappings: // // Target Sampler Source Sampler Source Resource // -------------- --------------- ---------------- // s0 s0 t0 // s1 s1 t1 // // // Level9 shader bytecode: // ps_2_0 def c0, 0.25, 1, 0, 0 dcl t1 dcl t2 dcl t3.xy dcl t4 dcl_2d s0 dcl_2d s1 mov r0.x, t1.z mov r0.y, t1.w mov r1.x, t2.z mov r1.y, t2.w texld r0, r0, s0 texld r2, t1, s0 texld r3, t2, s0 texld r1, r1, s0 texld r4, t3, s1 add r0.xyz, r0, r2 add r0.xyz, r3, r0 add r0.xyz, r1, r0 mul r0.xyz, r0, c0.x mov r0.w, c0.y mul r0, r4.w, r0 mul r0.w, r0.w, t4.w mov oC0, r0 // approximately 17 instruction slots used (5 texture, 12 arithmetic) ps_4_0 dcl_sampler s0, mode_default dcl_sampler s1, mode_default dcl_resource_texture2d (float,float,float,float) t0 dcl_resource_texture2d (float,float,float,float) t1 dcl_input_ps linear v2.xyzw dcl_input_ps linear v3.xyzw dcl_input_ps linear v4.xy dcl_input_ps linear v5.w dcl_output o0.xyzw dcl_temps 2 sample r0.xyzw, v2.xyxx, t0.xyzw, s0 sample r1.xyzw, v2.zwzz, t0.xyzw, s0 add r0.xyz, r0.xyzx, r1.xyzx sample r1.xyzw, v3.xyxx, t0.xyzw, s0 add r0.xyz, r0.xyzx, r1.xyzx sample r1.xyzw, v3.zwzz, t0.xyzw, s0 add r0.xyz, r0.xyzx, r1.xyzx mul r0.xyz, r0.xyzx, l(0.250000, 0.250000, 0.250000, 0.000000) sample r1.xyzw, v4.xyxx, t1.xyzw, s1 mov r0.w, l(1.000000) mul r0.xyzw, r0.xyzw, r1.wwww mul o0.w, r0.w, v5.w mov o0.xyz, r0.xyzx ret // Approximately 14 instruction slots used