//
// Generated by Microsoft (R) HLSL Shader Compiler 9.25.950.2675
//
//   using 3Dmigoto v1.3.16 on Wed Feb 09 18:55:49 2022
//
//
// Buffer Definitions:
//
// cbuffer cbVSUpdateEveryCall
// {
//
//   struct
//   {
//
//       struct
//       {
//
//           float4x4 mat4x4WorldToProjection;// Offset:    0
//
//       } Transform_World2D_By_Matrix4x4_VS0_ConstantTable;// Offset:    0
//
//       struct
//       {
//
//           float4 ddxyEstimated;      // Offset:   64
//
//       } ExpandUVToSuperSampleUVInterpolator_VS1_ConstantTable;// Offset:   64
//
//   } Data_VS;                         // Offset:    0 Size:    80
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// cbVSUpdateEveryCall               cbuffer      NA          NA    0        1
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// POSITION                 0   xyz         0     NONE   float   xyz
// TEXCOORD                 0   xyzw        1     NONE   float   xyzw
// TEXCOORD                 1   xy          2     NONE   float   xy
// TEXCOORD                 2   xy          3     NONE   float
//
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_POSITION              0   xyzw        0      POS   float   xyzw
// TEXCOORD                 0   xyzw        1     NONE   float   xyzw
// TEXCOORD                 1   xyzw        2     NONE   float   xyzw
// TEXCOORD                 2   xyzw        3     NONE   float   xyzw
// TEXCOORD                 3   xyzw        4     NONE   float   xyzw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer  Start Reg # of Regs        Data Conversion
// ---------- ------- --------- --------- ----------------------
// c1         cb0             0         5  ( FLT, FLT, FLT, FLT)
//
//
// Runtime generated constant mappings:
//
// Target Reg                               Constant Description
// ---------- --------------------------------------------------
// c0                              Vertex Shader position offset
//
//
// Level9 shader bytecode:
//
    vs_2_0
    def c6, 1, 0, 3, 0.375
    def c7, 0, 0.125, 0, 0
    dcl_texcoord v0
    dcl_texcoord1 v1
    dcl_texcoord2 v2
    mad r0, v0.xyzx, c6.xxxy, c6.yyyx
    dp4 oPos.z, r0, c3
    mov r1.xyz, c6
    mul r2.xy, r1, c5.x
    mad r2.zw, r2.xyxy, c6.xywz, v2.xyxy
    mad r2.xy, r2, -c6.wzzw, v2
    mov r3.xy, c5
    mad oT2.xy, r3, c7, r2
    mad oT1.xy, r3, -c7, r2.zwzw
    mad r2.xy, r3.x, -c7.yxzw, v2
    mad r1.xy, c5.y, r1.yxzw, r1.zyzw
    mad oT1.zw, c6.xyyw, -r1.xyxy, r2.xyxy
    mad r1.zw, r3.x, c7.xyyx, v2.xyxy
    mad oT2.zw, c6.xyyw, r1.xyxy, r1
    dp4 r1.x, r0, c1
    dp4 r1.y, r0, c2
    dp4 r0.x, r0, c4
    mad oPos.xy, r0.x, c0, r1
    mov oPos.w, r0.x
    mov oT0, c6.x
    mov oT3, v1

// approximately 21 instruction slots used
vs_4_0
dcl_constantbuffer cb0[5], immediateIndexed
dcl_input v0.xyz
dcl_input v1.xyzw
dcl_input v2.xy
dcl_output_siv o0.xyzw, position
dcl_output o1.xyzw
dcl_output o2.xyzw
dcl_output o3.xyzw
dcl_output o4.xyzw
dcl_temps 2
mov r0.xyz, v0.xyzx
mov r0.w, l(1.000000)
dp4 o0.x, r0.xyzw, cb0[0].xyzw
dp4 o0.y, r0.xyzw, cb0[1].xyzw
dp4 o0.z, r0.xyzw, cb0[2].xyzw
dp4 o0.w, r0.xyzw, cb0[3].xyzw
mov o1.xyzw, l(1.000000,1.000000,1.000000,1.000000)
mul r0.z, cb0[4].x, l(0.125000)
mov r0.w, l(0)
add r0.xy, -r0.zwzz, v2.xyxx
add r0.zw, r0.zzzw, v2.xxxy
mov r1.z, l(3.000000)
mov r1.w, cb0[4].y
mad o2.zw, l(-0.000000, -0.000000, -0.000000, -0.375000), r1.zzzw, r0.xxxy
mad o3.zw, l(0.000000, 0.000000, 0.000000, 0.375000), r1.zzzw, r0.zzzw
mul r0.w, cb0[4].y, l(0.125000)
mov r0.x, cb0[4].x
mov r0.yz, l(0,0,0,0)
mad r1.xy, r0.xyxx, l(0.375000, 3.000000, 0.000000, 0.000000), v2.xyxx
mad r0.xy, -r0.xyxx, l(0.375000, 3.000000, 0.000000, 0.000000), v2.xyxx
add o3.xy, r0.zwzz, r0.xyxx
add o2.xy, -r0.zwzz, r1.xyxx
mov o4.xyzw, v1.xyzw
ret
// Approximately 24 instruction slots used