From f9d35bb91eea55bddcb604ec369ddab847d7ed5a Mon Sep 17 00:00:00 2001 From: Roland McGrath Date: Tue, 4 Apr 2006 08:18:56 +0000 Subject: [BZ #2505] 2006-04-03 Steven Munroe [BZ #2505] * sysdeps/powerpc/powerpc32/bits/atomic.h [_ARCH_PWR4]: Define atomic_read_barrier and __ARCH_REL_INSTR using lwsync. --- sysdeps/powerpc/powerpc32/bits/atomic.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'sysdeps/powerpc') diff --git a/sysdeps/powerpc/powerpc32/bits/atomic.h b/sysdeps/powerpc/powerpc32/bits/atomic.h index 0f1a72335f..6fcc669fb1 100644 --- a/sysdeps/powerpc/powerpc32/bits/atomic.h +++ b/sysdeps/powerpc/powerpc32/bits/atomic.h @@ -89,12 +89,27 @@ # define __arch_atomic_decrement_if_positive_64(mem) \ ({ abort (); (*mem)--; }) +#ifdef _ARCH_PWR4 +/* + * Newer powerpc64 processors support the new "light weight" sync (lwsync) + * So if the build is using -mcpu=[power4,power5,power5+,970] we can + * safely use lwsync. + */ +# define atomic_read_barrier() __asm ("lwsync" ::: "memory") +/* + * "light weight" sync can also be used for the release barrier. + */ +# ifndef UP +# define __ARCH_REL_INSTR "lwsync" +# endif +#else /* * Older powerpc32 processors don't support the new "light weight" * sync (lwsync). So the only safe option is to use normal sync * for all powerpc32 applications. */ # define atomic_read_barrier() __asm ("sync" ::: "memory") +#endif /* * Include the rest of the atomic ops macros which are common to both -- cgit v1.2.3