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2015-08-20Move x86_64 init-arch.h to sysdeps/x86/init-arch.hH.J. Lu
Move sysdeps/x86_64/multiarch/init-arch.h to sysdeps/x86/init-arch.h which can be used for both i386 and x86_64. * sysdeps/i386/i686/multiarch/init-arch.h: Removed. * sysdeps/unix/sysv/linux/x86/init-arch.h: Likewise. * sysdeps/x86_64/cacheinfo.c: Include <init-arch.h> instead of "multiarch/init-arch.h". * sysdeps/x86_64/multiarch/init-arch.h: Renamed to ... * sysdeps/x86/init-arch.h: This.
2015-08-13Add _dl_x86_cpu_features to rtld_globalH.J. Lu
This patch adds _dl_x86_cpu_features to rtld_global in x86 ld.so and initializes it early before __libc_start_main is called so that cpu_features is always available when it is used and we can avoid calling __init_cpu_features in IFUNC selectors. * sysdeps/i386/dl-machine.h: Include <cpu-features.c>. (dl_platform_init): Call init_cpu_features. * sysdeps/i386/dl-procinfo.c (_dl_x86_cpu_features): New. * sysdeps/i386/i686/cacheinfo.c (DISABLE_PREFERRED_MEMORY_INSTRUCTION): Removed. * sysdeps/i386/i686/multiarch/Makefile (aux): Remove init-arch. * sysdeps/i386/i686/multiarch/Versions: Removed. * sysdeps/i386/i686/multiarch/ifunc-defines.sym (KIND_OFFSET): Removed. * sysdeps/i386/ldsodefs.h: Include <cpu-features.h>. * sysdeps/unix/sysv/linux/x86/Makefile (libpthread-sysdep_routines): Remove init-arch. * sysdeps/unix/sysv/linux/x86_64/dl-procinfo.c: Include <sysdeps/x86_64/dl-procinfo.c> instead of sysdeps/generic/dl-procinfo.c>. * sysdeps/x86/Makefile [$(subdir) == csu] (gen-as-const-headers): Add cpu-features-offsets.sym and rtld-global-offsets.sym. [$(subdir) == elf] (sysdep-dl-routines): Add dl-get-cpu-features. [$(subdir) == elf] (tests): Add tst-get-cpu-features. [$(subdir) == elf] (tests-static): Add tst-get-cpu-features-static. * sysdeps/x86/Versions: New file. * sysdeps/x86/cpu-features-offsets.sym: Likewise. * sysdeps/x86/cpu-features.c: Likewise. * sysdeps/x86/cpu-features.h: Likewise. * sysdeps/x86/dl-get-cpu-features.c: Likewise. * sysdeps/x86/libc-start.c: Likewise. * sysdeps/x86/rtld-global-offsets.sym: Likewise. * sysdeps/x86/tst-get-cpu-features-static.c: Likewise. * sysdeps/x86/tst-get-cpu-features.c: Likewise. * sysdeps/x86_64/dl-procinfo.c: Likewise. * sysdeps/x86_64/cacheinfo.c (__cpuid_count): Removed. Assume USE_MULTIARCH is defined and don't check it. (is_intel): Replace __cpu_features with GLRO(dl_x86_cpu_features). (is_amd): Likewise. (max_cpuid): Likewise. (intel_check_word): Likewise. (__cache_sysconf): Don't call __init_cpu_features. (__x86_preferred_memory_instruction): Removed. (init_cacheinfo): Don't call __init_cpu_features. Replace __cpu_features with GLRO(dl_x86_cpu_features). * sysdeps/x86_64/dl-machine.h: <cpu-features.c>. (dl_platform_init): Call init_cpu_features. * sysdeps/x86_64/ldsodefs.h: Include <cpu-features.h>. * sysdeps/x86_64/multiarch/Makefile (aux): Remove init-arch. * sysdeps/x86_64/multiarch/Versions: Removed. * sysdeps/x86_64/multiarch/cacheinfo.c: Likewise. * sysdeps/x86_64/multiarch/init-arch.c: Likewise. * sysdeps/x86_64/multiarch/ifunc-defines.sym (KIND_OFFSET): Removed. * sysdeps/x86_64/multiarch/init-arch.h: Rewrite.
2015-03-31Limit threads sharing L2 cache to 2 for SLM/KNLH.J. Lu
Silvermont and Knights Landing have a modular system design with two cores sharing an L2 cache. If more than 2 cores are detected to shared L2 cache, it should be adjusted for Silvermont and Knights Landing. [BZ #18185] * sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Limit threads sharing L2 cache to 2 for Silvermont/Knights Landing.
2015-01-02Update copyright dates with scripts/update-copyrights.Joseph Myers
2014-08-12Replace cpuid asm statement with __cpuid_countH.J. Lu
The compiler doesn't know that the cpuid asm statement in intel_check_word will trash RBX. We are lucky that it doesn't cause any problems since RBX is also used by compiler for other purposes so that RBX is saved and restored. This patch replaces it with __cpuid_count. [BZ #17259] * sysdeps/x86_64/cacheinfo.c (intel_check_word): Replace cpuid asm statement with __cpuid_count.
2014-01-01Update copyright notices with scripts/update-copyrightsAllan McRae
2013-01-05Change __x86_64 prefix in cache size to __x86H.J. Lu
2013-01-02Update copyright notices with scripts/update-copyrights.Joseph Myers
2012-02-09Replace FSF snail mail address with URLs.Paul Eggert
2011-04-03Fix typo in cache information table for x86-{32,64}.Ulrich Drepper
2011-03-22Last change caused infinite loops because of missing loop increment.Ulrich Drepper
2011-03-20Implement x86 cpuid handling of leaf4 for cache information.Ulrich Drepper
2011-03-04Enable SSE2 memset for AMD'supcoming Orochi processor.Harsha Jagasia
This patch enables SSE2 memset for AMD's upcoming Orochi processor. This patch also fixes the following bug: For misaligned blocks larger than > 144 Bytes, memset branches into the integer code path depending on the value of misalignment even if the startup code chooses the SSE2 code path upfront, when multiarch is enabled.
2010-11-0532bit memset-sse2.S fails with uneven cache sizeUlrich Drepper
32bit memset-sse2.S assumes cache size is multiple of 128 bytes. If it isn't true, memset-sse2.S will fail. For example, a processor can have 24576 KB L3 cache and 20 cores. That is 2516582 byte per core. Half of it is 1258291, which isn't helpful for vector instructions. This patch rounds cache sizes to multiple of 256 bytes and adds "raw" cache sizes.
2010-01-12Optimize 32bit memset/memcpy with SSE2/SSSE3.H.J. Lu
2009-08-07Fix whitespaces in last checkin.Ulrich Drepper
2009-08-07Properly count number of logical processors on Intel CPUs.H.J. Lu
The meaning of the 25-14 bits in EAX returned from cpuid with EAX = 4 has been changed from "the maximum number of threads sharing the cache" to "the maximum number of addressable IDs for logical processors sharing the cache" if cpuid takes EAX = 11. We need to use results from both EAX = 4 and EAX = 11 to get the number of threads sharing the cache. The 25-14 bits in EAX on Core i7 is 15 although the number of logical processors is 8. Here is a white paper on this: http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/ This patch correctly counts number of logical processors on Intel CPUs with EAX = 11 support on cpuid. Tested on Dinnington, Core i7 and Nehalem EX/EP. It also fixed Pentium Ds workaround since EBX may not have the right value returned from cpuid with EAX = 1.
2009-07-31Support multiarch for i686.H.J. Lu
This patch adds multiarch support when configured for i686. I modified some x86-64 functions to support 32bit. I will contribute 32bit SSE string and memory functions later.
2009-07-23Avoid cpuid instructions in cache info discovery.Ulrich Drepper
When multiarch is enabled we have this information stored. Use it.
2009-07-23Add more cache descriptors for L3 caches on x86 and x86-64.Ulrich Drepper
The most recent AP 485 describes a few more cache descriptors for L3 caches with 24-way associativity.
2009-05-31Simplify CPUID value handling.Ulrich Drepper
SO far Intel and AMD use exactly the same bits meaning the same things in CPUID index 1. Simplify the code. Should an architecture come along which doesn't use the same semantics then it must use a different index value than COMMON_CPUID_INDEX_1.
2009-05-29Compact cache info data structure for x86/x86-64.Ulrich Drepper
This saves about 1.5kB in the DSO.
2009-05-10* version.h (VERSION): Bump to 2.10.1.cvs/fedora-glibc-20090510T1842cvs/masterUlrich Drepper
* nss/getXXbyYY_r.c: If NO_COMPAT_NEEDED is defined don't define any compatibility functions. * nss/getXXent_r.c: Likewise. * gshadow/getsgent_r.c: Define NO_COMPAT_NEEDED. * gshadow/getsgnam_r.c: Likewise. * gshadow/Version: Remove duplicate entries. * sysdeps/x86_64/cacheinfo.c (intel_02_cache_info): Add missing entries for recent processor. * sysdeps/unix/sysv/linux/i386/sysconf.c (intel_02_cache_info): Likewise.
2009-03-13* config.h.in (USE_MULTIARCH): Define.Ulrich Drepper
* configure.in: Handle --enable-multi-arch. * elf/dl-runtime.c (_dl_fixup): Handle STT_GNU_IFUNC. (_dl_fixup_profile): Likewise. * elf/do-lookup.c (dl_lookup_x): Likewise. * sysdeps/x86_64/dl-machine.h: Handle STT_GNU_IFUNC. * elf/elf.h (STT_GNU_IFUNC): Define. * include/libc-symbols.h (libc_ifunc): Define. * sysdeps/x86_64/cacheinfo.c: If USE_MULTIARCH is defined, use the framework in init-arch.h to get CPUID values. * sysdeps/x86_64/multiarch/Makefile: New file. * sysdeps/x86_64/multiarch/init-arch.c: New file. * sysdeps/x86_64/multiarch/init-arch.h: New file. * sysdeps/x86_64/multiarch/sched_cpucount.c: New file. * config.make.in (experimental-malloc): Define. * configure.in: Handle --enable-experimental-malloc. * malloc/Makefile: Handle experimental-malloc flag. * malloc/malloc.c: Implement PER_THREAD and ATOMIC_FASTBINS features. * malloc/arena.c: Likewise. * malloc/hooks.c: Likewise. * malloc/malloc.h: Define M_ARENA_TEST and M_ARENA_MAX.
2009-02-01* sysdeps/x86_64/cacheinfo.c (intel_02_known): Add new descriptors.Ulrich Drepper
* sysdeps/unix/sysv/linux/i386/sysconf.c (intel_02_known): Likewise.
2008-03-07* sysdeps/x86_64/rtld-memset.c: New file.Ulrich Drepper
2008-2-26 Harsha Jagasia <harsha.jagasia@amd.com> * sysdeps/x86_64/cacheinfo.c (NOT_USED_RIGHT_NOW): Remove ifdef guards. * sysdeps/x86_64/memset.S: Rewrite non-SSE code path as tuned for AMD Barcelona machine. Make default fall through branch of __x86_64_preferred_memory_instruction check as the integer code path. 2007-10-15 H.J. Lu <hongjiu.lu@intel.com> * sysdeps/x86_64/cacheinfo.c (__x86_64_preferred_memory_instruction): New variable. (init_cacheinfo): Initialize __x86_64_preferred_memory_instruction. * sysdeps/x86_64/memset.S: Rewrite. 2008-01-08 Jakub Jelinek <jakub@redhat.com> * malloc/malloc.c (public_cALLOc): For arenas other than
2007-12-23(intel_02_known): New entry 0x3f.Ulrich Drepper
2007-10-17* sysdeps/x86_64/cacheinfo.c: Comment out code added in support ofUlrich Drepper
new memset. too high for the improvements. Implement bzero unconditionally for use in libc.
2007-10-16* sysdeps/x86_64/cacheinfo.c (__x86_64_shared_cache_size): Define.Ulrich Drepper
(init_cacheinfo): Initialize it. * sysdeps/x86_64/memset.S: Use __x86_64_shared_cache_size. Always define bzero. Remove non-glibc code. * sysdeps/x86_64/bzero.S: Make an empty file. 2007-10-15 H.J. Lu <hongjiu.lu@intel.com> * sysdeps/x86_64/cacheinfo.c (__x86_64_preferred_memory_instruction): New. (init_cacheinfo): Initialize __x86_64_preferred_memory_instruction. * sysdeps/x86_64/memset.S: Rewrite. * nss/getXXbyYY_r.c (REENTRANT_NAME): Mangle startp and start_fct
2007-10-10* sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Work around problemUlrich Drepper
with some Pentium Ds.
2007-09-22* sysdeps/x86_64/cacheinfo.c (__x86_64_data_cache_size_half): RenamedUlrich Drepper
from __x86_64_core_cache_size_half. (init_cacheinfo): Compute shared cache size for AMD processors with shared L3 correctly. * sysdeps/x86_64/memcpy.S: Adjust for __x86_64_data_cache_size_half name change. Patch in large parts by Evandro Menezes.
2007-08-25* sysdeps/x86_64/cacheinfo.c (handle_amd): Fix computation ofcvs/fedora-glibc-20070825T1839Ulrich Drepper
associativity for fully-associative caches.
2007-08-25* sysdeps/x86_64/cacheinfo.c (handle_amd): Handle L3 cacheUlrich Drepper
requests. Fill on more associativity values for L2. Patch mostly by Evandro Menezes.
2007-07-09* sysdeps/x86_64/cacheinfo.c (intel_02_known): Add new entries.Ulrich Drepper
* sysdeps/unix/sysv/linux/i386/sysconf.c (intel_02_known): Likewise.
2007-05-21* sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Pass correct valueUlrich Drepper
as second parameter to handle_intel.
2007-05-21* sysdeps/unix/sysv/linux/x86_64/sysconf.c: Move cache informationUlrich Drepper
handling to ... * sysdeps/x86_64/cacheinfo.c: ... here. New file. * sysdeps/x86_64/Makefile [subdir=string] (sysdep_routines): Add cacheinfo. * sysdeps/x86_64/memcpy.S: Complete rewrite. * sysdeps/x86_64/mempcpy.S: Adjust appropriately. Patch by Evandro Menezes <evandro.menezes@amd.com>. * sysdeps/unix/sysv/linux/i386/epoll_pwait.S: New file.
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