| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-05-27 | Count number of logical processors sharing L2 cache | H.J. Lu |
| 2016-05-20 | Remove special L2 cache case for Knights Landing | H.J. Lu |
| 2016-05-19 | Correct Intel processor level type mask from CPUID | H.J. Lu |
| 2016-05-19 | Check the HTT bit before counting logical threads | H.J. Lu |
| 2016-05-13 | Support non-inclusive caches on Intel processors | H.J. Lu |
| 2016-05-08 | Move sysdeps/x86_64/cacheinfo.c to sysdeps/x86 | H.J. Lu |
 |
index : glibc.git | |
| Mirror of https://sourceware.org/git/glibc.git |
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