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[BZ #15442] This adds support for the inverse interpretation of the
quiet bit of IEEE 754 floating-point NaN data that some processors
use. This includes in particular MIPS architecture processors; the
payload used for the canonical qNaN encoding is updated accordingly
so as not to interfere with the quiet bit.
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Joseph Myers noted that there were several old and really very
incorrect values in the hppa libm-test-ulps. This patch removes
all of the ulps values for ceil, floor, rint, round, trun,
llrint, and llround, all of which were previously incorreclty
added (including some negative values which are really wrong).
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ports/
2013-05-15 Carlos O'Donell <carlos@redhat.com>
* sysdeps/hppa/fpu/libm-test-ulps: Remove old values for ceil, floor,
rint, round, trunc, llrint, and llround.
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Update libm-test-ulps for hppa. There are a few entries
with 4 or 5 ulps, but these appear to be expected. A more
thorough review will be required if hppa switches long-double
to a different type.
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ports/
2013-05-15 Carlos O'Donell <carlos@redhat.com>
* sysdeps/hppa/fpu/libm-test-ulps: Regenerate.
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The following patch fixes both _FPU_GETCW and
_FPU_SETCW for hppa. The initial implementation was
flawed and not well tested. We failed to set cw,
and passed in the value of a register to fldd.
This patch fixes both of those errors and allows
the libm tests to pass without failure.
Signed-off-by: Guy Martin <gmsoft@tuxicoman.be>
Signed-off-by: Carlos O'Donell <carlos@redhat.com>
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2013-05-15 Guy Martin <gmsoft@tuxicoman.be>
Carlos O'Donell <carlos@redhat.com>
[BZ# 15000]
* ports/sysdeps/hppa/fpu/fpu_control.h (_FPU_GETCW): Set cw.
(_FPU_SETCW): Pass address to fldd.
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2013-05-12 Marcus Shawcroft <marcus.shawcroft@linaro.org>
* sysdeps/unix/sysv/linux/aarch64/clone.S (__clone):
Do not call sycall_error directly with a confitional branch.
* sysdeps/unix/sysv/linux/aarch64/ioctl.S (__ioctl):
Do not call sycall_error directly with a confitional branch.
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Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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It is based on draft TS 18661 and currently enabled as a GNU extension.
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ARM_NO_INDEX_REGISTER.
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Follow-up to commit 664a9ce4ca40feabff781fff044c93a43ae15b59.
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These macros often set up a variable that later macros sometimes do
not use. Add unused attribute to avoid that.
Similarly, the ia64 code tends to check the err field rather than
the val (which is opposite of most arches) leading to the same
kind of warning. Replace this with a dummy reference.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The current code declares double constants by using a char buffer and
then casting the pointer to a different type. This makes the aliasing
logic unhappy. Change it to use a union instead to avoid that.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Function pointers on ia64 are like parisc -- they're plabels. While
the parisc port enjoys a gcc builtin for extracting the address here,
ia64 has no such luck.
Casting & dereferencing in one go triggers a strict aliasing warning.
Use a union to fix that.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The ia64_rse_is_rnat_slot func expects an unsigned pointer, but we're
passing in a signed pointer. The signness doesn't matter here, so
convert it to unsigned.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The recent change to clean up these defines missed the ia64 logic.
Update it accordingly.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The strcpy and strchr (and related) functions are four times faster
than the byte-by-byte default versions.
The strlen function is twice as fast for long strings and 50% faster
for short strings over the armv4 version.
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* sysdeps/unix/sysv/linux/aarch64/bits/mman.h: Remove all
defines provided by bits/mman-linux.h and include <bits/mman-linux.h>.
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* sysdeps/unix/sysv/linux/bits/mman-linux.h (MAP_ANONYMOUS):
Allow definition via __MAP_ANONYMOUS.
* sysdeps/unix/sysv/linux/mips/bits/mman.h: Remove all defines
provided by bits/mman-linux.h and include <bits/mman-linux.h>.
(__MAP_ANONYMOUS): Define.
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Written from scratch rather than copied from GMP, due to LGPL 2.1 vs
GPL 3, but tested with the GMP testsuite.
This is 250% faster than the generic code as measured on Cortex-A15,
and the same speed as GMP on the same core, and probably everywhere.
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Written from scratch rather than copied from GMP, due to LGPL 2.1 vs
GPL 3, but tested with the GMP testsuite.
This is 50% faster than the generic code as measured on Cortex-A15.
It is 25% slower than the current GMP routine on the same core.
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Written from scratch rather than copied from GMP, due to LGPL 2.1 vs
GPL 3, but tested with the GMP testsuite.
This is 25% faster than the generic code as measured on Cortex-A15,
and the same speed as GMP on the same core. It's probably slower
than GMP on the A8 and A9 cores though.
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