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-rw-r--r--sysdeps/powerpc/bits/fenv.h92
-rw-r--r--sysdeps/s390/fpu/bits/fenv.h45
-rw-r--r--sysdeps/sh/sh4/fpu/bits/fenv.h35
-rw-r--r--sysdeps/sparc/fpu/bits/fenv.h45
-rw-r--r--sysdeps/x86/fpu/bits/fenv.h45
5 files changed, 157 insertions, 105 deletions
diff --git a/sysdeps/powerpc/bits/fenv.h b/sysdeps/powerpc/bits/fenv.h
index 1ee7e3bac1..845c68929f 100644
--- a/sysdeps/powerpc/bits/fenv.h
+++ b/sysdeps/powerpc/bits/fenv.h
@@ -1,4 +1,4 @@
-/* Copyright (C) 1997, 1998, 1999, 2008 Free Software Foundation, Inc.
+/* Copyright (C) 1997-2012 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -24,14 +24,18 @@
the appropriate bits in the FPSCR... */
enum
{
- FE_INEXACT = 1 << (31 - 6),
-#define FE_INEXACT FE_INEXACT
- FE_DIVBYZERO = 1 << (31 - 5),
-#define FE_DIVBYZERO FE_DIVBYZERO
- FE_UNDERFLOW = 1 << (31 - 4),
-#define FE_UNDERFLOW FE_UNDERFLOW
- FE_OVERFLOW = 1 << (31 - 3),
-#define FE_OVERFLOW FE_OVERFLOW
+ FE_INEXACT =
+#define FE_INEXACT (1 << (31 - 6))
+ FE_INEXACT,
+ FE_DIVBYZERO =
+#define FE_DIVBYZERO (1 << (31 - 5))
+ FE_DIVBYZERO,
+ FE_UNDERFLOW =
+#define FE_UNDERFLOW (1 << (31 - 4))
+ FE_UNDERFLOW,
+ FE_OVERFLOW =
+#define FE_OVERFLOW (1 << (31 - 3))
+ FE_OVERFLOW,
/* ... except for FE_INVALID, for which we use bit 31. FE_INVALID
actually corresponds to bits 7 through 12 and 21 through 23
@@ -39,8 +43,9 @@ enum
says that it must be a power of 2. Instead we use bit 2 which
is the summary bit for all the FE_INVALID exceptions, which
kind of makes sense. */
- FE_INVALID = 1 << (31 - 2),
-#define FE_INVALID FE_INVALID
+ FE_INVALID =
+#define FE_INVALID (1 << (31 - 2))
+ FE_INVALID,
#ifdef __USE_GNU
/* Breakdown of the FE_INVALID bits. Setting FE_INVALID on an
@@ -50,43 +55,52 @@ enum
enable these exceptions individually. */
/* Operation with SNaN. */
- FE_INVALID_SNAN = 1 << (31 - 7),
-# define FE_INVALID_SNAN FE_INVALID_SNAN
+ FE_INVALID_SNAN =
+# define FE_INVALID_SNAN (1 << (31 - 7))
+ FE_INVALID_SNAN,
/* Inf - Inf */
- FE_INVALID_ISI = 1 << (31 - 8),
-# define FE_INVALID_ISI FE_INVALID_ISI
+ FE_INVALID_ISI =
+# define FE_INVALID_ISI (1 << (31 - 8))
+ FE_INVALID_ISI,
/* Inf / Inf */
- FE_INVALID_IDI = 1 << (31 - 9),
-# define FE_INVALID_IDI FE_INVALID_IDI
+ FE_INVALID_IDI =
+# define FE_INVALID_IDI (1 << (31 - 9))
+ FE_INVALID_IDI,
/* 0 / 0 */
- FE_INVALID_ZDZ = 1 << (31 - 10),
-# define FE_INVALID_ZDZ FE_INVALID_ZDZ
+ FE_INVALID_ZDZ =
+# define FE_INVALID_ZDZ (1 << (31 - 10))
+ FE_INVALID_ZDZ,
/* Inf * 0 */
- FE_INVALID_IMZ = 1 << (31 - 11),
-# define FE_INVALID_IMZ FE_INVALID_IMZ
+ FE_INVALID_IMZ =
+# define FE_INVALID_IMZ (1 << (31 - 11))
+ FE_INVALID_IMZ,
/* Comparison with NaN or SNaN. */
- FE_INVALID_COMPARE = 1 << (31 - 12),
-# define FE_INVALID_COMPARE FE_INVALID_COMPARE
+ FE_INVALID_COMPARE =
+# define FE_INVALID_COMPARE (1 << (31 - 12))
+ FE_INVALID_COMPARE,
/* Invalid operation flag for software (not set by hardware). */
/* Note that some chips don't have this implemented, presumably
because no-one expected anyone to write software for them %-). */
- FE_INVALID_SOFTWARE = 1 << (31 - 21),
-# define FE_INVALID_SOFTWARE FE_INVALID_SOFTWARE
+ FE_INVALID_SOFTWARE =
+# define FE_INVALID_SOFTWARE (1 << (31 - 21))
+ FE_INVALID_SOFTWARE,
/* Square root of negative number (including -Inf). */
/* Note that some chips don't have this implemented. */
- FE_INVALID_SQRT = 1 << (31 - 22),
-# define FE_INVALID_SQRT FE_INVALID_SQRT
+ FE_INVALID_SQRT =
+# define FE_INVALID_SQRT (1 << (31 - 22))
+ FE_INVALID_SQRT,
/* Conversion-to-integer of a NaN or a number too large or too small. */
- FE_INVALID_INTEGER_CONVERSION = 1 << (31 - 23)
-# define FE_INVALID_INTEGER_CONVERSION FE_INVALID_INTEGER_CONVERSION
+ FE_INVALID_INTEGER_CONVERSION =
+# define FE_INVALID_INTEGER_CONVERSION (1 << (31 - 23))
+ FE_INVALID_INTEGER_CONVERSION
# define FE_ALL_INVALID \
(FE_INVALID_SNAN | FE_INVALID_ISI | FE_INVALID_IDI | FE_INVALID_ZDZ \
@@ -103,14 +117,18 @@ enum
appropriate macros. */
enum
{
- FE_TONEAREST = 0,
-#define FE_TONEAREST FE_TONEAREST
- FE_TOWARDZERO = 1,
-#define FE_TOWARDZERO FE_TOWARDZERO
- FE_UPWARD = 2,
-#define FE_UPWARD FE_UPWARD
- FE_DOWNWARD = 3
-#define FE_DOWNWARD FE_DOWNWARD
+ FE_TONEAREST =
+#define FE_TONEAREST 0
+ FE_TONEAREST,
+ FE_TOWARDZERO =
+#define FE_TOWARDZERO 1
+ FE_TOWARDZERO,
+ FE_UPWARD =
+#define FE_UPWARD 2
+ FE_UPWARD,
+ FE_DOWNWARD =
+#define FE_DOWNWARD 3
+ FE_DOWNWARD
};
/* Type representing exception flags. */
diff --git a/sysdeps/s390/fpu/bits/fenv.h b/sysdeps/s390/fpu/bits/fenv.h
index 6df7b177f9..f6cc351231 100644
--- a/sysdeps/s390/fpu/bits/fenv.h
+++ b/sysdeps/s390/fpu/bits/fenv.h
@@ -24,16 +24,21 @@
of the appropriate bits in the FPU control word. */
enum
{
- FE_INVALID = 0x80,
-#define FE_INVALID FE_INVALID
- FE_DIVBYZERO = 0x40,
-#define FE_DIVBYZERO FE_DIVBYZERO
- FE_OVERFLOW = 0x20,
-#define FE_OVERFLOW FE_OVERFLOW
- FE_UNDERFLOW = 0x10,
-#define FE_UNDERFLOW FE_UNDERFLOW
- FE_INEXACT = 0x08
-#define FE_INEXACT FE_INEXACT
+ FE_INVALID =
+#define FE_INVALID 0x80
+ FE_INVALID,
+ FE_DIVBYZERO =
+#define FE_DIVBYZERO 0x40
+ FE_DIVBYZERO,
+ FE_OVERFLOW =
+#define FE_OVERFLOW 0x20
+ FE_OVERFLOW,
+ FE_UNDERFLOW =
+#define FE_UNDERFLOW 0x10
+ FE_UNDERFLOW,
+ FE_INEXACT =
+#define FE_INEXACT 0x08
+ FE_INEXACT
};
/* We dont use the y bit of the DXC in the floating point control register
as glibc has no FE encoding for fe inexact incremented
@@ -48,14 +53,18 @@ enum
enum
{
- FE_TONEAREST = 0,
-#define FE_TONEAREST FE_TONEAREST
- FE_DOWNWARD = 0x3,
-#define FE_DOWNWARD FE_DOWNWARD
- FE_UPWARD = 0x2,
-#define FE_UPWARD FE_UPWARD
- FE_TOWARDZERO = 0x1
-#define FE_TOWARDZERO FE_TOWARDZERO
+ FE_TONEAREST =
+#define FE_TONEAREST 0
+ FE_TONEAREST,
+ FE_DOWNWARD =
+#define FE_DOWNWARD 0x3
+ FE_DOWNWARD,
+ FE_UPWARD =
+#define FE_UPWARD 0x2
+ FE_UPWARD,
+ FE_TOWARDZERO =
+#define FE_TOWARDZERO 0x1
+ FE_TOWARDZERO
};
diff --git a/sysdeps/sh/sh4/fpu/bits/fenv.h b/sysdeps/sh/sh4/fpu/bits/fenv.h
index 93159499d5..e51a057cb5 100644
--- a/sysdeps/sh/sh4/fpu/bits/fenv.h
+++ b/sysdeps/sh/sh4/fpu/bits/fenv.h
@@ -24,16 +24,21 @@
of the appropriate bits in the FPU control word. */
enum
{
- FE_INEXACT = 0x04,
-#define FE_INEXACT FE_INEXACT
- FE_UNDERFLOW = 0x08,
-#define FE_UNDERFLOW FE_UNDERFLOW
- FE_OVERFLOW = 0x10,
-#define FE_OVERFLOW FE_OVERFLOW
- FE_DIVBYZERO = 0x20,
-#define FE_DIVBYZERO FE_DIVBYZERO
- FE_INVALID = 0x40,
-#define FE_INVALID FE_INVALID
+ FE_INEXACT =
+#define FE_INEXACT 0x04
+ FE_INEXACT,
+ FE_UNDERFLOW =
+#define FE_UNDERFLOW 0x08
+ FE_UNDERFLOW,
+ FE_OVERFLOW =
+#define FE_OVERFLOW 0x10
+ FE_OVERFLOW,
+ FE_DIVBYZERO =
+#define FE_DIVBYZERO 0x20
+ FE_DIVBYZERO,
+ FE_INVALID =
+#define FE_INVALID 0x40
+ FE_INVALID,
};
#define FE_ALL_EXCEPT \
@@ -46,10 +51,12 @@ enum
{
__FE_UNDEFINED = -1,
- FE_TONEAREST = 0x0,
-#define FE_TONEAREST FE_TONEAREST
- FE_TOWARDZERO = 0x1,
-#define FE_TOWARDZERO FE_TOWARDZERO
+ FE_TONEAREST =
+#define FE_TONEAREST 0x0
+ FE_TONEAREST,
+ FE_TOWARDZERO =
+#define FE_TOWARDZERO 0x1
+ FE_TOWARDZERO,
};
diff --git a/sysdeps/sparc/fpu/bits/fenv.h b/sysdeps/sparc/fpu/bits/fenv.h
index 0e2a9b9e63..afe66ce5a0 100644
--- a/sysdeps/sparc/fpu/bits/fenv.h
+++ b/sysdeps/sparc/fpu/bits/fenv.h
@@ -26,16 +26,21 @@
of the appropriate accrued exception bits from the FSR. */
enum
{
- FE_INVALID = (1 << 9),
-#define FE_INVALID FE_INVALID
- FE_OVERFLOW = (1 << 8),
-#define FE_OVERFLOW FE_OVERFLOW
- FE_UNDERFLOW = (1 << 7),
-#define FE_UNDERFLOW FE_UNDERFLOW
- FE_DIVBYZERO = (1 << 6),
-#define FE_DIVBYZERO FE_DIVBYZERO
- FE_INEXACT = (1 << 5)
-#define FE_INEXACT FE_INEXACT
+ FE_INVALID =
+#define FE_INVALID (1 << 9)
+ FE_INVALID,
+ FE_OVERFLOW =
+#define FE_OVERFLOW (1 << 8)
+ FE_OVERFLOW,
+ FE_UNDERFLOW =
+#define FE_UNDERFLOW (1 << 7)
+ FE_UNDERFLOW,
+ FE_DIVBYZERO =
+#define FE_DIVBYZERO (1 << 6)
+ FE_DIVBYZERO,
+ FE_INEXACT =
+#define FE_INEXACT (1 << 5)
+ FE_INEXACT
};
#define FE_ALL_EXCEPT \
@@ -46,14 +51,18 @@ enum
for the appropriate macros. */
enum
{
- FE_TONEAREST = (0U << 30),
-#define FE_TONEAREST FE_TONEAREST
- FE_TOWARDZERO = (1U << 30),
-#define FE_TOWARDZERO FE_TOWARDZERO
- FE_UPWARD = (2U << 30),
-#define FE_UPWARD FE_UPWARD
- FE_DOWNWARD = (3U << 30)
-#define FE_DOWNWARD FE_DOWNWARD
+ FE_TONEAREST =
+#define FE_TONEAREST (0 << 30)
+ FE_TONEAREST,
+ FE_TOWARDZERO =
+#define FE_TOWARDZERO (1 << 30)
+ FE_TOWARDZERO,
+ FE_UPWARD =
+#define FE_UPWARD (-0x7fffffff - 1) /* (2 << 30) */
+ FE_UPWARD,
+ FE_DOWNWARD =
+#define FE_DOWNWARD (-0x40000000) /* (3 << 30) */
+ FE_DOWNWARD
};
#define __FE_ROUND_MASK (3U << 30)
diff --git a/sysdeps/x86/fpu/bits/fenv.h b/sysdeps/x86/fpu/bits/fenv.h
index b2c01c403f..e0079cd978 100644
--- a/sysdeps/x86/fpu/bits/fenv.h
+++ b/sysdeps/x86/fpu/bits/fenv.h
@@ -23,17 +23,22 @@
of the appropriate bits in the FPU control word. */
enum
{
- FE_INVALID = 0x01,
-#define FE_INVALID FE_INVALID
+ FE_INVALID =
+#define FE_INVALID 0x01
+ FE_INVALID,
__FE_DENORM = 0x02,
- FE_DIVBYZERO = 0x04,
-#define FE_DIVBYZERO FE_DIVBYZERO
- FE_OVERFLOW = 0x08,
-#define FE_OVERFLOW FE_OVERFLOW
- FE_UNDERFLOW = 0x10,
-#define FE_UNDERFLOW FE_UNDERFLOW
- FE_INEXACT = 0x20
-#define FE_INEXACT FE_INEXACT
+ FE_DIVBYZERO =
+#define FE_DIVBYZERO 0x04
+ FE_DIVBYZERO,
+ FE_OVERFLOW =
+#define FE_OVERFLOW 0x08
+ FE_OVERFLOW,
+ FE_UNDERFLOW =
+#define FE_UNDERFLOW 0x10
+ FE_UNDERFLOW,
+ FE_INEXACT =
+#define FE_INEXACT 0x20
+ FE_INEXACT
};
#define FE_ALL_EXCEPT \
@@ -44,14 +49,18 @@ enum
for the appropriate macros. */
enum
{
- FE_TONEAREST = 0,
-#define FE_TONEAREST FE_TONEAREST
- FE_DOWNWARD = 0x400,
-#define FE_DOWNWARD FE_DOWNWARD
- FE_UPWARD = 0x800,
-#define FE_UPWARD FE_UPWARD
- FE_TOWARDZERO = 0xc00
-#define FE_TOWARDZERO FE_TOWARDZERO
+ FE_TONEAREST =
+#define FE_TONEAREST 0
+ FE_TONEAREST,
+ FE_DOWNWARD =
+#define FE_DOWNWARD 0x400
+ FE_DOWNWARD,
+ FE_UPWARD =
+#define FE_UPWARD 0x800
+ FE_UPWARD,
+ FE_TOWARDZERO =
+#define FE_TOWARDZERO 0xc00
+ FE_TOWARDZERO
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-25 20:16:31 +0000