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-rw-r--r--sysdeps/powerpc/fpu/Makefile2
-rw-r--r--sysdeps/powerpc/fpu/fe_mask.c33
-rw-r--r--sysdeps/powerpc/fpu/fe_nomask.c5
-rw-r--r--sysdeps/powerpc/fpu/fedisblxcpt.c8
-rw-r--r--sysdeps/powerpc/fpu/feholdexcpt.c19
-rw-r--r--sysdeps/powerpc/fpu/fesetenv.c22
-rw-r--r--sysdeps/powerpc/fpu/feupdateenv.c22
7 files changed, 96 insertions, 15 deletions
diff --git a/sysdeps/powerpc/fpu/Makefile b/sysdeps/powerpc/fpu/Makefile
index d0fe4a8ba1..060c952d15 100644
--- a/sysdeps/powerpc/fpu/Makefile
+++ b/sysdeps/powerpc/fpu/Makefile
@@ -1,5 +1,5 @@
ifeq ($(subdir),math)
-libm-support += fenv_const fe_nomask t_sqrt
+libm-support += fenv_const fe_nomask fe_mask t_sqrt
# libm needs ld.so to access dl_hwcap
$(objpfx)libm.so: $(elfobjdir)/ld.so
diff --git a/sysdeps/powerpc/fpu/fe_mask.c b/sysdeps/powerpc/fpu/fe_mask.c
new file mode 100644
index 0000000000..d7ee5551ff
--- /dev/null
+++ b/sysdeps/powerpc/fpu/fe_mask.c
@@ -0,0 +1,33 @@
+/* Procedure definition for FE_MASK_ENV.
+ Copyright (C) 2007 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, write to the Free
+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307 USA. */
+
+#include <fenv.h>
+#include <errno.h>
+
+/* This is a generic stub. An OS specific override is required to clear
+ the FE0/FE1 bits in the MSR. MSR update is privileged, so this will
+ normally involve a syscall. */
+
+const fenv_t *
+__fe_mask_env(void)
+{
+ __set_errno (ENOSYS);
+ return FE_DFL_ENV;
+}
+stub_warning (__fe_mask_env)
diff --git a/sysdeps/powerpc/fpu/fe_nomask.c b/sysdeps/powerpc/fpu/fe_nomask.c
index ba45d85709..3cccee1d06 100644
--- a/sysdeps/powerpc/fpu/fe_nomask.c
+++ b/sysdeps/powerpc/fpu/fe_nomask.c
@@ -20,8 +20,9 @@
#include <fenv.h>
#include <errno.h>
-/* This is presently a stub, until it's decided how the kernels should
- support this. */
+/* This is a generic stub. An OS specific override is required to set
+ the FE0/FE1 bits in the MSR. MSR update is privileged, so this will
+ normally involve a syscall. */
const fenv_t *
__fe_nomask_env(void)
diff --git a/sysdeps/powerpc/fpu/fedisblxcpt.c b/sysdeps/powerpc/fpu/fedisblxcpt.c
index 633a6e6e36..3002b1b4cc 100644
--- a/sysdeps/powerpc/fpu/fedisblxcpt.c
+++ b/sysdeps/powerpc/fpu/fedisblxcpt.c
@@ -24,7 +24,7 @@ int
fedisableexcept (int excepts)
{
fenv_union_t fe;
- int result;
+ int result, new;
result = fegetexcept ();
@@ -44,7 +44,11 @@ fedisableexcept (int excepts)
fe.l[1] &= ~(1 << (31 - FPSCR_VE));
fesetenv_register (fe.fenv);
- if ((fegetexcept () & excepts) != 0)
+ new = fegetexcept ();
+ if (new == 0 && result != 0)
+ (void)__fe_mask_env ();
+
+ if ((new & excepts) != 0)
result = -1;
return result;
}
diff --git a/sysdeps/powerpc/fpu/feholdexcpt.c b/sysdeps/powerpc/fpu/feholdexcpt.c
index 150becd678..c9432248db 100644
--- a/sysdeps/powerpc/fpu/feholdexcpt.c
+++ b/sysdeps/powerpc/fpu/feholdexcpt.c
@@ -22,17 +22,24 @@
int
feholdexcept (fenv_t *envp)
{
- fenv_union_t u;
+ fenv_union_t old, new;
- /* Get the current state. */
- u.fenv = *envp = fegetenv_register ();
+ /* Save the currently set exceptions. */
+ old.fenv = *envp = fegetenv_register ();
- /* Clear everything except for the rounding mode and non-IEEE arithmetic
+ /* Clear everything except for the rounding modes and non-IEEE arithmetic
flag. */
- u.l[1] = u.l[1] & 7;
+ new.l[1] = old.l[1] & 7;
+ new.l[0] = old.l[0];
+
+ /* If the old env had any eabled exceptions, then mask SIGFPE in the
+ MSR FE0/FE1 bits. This may allow the FPU to run faster because it
+ always takes the default action and can not generate SIGFPE. */
+ if ((old.l[1] & 0x000000F8) != 0)
+ (void)__fe_mask_env ();
/* Put the new state in effect. */
- fesetenv_register (u.fenv);
+ fesetenv_register (new.fenv);
return 0;
}
diff --git a/sysdeps/powerpc/fpu/fesetenv.c b/sysdeps/powerpc/fpu/fesetenv.c
index ff82dfd176..5a0c742ffe 100644
--- a/sysdeps/powerpc/fpu/fesetenv.c
+++ b/sysdeps/powerpc/fpu/fesetenv.c
@@ -1,5 +1,5 @@
/* Install given floating-point environment.
- Copyright (C) 1997,99,2000,01,02 Free Software Foundation, Inc.
+ Copyright (C) 1997,99,2000,01,02,07 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -23,6 +23,26 @@
int
__fesetenv (const fenv_t *envp)
{
+ fenv_union_t old, new;
+
+ /* get the currently set exceptions. */
+ new.fenv = *envp;
+ old.fenv = fegetenv_register ();
+
+ /* If the old env has no eabled exceptions and the new env has any enabled
+ exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put
+ the hardware into "precise mode" and may cause the FPU to run slower on
+ some hardware. */
+ if ((old.l[1] & 0x000000F8) == 0 && (new.l[1] & 0x000000F8) != 0)
+ (void)__fe_nomask_env ();
+
+ /* If the old env had any eabled exceptions and the new env has no enabled
+ exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
+ FPU to run faster because it always takes the default action and can not
+ generate SIGFPE. */
+ if ((old.l[1] & 0x000000F8) != 0 && (new.l[1] & 0x000000F8) == 0)
+ (void)__fe_mask_env ();
+
fesetenv_register (*envp);
/* Success. */
diff --git a/sysdeps/powerpc/fpu/feupdateenv.c b/sysdeps/powerpc/fpu/feupdateenv.c
index 3a60d0f33d..5a4000f599 100644
--- a/sysdeps/powerpc/fpu/feupdateenv.c
+++ b/sysdeps/powerpc/fpu/feupdateenv.c
@@ -1,5 +1,5 @@
/* Install given floating-point environment and raise exceptions.
- Copyright (C) 1997,99,2000,01 Free Software Foundation, Inc.
+ Copyright (C) 1997,99,2000,01,07 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Ulrich Drepper <drepper@cygnus.com>, 1997.
@@ -30,8 +30,24 @@ __feupdateenv (const fenv_t *envp)
new.fenv = *envp;
old.fenv = fegetenv_register ();
- /* Copy the set exceptions from `old' to `new'. */
- new.l[1] = (new.l[1] & 0xE00000FF) | (old.l[1] & 0x1FFFFF00);
+ /* Restore rounding mode and exception enable from *envp and merge
+ exceptions. Leave fraction rounded/inexact and FP result/CC bits
+ unchanged. */
+ new.l[1] = (old.l[1] & 0x1FFFFF00) | (new.l[1] & 0x1FF80FFF);
+
+ /* If the old env has no eabled exceptions and the new env has any enabled
+ exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put
+ the hardware into "precise mode" and may cause the FPU to run slower on
+ some hardware. */
+ if ((old.l[1] & 0x000000F8) == 0 && (new.l[1] & 0x000000F8) != 0)
+ (void)__fe_nomask_env ();
+
+ /* If the old env had any eabled exceptions and the new env has no enabled
+ exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
+ FPU to run faster because it always takes the default action and can not
+ generate SIGFPE. */
+ if ((old.l[1] & 0x000000F8) != 0 && (new.l[1] & 0x000000F8) == 0)
+ (void)__fe_mask_env ();
/* Atomically enable and raise (if appropriate) exceptions set in `new'. */
fesetenv_register (new.fenv);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 17:31:30 +0000