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-rw-r--r--sysdeps/i386/fpu/fclrexcpt.c18
-rw-r--r--sysdeps/i386/fpu/fsetexcptflg.c19
-rw-r--r--sysdeps/i386/fpu_control.h8
-rw-r--r--sysdeps/i386/setfpucw.c55
4 files changed, 98 insertions, 2 deletions
diff --git a/sysdeps/i386/fpu/fclrexcpt.c b/sysdeps/i386/fpu/fclrexcpt.c
index c3e7c3ed48..f7ccd3acf6 100644
--- a/sysdeps/i386/fpu/fclrexcpt.c
+++ b/sysdeps/i386/fpu/fclrexcpt.c
@@ -19,6 +19,9 @@
02111-1307 USA. */
#include <fenv.h>
+#include <unistd.h>
+#include <ldsodefs.h>
+#include <dl-procinfo.h>
int
__feclearexcept (int excepts)
@@ -38,6 +41,21 @@ __feclearexcept (int excepts)
/* Put the new data in effect. */
__asm__ ("fldenv %0" : : "m" (*&temp));
+ /* If the CPU supports SSE, we clear the MXCSR as well. */
+ if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
+ {
+ unsigned int xnew_exc;
+
+ /* Get the current MXCSR. */
+ __asm__ ("stmxcsr %0" : "=m" (*&xnew_exc));
+
+ /* Clear the relevant bits. */
+ xnew_exc &= excepts ^ FE_ALL_EXCEPT;
+
+ /* Put the new data in effect. */
+ __asm__ ("ldmxcsr %0" : : "m" (*&xnew_exc));
+ }
+
/* Success. */
return 0;
}
diff --git a/sysdeps/i386/fpu/fsetexcptflg.c b/sysdeps/i386/fpu/fsetexcptflg.c
index 2bfc736054..d262738b68 100644
--- a/sysdeps/i386/fpu/fsetexcptflg.c
+++ b/sysdeps/i386/fpu/fsetexcptflg.c
@@ -21,6 +21,9 @@
#include <fenv.h>
#include <math.h>
#include <bp-sym.h>
+#include <unistd.h>
+#include <ldsodefs.h>
+#include <dl-procinfo.h>
int
__fesetexceptflag (const fexcept_t *flagp, int excepts)
@@ -39,6 +42,22 @@ __fesetexceptflag (const fexcept_t *flagp, int excepts)
the next floating-point instruction. */
__asm__ ("fldenv %0" : : "m" (*&temp));
+ /* If the CPU supports SSE, we set the MXCSR as well. */
+ if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
+ {
+ unsigned int xnew_exc;
+
+ /* Get the current MXCSR. */
+ __asm__ ("stmxcsr %0" : "=m" (*&xnew_exc));
+
+ /* Set the relevant bits. */
+ xnew_exc &= ~(excepts & FE_ALL_EXCEPT);
+ xnew_exc |= *flagp & excepts & FE_ALL_EXCEPT;
+
+ /* Put the new data in effect. */
+ __asm__ ("ldmxcsr %0" : : "m" (*&xnew_exc));
+ }
+
/* Success. */
return 0;
}
diff --git a/sysdeps/i386/fpu_control.h b/sysdeps/i386/fpu_control.h
index ed9bf388a8..e2d00467b7 100644
--- a/sysdeps/i386/fpu_control.h
+++ b/sysdeps/i386/fpu_control.h
@@ -1,5 +1,5 @@
/* FPU control word bits. i387 version.
- Copyright (C) 1993,1995,1996,1997,1998,2000,2001 Free Software Foundation, Inc.
+ Copyright (C) 1993,1995-1998,2000,2001,2003 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Olaf Flebbe.
@@ -88,7 +88,11 @@
/* Type of the control word. */
typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__HI__)));
-/* Macros for accessing the hardware control word. */
+/* Macros for accessing the hardware control word.
+
+ Note that the use of these macros is no sufficient anymore with
+ recent hardware. Some floating point operations are executed in
+ the SSE/SSE2 engines which have their own control and status register. */
#define _FPU_GETCW(cw) __asm__ ("fnstcw %0" : "=m" (*&cw))
#define _FPU_SETCW(cw) __asm__ ("fldcw %0" : : "m" (*&cw))
diff --git a/sysdeps/i386/setfpucw.c b/sysdeps/i386/setfpucw.c
new file mode 100644
index 0000000000..0a6af25ddf
--- /dev/null
+++ b/sysdeps/i386/setfpucw.c
@@ -0,0 +1,55 @@
+/* Set the FPU control word for x86.
+ Copyright (C) 2003 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, write to the Free
+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307 USA. */
+
+#include <math.h>
+#include <fpu_control.h>
+#include <fenv.h>
+#include <unistd.h>
+#include <ldsodefs.h>
+#include <dl-procinfo.h>
+
+void
+__setfpucw (fpu_control_t set)
+{
+ fpu_control_t cw;
+
+ /* Fetch the current control word. */
+ __asm__ ("fnstcw %0" : "=m" (*&cw));
+
+ /* Preserve the reserved bits, and set the rest as the user
+ specified (or the default, if the user gave zero). */
+ cw &= _FPU_RESERVED;
+ cw |= set & ~_FPU_RESERVED;
+
+ __asm__ ("fldcw %0" : : "m" (*&cw));
+
+ /* If the CPU supports SSE, we set the MXCSR as well. */
+ if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
+ {
+ unsigned int xnew_exc;
+
+ /* Get the current MXCSR. */
+ __asm__ ("stmxcsr %0" : "=m" (*&xnew_exc));
+
+ xnew_exc &= ~((0xc00 << 3) | (FE_ALL_EXCEPT << 7));
+ xnew_exc |= ((set & 0xc00) << 3) | ((set & FE_ALL_EXCEPT) << 7);
+
+ __asm__ ("ldmxcsr %0" : : "m" (*&xnew_exc));
+ }
+}