diff options
Diffstat (limited to 'REORG.TODO/sysdeps/sparc')
457 files changed, 32025 insertions, 0 deletions
diff --git a/REORG.TODO/sysdeps/sparc/Makefile b/REORG.TODO/sysdeps/sparc/Makefile new file mode 100644 index 0000000000..31aaeaed8f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/Makefile @@ -0,0 +1,24 @@ +# The Sparc `long double' is a distinct type we support. +long-double-fcts = yes + +pie-ccflag = -fPIE + +ifeq ($(subdir),debug) +CFLAGS-backtrace.c += -funwind-tables +endif + +ifeq ($(subdir),gmon) +sysdep_routines += sparc-mcount +endif + +ifeq ($(subdir),db2) +CPPFLAGS += -DHAVE_SPINLOCKS=1 -DHAVE_ASSEM_SPARC_GCC=1 +endif + +ifeq ($(subdir),csu) +CPPFLAGS-crti.S += -fPIC +CPPFLAGS-crtn.S += -fPIC +endif + +# The assembler on SPARC needs the -fPIC flag even when it's assembler code. +ASFLAGS-.os += -fPIC diff --git a/REORG.TODO/sysdeps/sparc/Subdirs b/REORG.TODO/sysdeps/sparc/Subdirs new file mode 100644 index 0000000000..87eadf3024 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/Subdirs @@ -0,0 +1 @@ +soft-fp diff --git a/REORG.TODO/sysdeps/sparc/abort-instr.h b/REORG.TODO/sysdeps/sparc/abort-instr.h new file mode 100644 index 0000000000..ea92dfe866 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/abort-instr.h @@ -0,0 +1,2 @@ +/* An instruction which should crash any program is an unimp. */ +#define ABORT_INSTRUCTION asm ("unimp 0xf00") diff --git a/REORG.TODO/sysdeps/sparc/backtrace.c b/REORG.TODO/sysdeps/sparc/backtrace.c new file mode 100644 index 0000000000..2887031c72 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/backtrace.c @@ -0,0 +1,159 @@ +/* Return backtrace of current program state. + Copyright (C) 2013-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net> + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Library General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Library General Public License for more details. + + You should have received a copy of the GNU Library General Public + License along with the GNU C Library; see the file COPYING.LIB. If + not, see <http://www.gnu.org/licenses/>. */ + +#include <execinfo.h> +#include <stddef.h> +#include <sysdep.h> +#include <sys/trap.h> +#include <dlfcn.h> +#include <unwind.h> +#include <backtrace.h> + +struct layout +{ + unsigned long locals[8]; + unsigned long ins[6]; + unsigned long next; + void *return_address; +}; + +struct trace_arg +{ + void **array; + _Unwind_Word cfa; + int cnt; + int size; +}; + +#ifdef SHARED +static _Unwind_Reason_Code (*unwind_backtrace) (_Unwind_Trace_Fn, void *); +static _Unwind_Ptr (*unwind_getip) (struct _Unwind_Context *); +static _Unwind_Word (*unwind_getcfa) (struct _Unwind_Context *); +static void *libgcc_handle; + +/* Dummy version in case libgcc_s does not contain the real code. */ +static _Unwind_Word +dummy_getcfa (struct _Unwind_Context *ctx __attribute__ ((unused))) +{ + return 0; +} + +static void +init (void) +{ + libgcc_handle = __libc_dlopen ("libgcc_s.so.1"); + + if (libgcc_handle == NULL) + return; + + unwind_backtrace = __libc_dlsym (libgcc_handle, "_Unwind_Backtrace"); + unwind_getip = __libc_dlsym (libgcc_handle, "_Unwind_GetIP"); + if (unwind_getip == NULL) + unwind_backtrace = NULL; + unwind_getcfa = (__libc_dlsym (libgcc_handle, "_Unwind_GetCFA") + ?: dummy_getcfa); +} +#else +# define unwind_backtrace _Unwind_Backtrace +# define unwind_getip _Unwind_GetIP +# define unwind_getcfa _Unwind_GetCFA +#endif + +static _Unwind_Reason_Code +backtrace_helper (struct _Unwind_Context *ctx, void *a) +{ + struct trace_arg *arg = a; + _Unwind_Ptr ip; + + /* We are first called with address in the __backtrace function. + Skip it. */ + if (arg->cnt != -1) + { + ip = unwind_getip (ctx); + arg->array[arg->cnt] = (void *) ip; + + /* Check whether we make any progress. */ + _Unwind_Word cfa = unwind_getcfa (ctx); + + if (arg->cnt > 0 && arg->array[arg->cnt - 1] == arg->array[arg->cnt] + && cfa == arg->cfa) + return _URC_END_OF_STACK; + arg->cfa = cfa; + } + if (++arg->cnt == arg->size) + return _URC_END_OF_STACK; + return _URC_NO_REASON; +} + +int +__backtrace (void **array, int size) +{ + struct trace_arg arg = { .array = array, .cfa = 0, .size = size, .cnt = -1 }; + bool use_unwinder; + int count; + + if (size <= 0) + return 0; + + use_unwinder = true; +#ifdef SHARED + __libc_once_define (static, once); + + __libc_once (once, init); + if (unwind_backtrace == NULL) + use_unwinder = false; +#endif + + if (use_unwinder == false) + { + struct layout *current; + unsigned long fp, i7; + + asm volatile ("mov %%fp, %0" : "=r"(fp)); + asm volatile ("mov %%i7, %0" : "=r"(i7)); + current = (struct layout *) (fp + BACKTRACE_STACK_BIAS); + + array[0] = (void *) i7; + + if (size == 1) + return 1; + + backtrace_flush_register_windows(); + for (count = 1; count < size; count++) + { + array[count] = current->return_address; + if (!current->next) + break; + current = (struct layout *) (current->next + BACKTRACE_STACK_BIAS); + } + } + else + { + unwind_backtrace (backtrace_helper, &arg); + + /* _Unwind_Backtrace seems to put NULL address above + _start. Fix it up here. */ + if (arg.cnt > 1 && arg.array[arg.cnt - 1] == NULL) + --arg.cnt; + count = arg.cnt != -1 ? arg.cnt : 0; + } + return count; +} +weak_alias (__backtrace, backtrace) +libc_hidden_def (__backtrace) diff --git a/REORG.TODO/sysdeps/sparc/bits/endian.h b/REORG.TODO/sysdeps/sparc/bits/endian.h new file mode 100644 index 0000000000..8acfdf5df6 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/bits/endian.h @@ -0,0 +1,12 @@ +/* Sparc is big-endian, but v9 supports endian conversion on loads/stores + and GCC supports such a mode. Be prepared. */ + +#ifndef _ENDIAN_H +# error "Never use <bits/endian.h> directly; include <endian.h> instead." +#endif + +#ifdef __LITTLE_ENDIAN__ +# define __BYTE_ORDER __LITTLE_ENDIAN +#else +# define __BYTE_ORDER __BIG_ENDIAN +#endif diff --git a/REORG.TODO/sysdeps/sparc/bits/huge_vall.h b/REORG.TODO/sysdeps/sparc/bits/huge_vall.h new file mode 100644 index 0000000000..6704bc0528 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/bits/huge_vall.h @@ -0,0 +1,47 @@ +/* `HUGE_VALL' constant for IEEE 754 machines (where it is infinity). + Used by <stdlib.h> and <math.h> functions for overflow. + Copyright (C) 1992-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _MATH_H +# error "Never use <bits/huge_vall.h> directly; include <math.h> instead." +#endif + +#if __GNUC_PREREQ(3,3) +# define HUGE_VALL (__builtin_huge_vall()) +#else +# include <bits/wordsize.h> +# if __WORDSIZE == 32 +# define HUGE_VALL ((long double) HUGE_VAL) +# elif __GNUC_PREREQ(2,96) +# define HUGE_VALL (__extension__ 0x1.0p32767L) +# elif defined __GNUC__ + +# define HUGE_VALL \ + (__extension__ \ + ((union { struct { unsigned long __h, __l; } __i; long double __d; }) \ + { __i: { __h: 0x7fff000000000000UL, __l: 0 } }).__d) + +# else /* not GCC */ + +typedef union { unsigned char __c[16]; long double __d; } __huge_vall_t; +# define __HUGE_VALL_bytes { 0x7f, 0xff, 0,0,0,0,0,0,0,0,0,0,0,0,0,0 } +static __huge_vall_t __huge_vall = { __HUGE_VALL_bytes }; +# define HUGE_VALL (__huge_vall.__d) + +# endif /* GCC. */ +#endif /* GCC 3.3. */ diff --git a/REORG.TODO/sysdeps/sparc/bits/hwcap.h b/REORG.TODO/sysdeps/sparc/bits/hwcap.h new file mode 100644 index 0000000000..e0907239d7 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/bits/hwcap.h @@ -0,0 +1,50 @@ +/* Defines for bits in AT_HWCAP. + Copyright (C) 2011-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#if !defined(_SYS_AUXV_H) && !defined(_SYSDEPS_SYSDEP_H) +# error "Never include <bits/hwcap.h> directly; use <sys/auxv.h> instead." +#endif + +#define HWCAP_SPARC_FLUSH 0x00000001 +#define HWCAP_SPARC_STBAR 0x00000002 +#define HWCAP_SPARC_SWAP 0x00000004 +#define HWCAP_SPARC_MULDIV 0x00000008 +#define HWCAP_SPARC_V9 0x00000010 +#define HWCAP_SPARC_ULTRA3 0x00000020 +#define HWCAP_SPARC_BLKINIT 0x00000040 +#define HWCAP_SPARC_N2 0x00000080 +#define HWCAP_SPARC_MUL32 0x00000100 +#define HWCAP_SPARC_DIV32 0x00000200 +#define HWCAP_SPARC_FSMULD 0x00000400 +#define HWCAP_SPARC_V8PLUS 0x00000800 +#define HWCAP_SPARC_POPC 0x00001000 +#define HWCAP_SPARC_VIS 0x00002000 +#define HWCAP_SPARC_VIS2 0x00004000 +#define HWCAP_SPARC_ASI_BLK_INIT 0x00008000 +#define HWCAP_SPARC_FMAF 0x00010000 +#define HWCAP_SPARC_VIS3 0x00020000 +#define HWCAP_SPARC_HPC 0x00040000 +#define HWCAP_SPARC_RANDOM 0x00080000 +#define HWCAP_SPARC_TRANS 0x00100000 +#define HWCAP_SPARC_FJFMAU 0x00200000 +#define HWCAP_SPARC_IMA 0x00400000 +#define HWCAP_SPARC_ASI_CACHE_SPARING \ + 0x00800000 +#define HWCAP_SPARC_PAUSE 0x01000000 +#define HWCAP_SPARC_CBCOND 0x02000000 +#define HWCAP_SPARC_CRYPTO 0x04000000 diff --git a/REORG.TODO/sysdeps/sparc/bits/link.h b/REORG.TODO/sysdeps/sparc/bits/link.h new file mode 100644 index 0000000000..74e260f8f4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/bits/link.h @@ -0,0 +1,99 @@ +/* Machine-specific audit interfaces for dynamic linker. SPARC version. + Copyright (C) 2005-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _LINK_H +# error "Never include <bits/link.h> directly; use <link.h> instead." +#endif + +#if __WORDSIZE == 32 + +typedef struct La_sparc32_regs +{ + uint32_t lr_lreg[8]; /* %l0 through %l7 */ + uint32_t lr_reg[6]; /* %o0 through %o5 */ + uint32_t lr_sp; /* %o6 */ + uint32_t lr_ra; /* %o7 */ + uint32_t lr_struct; /* Pass-by-reference struct pointer */ +} La_sparc32_regs; + +typedef struct La_sparc32_retval +{ + uint32_t lrv_reg[2]; /* %o0 and %o1 */ + double lrv_fpreg[2]; /* %f0 and %f2 */ +} La_sparc32_retval; + +#else + +typedef struct La_sparc64_regs +{ + uint64_t lr_lreg[8]; /* %l0 through %l7 */ + uint64_t lr_reg[6]; /* %o0 through %o5 */ + uint64_t lr_sp; /* %o6 */ + uint64_t lr_ra; /* %o7 */ + double lr_fpreg[16]; /* %f0 through %f30 */ +} La_sparc64_regs; + +typedef struct La_sparc64_retval +{ + uint64_t lrv_reg[4]; /* %o0 through %o3 */ + double lrv_fprev[4]; /* %f0 through %f8 */ +} La_sparc64_retval; + +#endif + +__BEGIN_DECLS + +#if __WORDSIZE == 32 + +extern Elf32_Addr la_sparc32_gnu_pltenter (Elf32_Sym *__sym, + unsigned int __ndx, + uintptr_t *__refcook, + uintptr_t *__defcook, + La_sparc32_regs *__regs, + unsigned int *__flags, + const char *__symname, + long int *__framesizep); +extern unsigned int la_sparc32_gnu_pltexit (Elf32_Sym *__sym, + unsigned int __ndx, + uintptr_t *__refcook, + uintptr_t *__defcook, + const La_sparc32_regs *__inregs, + La_sparc32_retval *__outregs, + const char *__symname); + +#else + +extern Elf64_Addr la_sparc64_gnu_pltenter (Elf64_Sym *__sym, + unsigned int __ndx, + uintptr_t *__refcook, + uintptr_t *__defcook, + La_sparc64_regs *__regs, + unsigned int *__flags, + const char *__symname, + long int *__framesizep); +extern unsigned int la_sparc64_gnu_pltexit (Elf64_Sym *__sym, + unsigned int __ndx, + uintptr_t *__refcook, + uintptr_t *__defcook, + const La_sparc64_regs *__inregs, + La_sparc64_retval *__outregs, + const char *__symname); + +#endif + +__END_DECLS diff --git a/REORG.TODO/sysdeps/sparc/bits/string.h b/REORG.TODO/sysdeps/sparc/bits/string.h new file mode 100644 index 0000000000..4fd4e8d1de --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/bits/string.h @@ -0,0 +1,31 @@ +/* Optimized, inlined string functions. SPARC version. + Copyright (C) 2000-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _STRING_H +# error "Never use <bits/string.h> directly; include <string.h> instead." +#endif + +/* sparc uses the aligned string inline ABI. */ +#define _STRING_INLINE_unaligned 0 + +/* sparc32 and sparc64 strchr(x, '\0') perform better than + __rawmemchr(x, '\0'). */ +#define _HAVE_STRING_ARCH_strchr 1 + +/* Don't inline mempcpy into memcpy as sparc has an optimized mempcpy. */ +#define _HAVE_STRING_ARCH_mempcpy 1 diff --git a/REORG.TODO/sysdeps/sparc/configure b/REORG.TODO/sysdeps/sparc/configure new file mode 100644 index 0000000000..90a86f6da3 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/configure @@ -0,0 +1,83 @@ +# This file is generated from configure.ac by Autoconf. DO NOT EDIT! + # Local configure fragment for sysdeps/sparc. + +# Check for support of VIS3 et al. instructions in the assembler. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for sparc assembler VIS3 support" >&5 +$as_echo_n "checking for sparc assembler VIS3 support... " >&6; } +if ${libc_cv_sparc_as_vis3+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat > conftest.S <<\EOF + .text +foo: fmadds %f1, %f2, %f3, %f5 + fmaddd %f2, %f4, %f8, %f10 + fhadds %f2, %f3, %f5 + fhaddd %f4, %f8, %f10 + pdistn %f2, %f4, %g1 + movdtox %f10, %o0 + movstouw %f9, %o1 + movstosw %f7, %o2 + movxtod %o3, %f18 + movwtos %o4, %f15 + flcmps %fcc0, %f3, %f5 + flcmpd %fcc1, %f4, %f6 +EOF +if { ac_try='${CC-cc} -c $CFLAGS -Wa,-Av9d conftest.S' + { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 + (eval $ac_try) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; }; then + libc_cv_sparc_as_vis3=yes +else + libc_cv_sparc_as_vis3=no +fi +rm -f conftest* +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libc_cv_sparc_as_vis3" >&5 +$as_echo "$libc_cv_sparc_as_vis3" >&6; } +if test $libc_cv_sparc_as_vis3 = yes; then + $as_echo "#define HAVE_AS_VIS3_SUPPORT 1" >>confdefs.h + +fi +config_vars="$config_vars +have-as-vis3 = $libc_cv_sparc_as_vis3" + +# Check for a GCC emitting GOTDATA relocations. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for sparc gcc GOTDATA reloc support" >&5 +$as_echo_n "checking for sparc gcc GOTDATA reloc support... " >&6; } +if ${libc_cv_sparc_gcc_gotdata+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat > conftest.c <<\EOF +int data; +int foo(void) +{ + return data; +} +EOF +libc_cv_sparc_gcc_gotdata=no +if { ac_try='${CC-cc} -S $CFLAGS -O2 -fPIC conftest.c 1>&5' + { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 + (eval $ac_try) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; }; then + if grep -q 'gdop_hix22' conftest.s \ + && grep -q 'gdop_lox10' conftest.s; then + libc_cv_sparc_gcc_gotdata=yes + fi +fi +rm -f conftest* +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libc_cv_sparc_gcc_gotdata" >&5 +$as_echo "$libc_cv_sparc_gcc_gotdata" >&6; } +if test $libc_cv_sparc_gcc_gotdata = yes; then + $as_echo "#define HAVE_GCC_GOTDATA 1" >>confdefs.h + +fi + +if test $libc_cv_sparc_gcc_gotdata = yes; then + $as_echo "#define PI_STATIC_AND_HIDDEN 1" >>confdefs.h + +fi diff --git a/REORG.TODO/sysdeps/sparc/configure.ac b/REORG.TODO/sysdeps/sparc/configure.ac new file mode 100644 index 0000000000..982077c9b9 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/configure.ac @@ -0,0 +1,59 @@ +GLIBC_PROVIDES dnl See aclocal.m4 in the top level source directory. +# Local configure fragment for sysdeps/sparc. + +# Check for support of VIS3 et al. instructions in the assembler. +AC_CACHE_CHECK(for sparc assembler VIS3 support, libc_cv_sparc_as_vis3, [dnl +cat > conftest.S <<\EOF + .text +foo: fmadds %f1, %f2, %f3, %f5 + fmaddd %f2, %f4, %f8, %f10 + fhadds %f2, %f3, %f5 + fhaddd %f4, %f8, %f10 + pdistn %f2, %f4, %g1 + movdtox %f10, %o0 + movstouw %f9, %o1 + movstosw %f7, %o2 + movxtod %o3, %f18 + movwtos %o4, %f15 + flcmps %fcc0, %f3, %f5 + flcmpd %fcc1, %f4, %f6 +EOF +dnl +if AC_TRY_COMMAND([${CC-cc} -c $CFLAGS -Wa,-Av9d conftest.S]); then + libc_cv_sparc_as_vis3=yes +else + libc_cv_sparc_as_vis3=no +fi +rm -f conftest*]) +if test $libc_cv_sparc_as_vis3 = yes; then + AC_DEFINE(HAVE_AS_VIS3_SUPPORT) +fi +LIBC_CONFIG_VAR([have-as-vis3], [$libc_cv_sparc_as_vis3]) + +# Check for a GCC emitting GOTDATA relocations. +AC_CACHE_CHECK(for sparc gcc GOTDATA reloc support, libc_cv_sparc_gcc_gotdata, [dnl +changequote(,)dnl +cat > conftest.c <<\EOF +int data; +int foo(void) +{ + return data; +} +EOF +changequote([,])dnl +dnl +libc_cv_sparc_gcc_gotdata=no +if AC_TRY_COMMAND(${CC-cc} -S $CFLAGS -O2 -fPIC conftest.c 1>&AS_MESSAGE_LOG_FD); then + if grep -q 'gdop_hix22' conftest.s \ + && grep -q 'gdop_lox10' conftest.s; then + libc_cv_sparc_gcc_gotdata=yes + fi +fi +rm -f conftest*]) +if test $libc_cv_sparc_gcc_gotdata = yes; then + AC_DEFINE(HAVE_GCC_GOTDATA) +fi + +if test $libc_cv_sparc_gcc_gotdata = yes; then + AC_DEFINE(PI_STATIC_AND_HIDDEN) +fi diff --git a/REORG.TODO/sysdeps/sparc/crti.S b/REORG.TODO/sysdeps/sparc/crti.S new file mode 100644 index 0000000000..1afd816ee7 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/crti.S @@ -0,0 +1,93 @@ +/* Special .init and .fini section support for sparc. + Copyright (C) 1995-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + In addition to the permissions in the GNU Lesser General Public + License, the Free Software Foundation gives you unlimited + permission to link the compiled version of this file with other + programs, and to distribute those programs without any restriction + coming from the use of this file. (The GNU Lesser General Public + License restrictions do apply in other respects; for example, they + cover modification of the file, and distribution when not linked + into another program.) + + Note that people who make modified versions of this file are not + obligated to grant this special exception for their modified + versions; it is their choice whether to do so. The GNU Lesser + General Public License gives permission to release a modified + version without this exception; this exception also makes it + possible to release a modified version which carries forward this + exception. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +/* crti.S puts a function prologue at the beginning of the .init and + .fini sections and defines global symbols for those addresses, so + they can be called as functions. The symbols _init and _fini are + magic and cause the linker to emit DT_INIT and DT_FINI. */ + +#include <libc-symbols.h> +#include <sysdep.h> + +#ifndef PREINIT_FUNCTION +# define PREINIT_FUNCTION __gmon_start__ +#endif + +#ifndef PREINIT_FUNCTION_WEAK +# define PREINIT_FUNCTION_WEAK 1 +#endif + +#if PREINIT_FUNCTION_WEAK + weak_extern (PREINIT_FUNCTION) +#else + .hidden PREINIT_FUNCTION +#endif + +#ifdef __arch64__ +#define STACKFRAME_SIZE 176 +#define GOT_LOAD ldx +#else +#define STACKFRAME_SIZE 96 +#define GOT_LOAD ld +#endif + + .section .init,"ax",@progbits + .p2align 2 + .globl _init + .type _init, @function +_init: + save %sp, -STACKFRAME_SIZE, %sp +#if PREINIT_FUNCTION_WEAK + SETUP_PIC_REG(l7) + sethi %gdop_hix22(PREINIT_FUNCTION), %g1 + xor %g1, %gdop_lox10(PREINIT_FUNCTION), %g1 + GOT_LOAD [%l7 + %g1], %g1, %gdop(PREINIT_FUNCTION) + cmp %g1, 0 + be 1f + nop + call PREINIT_FUNCTION + nop +1: +#else + call PREINIT_FUNCTION + nop +#endif + + .section .fini,"ax",@progbits + .p2align 2 + .globl _fini + .type _fini, @function +_fini: + save %sp, -STACKFRAME_SIZE, %sp diff --git a/REORG.TODO/sysdeps/sparc/crtn.S b/REORG.TODO/sysdeps/sparc/crtn.S new file mode 100644 index 0000000000..7c2cc96727 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/crtn.S @@ -0,0 +1,45 @@ +/* Special .init and .fini section support for sparc. + Copyright (C) 1995-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + In addition to the permissions in the GNU Lesser General Public + License, the Free Software Foundation gives you unlimited + permission to link the compiled version of this file with other + programs, and to distribute those programs without any restriction + coming from the use of this file. (The GNU Lesser General Public + License restrictions do apply in other respects; for example, they + cover modification of the file, and distribution when not linked + into another program.) + + Note that people who make modified versions of this file are not + obligated to grant this special exception for their modified + versions; it is their choice whether to do so. The GNU Lesser + General Public License gives permission to release a modified + version without this exception; this exception also makes it + possible to release a modified version which carries forward this + exception. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +/* crtn.S puts function epilogues in the .init and .fini sections + corresponding to the prologues in crti.S. */ + + .section .init,"ax",@progbits + jmp %i7 + 8 + restore + + .section .fini,"ax",@progbits + jmp %i7 + 8 + restore diff --git a/REORG.TODO/sysdeps/sparc/dl-dtprocnum.h b/REORG.TODO/sysdeps/sparc/dl-dtprocnum.h new file mode 100644 index 0000000000..90e956d646 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/dl-dtprocnum.h @@ -0,0 +1,21 @@ +/* Configuration of lookup functions. SPARC version. + Copyright (C) 2000-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +/* Number of extra dynamic section entries for this architecture. By + default there are none. */ +#define DT_THISPROCNUM DT_SPARC_NUM diff --git a/REORG.TODO/sysdeps/sparc/dl-procinfo.c b/REORG.TODO/sysdeps/sparc/dl-procinfo.c new file mode 100644 index 0000000000..653bdfb546 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/dl-procinfo.c @@ -0,0 +1,64 @@ +/* Data for Linux/sparc version of processor capability information. + Copyright (C) 2002-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jakub@redhat.com>, 2002. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +/* This information must be kept in sync with the _DL_HWCAP_COUNT + definition in procinfo.h. + + If anything should be added here check whether the size of each string + is still ok with the given array size. + + All the #ifdefs in the definitions ar equite irritating but + necessary if we want to avoid duplicating the information. There + are three different modes: + + - PROCINFO_DECL is defined. This means we are only interested in + declarations. + + - PROCINFO_DECL is not defined: + + + if SHARED is defined the file is included in an array + initializer. The .element = { ... } syntax is needed. + + + if SHARED is not defined a normal array initialization is + needed. + */ + +#ifndef PROCINFO_CLASS +#define PROCINFO_CLASS +#endif + +#if !defined PROCINFO_DECL && defined SHARED + ._dl_sparc_cap_flags +#else +PROCINFO_CLASS const char _dl_sparc_cap_flags[27][11] +#endif +#ifndef PROCINFO_DECL + = { "flush", "stbar", "swap", "muldiv", "v9", "ultra3", "v9v", "v9v2", + "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2", + "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau", + "ima", "cspare", "pause", "cbcond", "crypto" } +#endif +#if !defined SHARED || defined PROCINFO_DECL +; +#else +, +#endif + +#undef PROCINFO_DECL +#undef PROCINFO_CLASS diff --git a/REORG.TODO/sysdeps/sparc/dl-procinfo.h b/REORG.TODO/sysdeps/sparc/dl-procinfo.h new file mode 100644 index 0000000000..456dde6c9e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/dl-procinfo.h @@ -0,0 +1,79 @@ +/* Linux/sparc version of processor capability information handling macros. + Copyright (C) 1999-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jj@ultra.linux.cz>, 1999. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _DL_PROCINFO_H +#define _DL_PROCINFO_H 1 + +#include <ldsodefs.h> +#include <sysdep.h> + +#define _DL_HWCAP_COUNT 27 + +static inline int +__attribute__ ((unused)) +_dl_procinfo (unsigned int type, unsigned long int word) +{ + int i; + + /* Fallback to unknown output mechanism. */ + if (type == AT_HWCAP2) + return -1; + + _dl_printf ("AT_HWCAP: "); + + for (i = 0; i < _DL_HWCAP_COUNT; ++i) + if (word & (1 << i)) + _dl_printf (" %s", GLRO(dl_sparc_cap_flags)[i]); + + _dl_printf ("\n"); + + return 0; +} + +static inline const char * +__attribute__ ((unused)) +_dl_hwcap_string (int idx) +{ + return GLRO(dl_sparc_cap_flags)[idx]; +}; + +static inline int +__attribute__ ((unused, always_inline)) +_dl_string_hwcap (const char *str) +{ + int i; + for (i = 0; i < _DL_HWCAP_COUNT; i++) + { + if (strcmp (str, GLRO(dl_sparc_cap_flags) [i]) == 0) + return i; + } + return -1; +}; + +#include <bits/wordsize.h> +#define HWCAP_IMPORTANT_V9 (__WORDSIZE == 64 ? 0 : HWCAP_SPARC_V9) +#define HWCAP_IMPORTANT (HWCAP_IMPORTANT_V9 | HWCAP_SPARC_ULTRA3 \ + | HWCAP_SPARC_BLKINIT | HWCAP_SPARC_N2) + +/* There're no platforms to filter out. */ +#define _DL_HWCAP_PLATFORM 0 + +#define _dl_string_platform(str) (-1) + +#endif /* dl-procinfo.h */ diff --git a/REORG.TODO/sysdeps/sparc/dl-sysdep.h b/REORG.TODO/sysdeps/sparc/dl-sysdep.h new file mode 100644 index 0000000000..caf5c5fb32 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/dl-sysdep.h @@ -0,0 +1,23 @@ +/* System-specific settings for dynamic linker code. SPARC version. + Copyright (C) 2002-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include_next <dl-sysdep.h> + +/* _dl_argv cannot be attribute_relro, because _dl_start_user + might write into it after _dl_start returns. */ +#define DL_ARGV_NOT_RELRO 1 diff --git a/REORG.TODO/sysdeps/sparc/dl-tls.h b/REORG.TODO/sysdeps/sparc/dl-tls.h new file mode 100644 index 0000000000..bee27e267b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/dl-tls.h @@ -0,0 +1,28 @@ +/* Thread-local storage handling in the ELF dynamic linker. SPARC version. + Copyright (C) 2003-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + + +/* Type used for the representation of TLS information in the GOT. */ +typedef struct +{ + unsigned long int ti_module; + unsigned long int ti_offset; +} tls_index; + + +extern void *__tls_get_addr (tls_index *ti); diff --git a/REORG.TODO/sysdeps/sparc/fpu/bits/fenv.h b/REORG.TODO/sysdeps/sparc/fpu/bits/fenv.h new file mode 100644 index 0000000000..95e37d0b2c --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/bits/fenv.h @@ -0,0 +1,101 @@ +/* Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _FENV_H +# error "Never use <bits/fenv.h> directly; include <fenv.h> instead." +#endif + +#include <bits/wordsize.h> + + +/* Define bits representing the exception. We use the bit positions + of the appropriate accrued exception bits from the FSR. */ +enum + { + FE_INVALID = +#define FE_INVALID (1 << 9) + FE_INVALID, + FE_OVERFLOW = +#define FE_OVERFLOW (1 << 8) + FE_OVERFLOW, + FE_UNDERFLOW = +#define FE_UNDERFLOW (1 << 7) + FE_UNDERFLOW, + FE_DIVBYZERO = +#define FE_DIVBYZERO (1 << 6) + FE_DIVBYZERO, + FE_INEXACT = +#define FE_INEXACT (1 << 5) + FE_INEXACT + }; + +#define FE_ALL_EXCEPT \ + (FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID) + +/* The Sparc FPU supports all of the four defined rounding modes. We + use again the bit positions in the FPU control word as the values + for the appropriate macros. */ +enum + { + FE_TONEAREST = +#define FE_TONEAREST (0 << 30) + FE_TONEAREST, + FE_TOWARDZERO = +#define FE_TOWARDZERO (1 << 30) + FE_TOWARDZERO, + FE_UPWARD = +#define FE_UPWARD (-0x7fffffff - 1) /* (2 << 30) */ + FE_UPWARD, + FE_DOWNWARD = +#define FE_DOWNWARD (-0x40000000) /* (3 << 30) */ + FE_DOWNWARD + }; + +#define __FE_ROUND_MASK (3U << 30) + + +/* Type representing exception flags. */ +typedef unsigned long int fexcept_t; + + +/* Type representing floating-point environment. */ +typedef unsigned long int fenv_t; + +/* If the default argument is used we use this value. */ +#define FE_DFL_ENV ((const fenv_t *) -1) + +#ifdef __USE_GNU +/* Floating-point environment where none of the exception is masked. */ +# define FE_NOMASK_ENV ((const fenv_t *) -2) +#endif + +/* For internal use only: access the fp state register. */ +#if __WORDSIZE == 64 +# define __fenv_stfsr(X) __asm__ __volatile__ ("stx %%fsr,%0" : "=m" (X)) +# define __fenv_ldfsr(X) __asm__ __volatile__ ("ldx %0,%%fsr" : : "m" (X)) +#else +# define __fenv_stfsr(X) __asm__ __volatile__ ("st %%fsr,%0" : "=m" (X)) +# define __fenv_ldfsr(X) __asm__ __volatile__ ("ld %0,%%fsr" : : "m" (X)) +#endif + +#if __GLIBC_USE (IEC_60559_BFP_EXT) +/* Type representing floating-point control modes. */ +typedef unsigned long int femode_t; + +/* Default floating-point control modes. */ +# define FE_DFL_MODE ((const femode_t *) -1L) +#endif diff --git a/REORG.TODO/sysdeps/sparc/fpu/bits/mathinline.h b/REORG.TODO/sysdeps/sparc/fpu/bits/mathinline.h new file mode 100644 index 0000000000..60a2028f2c --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/bits/mathinline.h @@ -0,0 +1,290 @@ +/* Inline math functions for SPARC. + Copyright (C) 1999-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jakub@redhat.com>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _MATH_H +# error "Never use <bits/mathinline.h> directly; include <math.h> instead." +#endif + +#include <bits/wordsize.h> + +#ifdef __GNUC__ + +#if defined __USE_ISOC99 && !__GNUC_PREREQ (3, 0) +# undef isgreater +# undef isgreaterequal +# undef isless +# undef islessequal +# undef islessgreater +# undef isunordered + +# if __WORDSIZE == 32 + +# ifndef __NO_LONG_DOUBLE_MATH + +# define __unordered_cmp(x, y) \ + (__extension__ \ + ({ unsigned __r; \ + if (sizeof (x) == 4 && sizeof (y) == 4) \ + { \ + float __x = (x); float __y = (y); \ + __asm__ ("fcmps %1,%2; st %%fsr, %0" : "=m" (__r) : "f" (__x), \ + "f" (__y) : "cc"); \ + } \ + else if (sizeof (x) <= 8 && sizeof (y) <= 8) \ + { \ + double __x = (x); double __y = (y); \ + __asm__ ("fcmpd\t%1,%2\n\tst\t%%fsr,%0" : "=m" (__r) : "f" (__x), \ + "f" (__y) : "cc"); \ + } \ + else \ + { \ + long double __x = (x); long double __y = (y); \ + extern int _Q_cmp (const long double a, const long double b); \ + __r = _Q_cmp (__x, __y) << 10; \ + } \ + __r; })) + +# else + +# define __unordered_cmp(x, y) \ + (__extension__ \ + ({ unsigned __r; \ + if (sizeof (x) == 4 && sizeof (y) == 4) \ + { \ + float __x = (x); float __y = (y); \ + __asm__ ("fcmps %1,%2; st %%fsr, %0" : "=m" (__r) : "f" (__x), \ + "f" (__y) : "cc"); \ + } \ + else \ + { \ + double __x = (x); double __y = (y); \ + __asm__ ("fcmpd\t%1,%2\n\tst\t%%fsr,%0" : "=m" (__r) : "f" (__x), \ + "f" (__y) : "cc"); \ + } \ + __r; })) + +# endif + +# define isgreater(x, y) ((__unordered_cmp (x, y) & (3 << 10)) == (2 << 10)) +# define isgreaterequal(x, y) ((__unordered_cmp (x, y) & (1 << 10)) == 0) +# define isless(x, y) ((__unordered_cmp (x, y) & (3 << 10)) == (1 << 10)) +# define islessequal(x, y) ((__unordered_cmp (x, y) & (2 << 10)) == 0) +# define islessgreater(x, y) (((__unordered_cmp (x, y) + (1 << 10)) & (2 << 10)) != 0) +# define isunordered(x, y) ((__unordered_cmp (x, y) & (3 << 10)) == (3 << 10)) + +# else /* sparc64 */ + +# define __unordered_v9cmp(x, y, op, qop) \ + (__extension__ \ + ({ unsigned __r; \ + if (sizeof (x) == 4 && sizeof (y) == 4) \ + { \ + float __x = (x); float __y = (y); \ + __asm__ ("fcmps\t%%fcc3,%1,%2\n\tmov" op "\t%%fcc3,1,%0" \ + : "=r" (__r) : "f" (__x), "f" (__y), "0" (0) : "cc"); \ + } \ + else if (sizeof (x) <= 8 && sizeof (y) <= 8) \ + { \ + double __x = (x); double __y = (y); \ + __asm__ ("fcmpd\t%%fcc3,%1,%2\n\tmov" op "\t%%fcc3,1,%0" \ + : "=r" (__r) : "f" (__x), "f" (__y), "0" (0) : "cc"); \ + } \ + else \ + { \ + long double __x = (x); long double __y = (y); \ + extern int _Qp_cmp (const long double *a, const long double *b); \ + __r = qop; \ + } \ + __r; })) + +# define isgreater(x, y) __unordered_v9cmp(x, y, "g", _Qp_cmp (&__x, &__y) == 2) +# define isgreaterequal(x, y) __unordered_v9cmp(x, y, "ge", (_Qp_cmp (&__x, &__y) & 1) == 0) +# define isless(x, y) __unordered_v9cmp(x, y, "l", _Qp_cmp (&__x, &__y) == 1) +# define islessequal(x, y) __unordered_v9cmp(x, y, "le", (_Qp_cmp (&__x, &__y) & 2) == 0) +# define islessgreater(x, y) __unordered_v9cmp(x, y, "lg", ((_Qp_cmp (&__x, &__y) + 1) & 2) != 0) +# define isunordered(x, y) __unordered_v9cmp(x, y, "u", _Qp_cmp (&__x, &__y) == 3) + +# endif /* sparc64 */ + +#endif /* __USE_ISOC99 */ + +#if (!defined __NO_MATH_INLINES || defined __LIBC_INTERNAL_MATH_INLINES) && defined __OPTIMIZE__ + +# ifndef __extern_inline +# define __MATH_INLINE __inline +# else +# define __MATH_INLINE __extern_inline +# endif /* __cplusplus */ + +/* The gcc, version 2.7 or below, has problems with all this inlining + code. So disable it for this version of the compiler. */ +# if __GNUC_PREREQ (2, 8) + +# ifdef __USE_ISOC99 + +/* Test for negative number. Used in the signbit() macro. */ +__MATH_INLINE int +__NTH (__signbitf (float __x)) +{ + __extension__ union { float __f; int __i; } __u = { __f: __x }; + return __u.__i < 0; +} + +# if __WORDSIZE == 32 + +__MATH_INLINE int +__NTH (__signbit (double __x)) +{ + __extension__ union { double __d; int __i[2]; } __u = { __d: __x }; + return __u.__i[0] < 0; +} + +# ifndef __NO_LONG_DOUBLE_MATH +__MATH_INLINE int +__NTH (__signbitl (long double __x)) +{ + __extension__ union { long double __l; int __i[4]; } __u = { __l: __x }; + return __u.__i[0] < 0; +} +# else +__MATH_INLINE int +__NTH (__signbitl (long double __x)) +{ + return __signbit ((double)__x); +} +# endif + +# else /* sparc64 */ + +__MATH_INLINE int +__NTH (__signbit (double __x)) +{ + __extension__ union { double __d; long int __i; } __u = { __d: __x }; + return __u.__i < 0; +} + +__MATH_INLINE int +__NTH (__signbitl (long double __x)) +{ + __extension__ union { long double __l; long int __i[2]; } __u = { __l: __x }; + return __u.__i[0] < 0; +} + +# endif /* sparc64 */ + +# endif /* __USE_ISOC99 */ + +# if !defined __NO_MATH_INLINES && !__GNUC_PREREQ (3, 2) + +__MATH_INLINE double +__NTH (sqrt (double __x)) +{ + register double __r; + __asm ("fsqrtd %1,%0" : "=f" (__r) : "f" (__x)); + return __r; +} + +__MATH_INLINE float +__NTH (sqrtf (float __x)) +{ + register float __r; + __asm ("fsqrts %1,%0" : "=f" (__r) : "f" (__x)); + return __r; +} + +# if __WORDSIZE == 64 +__MATH_INLINE long double +__NTH (sqrtl (long double __x)) +{ + long double __r; + extern void _Qp_sqrt (long double *, const long double *); + _Qp_sqrt (&__r, &__x); + return __r; +} +# elif !defined __NO_LONG_DOUBLE_MATH +__MATH_INLINE long double +sqrtl (long double __x) __THROW +{ + extern long double _Q_sqrt (const long double); + return _Q_sqrt (__x); +} +# endif /* sparc64 */ + +# endif /* !__NO_MATH_INLINES && !GCC 3.2+ */ + +/* This code is used internally in the GNU libc. */ +# ifdef __LIBC_INTERNAL_MATH_INLINES +__MATH_INLINE double +__ieee754_sqrt (double __x) +{ + register double __r; + __asm ("fsqrtd %1,%0" : "=f" (__r) : "f" (__x)); + return __r; +} + +__MATH_INLINE float +__ieee754_sqrtf (float __x) +{ + register float __r; + __asm ("fsqrts %1,%0" : "=f" (__r) : "f" (__x)); + return __r; +} + +# if __WORDSIZE == 64 +__MATH_INLINE long double +__ieee754_sqrtl (long double __x) +{ + long double __r; + extern void _Qp_sqrt (long double *, const long double *); + _Qp_sqrt(&__r, &__x); + return __r; +} +# elif !defined __NO_LONG_DOUBLE_MATH +__MATH_INLINE long double +__ieee754_sqrtl (long double __x) +{ + extern long double _Q_sqrt (const long double); + return _Q_sqrt (__x); +} +# endif /* sparc64 */ +# endif /* __LIBC_INTERNAL_MATH_INLINES */ +# endif /* gcc 2.8+ */ + +# ifdef __USE_ISOC99 + +# ifndef __NO_MATH_INLINES + +__MATH_INLINE double __NTH (fdim (double __x, double __y)); +__MATH_INLINE double +__NTH (fdim (double __x, double __y)) +{ + return __x <= __y ? 0 : __x - __y; +} + +__MATH_INLINE float __NTH (fdimf (float __x, float __y)); +__MATH_INLINE float +__NTH (fdimf (float __x, float __y)) +{ + return __x <= __y ? 0 : __x - __y; +} + +# endif /* !__NO_MATH_INLINES */ +# endif /* __USE_ISOC99 */ +#endif /* !__NO_MATH_INLINES && __OPTIMIZE__ */ +#endif /* __GNUC__ */ diff --git a/REORG.TODO/sysdeps/sparc/fpu/fclrexcpt.c b/REORG.TODO/sysdeps/sparc/fpu/fclrexcpt.c new file mode 100644 index 0000000000..16ca6b64fc --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/fclrexcpt.c @@ -0,0 +1,43 @@ +/* Clear given exceptions in current floating-point environment. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> +#include <shlib-compat.h> + +int +__feclearexcept (int excepts) +{ + fenv_t tmp; + + __fenv_stfsr (tmp); + + tmp &= ~(excepts & FE_ALL_EXCEPT); + + __fenv_ldfsr (tmp); + + /* Success. */ + return 0; +} + +#if SHLIB_COMPAT (libm, GLIBC_2_1, GLIBC_2_2) +strong_alias (__feclearexcept, __old_feclearexcept) +compat_symbol (libm, __old_feclearexcept, feclearexcept, GLIBC_2_1); +#endif + +libm_hidden_ver (__feclearexcept, feclearexcept) +versioned_symbol (libm, __feclearexcept, feclearexcept, GLIBC_2_2); diff --git a/REORG.TODO/sysdeps/sparc/fpu/fedisblxcpt.c b/REORG.TODO/sysdeps/sparc/fpu/fedisblxcpt.c new file mode 100644 index 0000000000..74d1722093 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/fedisblxcpt.c @@ -0,0 +1,35 @@ +/* Disable floating-point exceptions. + Copyright (C) 2000-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jakub@redhat.com>, 2000. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +fedisableexcept (int excepts) +{ + fenv_t new_exc, old_exc; + + __fenv_stfsr (new_exc); + + old_exc = (new_exc >> 18) & FE_ALL_EXCEPT; + new_exc &= ~(((fenv_t)excepts & FE_ALL_EXCEPT) << 18); + + __fenv_ldfsr (new_exc); + + return old_exc; +} diff --git a/REORG.TODO/sysdeps/sparc/fpu/feenablxcpt.c b/REORG.TODO/sysdeps/sparc/fpu/feenablxcpt.c new file mode 100644 index 0000000000..64e2f04eaf --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/feenablxcpt.c @@ -0,0 +1,35 @@ +/* Enable floating-point exceptions. + Copyright (C) 2000-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jakub@redhat.com>, 2000. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +feenableexcept (int excepts) +{ + fenv_t new_exc, old_exc; + + __fenv_stfsr (new_exc); + + old_exc = (new_exc >> 18) & FE_ALL_EXCEPT; + new_exc |= (((fenv_t)excepts & FE_ALL_EXCEPT) << 18); + + __fenv_ldfsr (new_exc); + + return old_exc; +} diff --git a/REORG.TODO/sysdeps/sparc/fpu/fegetenv.c b/REORG.TODO/sysdeps/sparc/fpu/fegetenv.c new file mode 100644 index 0000000000..c497d2d72c --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/fegetenv.c @@ -0,0 +1,38 @@ +/* Store current floating-point environment. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> +#include <shlib-compat.h> + +int +__fegetenv (fenv_t *envp) +{ + __fenv_stfsr (*envp); + + /* Success. */ + return 0; +} + +#if SHLIB_COMPAT (libm, GLIBC_2_1, GLIBC_2_2) +strong_alias (__fegetenv, __old_fegetenv) +compat_symbol (libm, __old_fegetenv, fegetenv, GLIBC_2_1); +#endif + +libm_hidden_def (__fegetenv) +libm_hidden_ver (__fegetenv, fegetenv) +versioned_symbol (libm, __fegetenv, fegetenv, GLIBC_2_2); diff --git a/REORG.TODO/sysdeps/sparc/fpu/fegetexcept.c b/REORG.TODO/sysdeps/sparc/fpu/fegetexcept.c new file mode 100644 index 0000000000..77afc73e0f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/fegetexcept.c @@ -0,0 +1,29 @@ +/* Get enabled floating-point exceptions. + Copyright (C) 2000-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jakub@redhat.com>, 2000. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +fegetexcept (void) +{ + fenv_t exc; + __fenv_stfsr (exc); + + return (exc >> 18) & FE_ALL_EXCEPT; +} diff --git a/REORG.TODO/sysdeps/sparc/fpu/fegetmode.c b/REORG.TODO/sysdeps/sparc/fpu/fegetmode.c new file mode 100644 index 0000000000..53294dd542 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/fegetmode.c @@ -0,0 +1,26 @@ +/* Store current floating-point control modes. SPARC version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +fegetmode (femode_t *modep) +{ + __fenv_stfsr (*modep); + return 0; +} diff --git a/REORG.TODO/sysdeps/sparc/fpu/fegetround.c b/REORG.TODO/sysdeps/sparc/fpu/fegetround.c new file mode 100644 index 0000000000..d1225df652 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/fegetround.c @@ -0,0 +1,32 @@ +/* Return current rounding direction. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +__fegetround (void) +{ + fenv_t tmp; + + __fenv_stfsr (tmp); + + return tmp & __FE_ROUND_MASK; +} +libm_hidden_def (__fegetround) +weak_alias (__fegetround, fegetround) +libm_hidden_weak (fegetround) diff --git a/REORG.TODO/sysdeps/sparc/fpu/feholdexcpt.c b/REORG.TODO/sysdeps/sparc/fpu/feholdexcpt.c new file mode 100644 index 0000000000..8a712d892f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/feholdexcpt.c @@ -0,0 +1,37 @@ +/* Store current floating-point environment and clear exceptions. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +__feholdexcept (fenv_t *envp) +{ + fenv_t tmp; + + __fenv_stfsr (*envp); + + /* Set all exceptions to non-stop and clear all exceptions. */ + tmp = *envp & ~((0x1f << 23) | FE_ALL_EXCEPT); + + __fenv_ldfsr (tmp); + + return 0; +} +libm_hidden_def (__feholdexcept) +weak_alias (__feholdexcept, feholdexcept) +libm_hidden_weak (feholdexcept) diff --git a/REORG.TODO/sysdeps/sparc/fpu/fenv_private.h b/REORG.TODO/sysdeps/sparc/fpu/fenv_private.h new file mode 100644 index 0000000000..29b5d123cf --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/fenv_private.h @@ -0,0 +1,182 @@ +#ifndef FENV_PRIVATE_H +#define FENV_PRIVATE_H 1 + +#include <fenv.h> + +static __always_inline void +libc_feholdexcept (fenv_t *e) +{ + fenv_t etmp; + __fenv_stfsr(etmp); + *(e) = etmp; + etmp = etmp & ~((0x1f << 23) | FE_ALL_EXCEPT); + __fenv_ldfsr(etmp); +} + +static __always_inline void +libc_fesetround (int r) +{ + fenv_t etmp; + __fenv_stfsr(etmp); + etmp = (etmp & ~__FE_ROUND_MASK) | (r); + __fenv_ldfsr(etmp); +} + +static __always_inline void +libc_feholdexcept_setround (fenv_t *e, int r) +{ + fenv_t etmp; + __fenv_stfsr(etmp); + *(e) = etmp; + etmp = etmp & ~((0x1f << 23) | FE_ALL_EXCEPT); + etmp = (etmp & ~__FE_ROUND_MASK) | (r); + __fenv_ldfsr(etmp); +} + +static __always_inline int +libc_fetestexcept (int e) +{ + fenv_t etmp; + __fenv_stfsr(etmp); + return etmp & (e) & FE_ALL_EXCEPT; +} + +static __always_inline void +libc_fesetenv (fenv_t *e) +{ + __fenv_ldfsr(*e); +} + +static __always_inline int +libc_feupdateenv_test (fenv_t *e, int ex) +{ + fenv_t etmp; + + __fenv_stfsr(etmp); + etmp &= FE_ALL_EXCEPT; + + __fenv_ldfsr(*e); + + __feraiseexcept (etmp); + + return etmp & ex; +} + +static __always_inline void +libc_feupdateenv (fenv_t *e) +{ + libc_feupdateenv_test (e, 0); +} + +static __always_inline void +libc_feholdsetround (fenv_t *e, int r) +{ + fenv_t etmp; + __fenv_stfsr(etmp); + *(e) = etmp; + etmp = (etmp & ~__FE_ROUND_MASK) | (r); + __fenv_ldfsr(etmp); +} + +static __always_inline void +libc_feresetround (fenv_t *e) +{ + fenv_t etmp; + __fenv_stfsr(etmp); + etmp = (etmp & ~__FE_ROUND_MASK) | (*e & __FE_ROUND_MASK); + __fenv_ldfsr(etmp); +} + +#define libc_feholdexceptf libc_feholdexcept +#define libc_fesetroundf libc_fesetround +#define libc_feholdexcept_setroundf libc_feholdexcept_setround +#define libc_fetestexceptf libc_fetestexcept +#define libc_fesetenvf libc_fesetenv +#define libc_feupdateenv_testf libc_feupdateenv_test +#define libc_feupdateenvf libc_feupdateenv +#define libc_feholdsetroundf libc_feholdsetround +#define libc_feresetroundf libc_feresetround +#define libc_feholdexcept libc_feholdexcept +#define libc_fesetround libc_fesetround +#define libc_feholdexcept_setround libc_feholdexcept_setround +#define libc_fetestexcept libc_fetestexcept +#define libc_fesetenv libc_fesetenv +#define libc_feupdateenv_test libc_feupdateenv_test +#define libc_feupdateenv libc_feupdateenv +#define libc_feholdsetround libc_feholdsetround +#define libc_feresetround libc_feresetround +#define libc_feholdexceptl libc_feholdexcept +#define libc_fesetroundl libc_fesetround +#define libc_feholdexcept_setroundl libc_feholdexcept_setround +#define libc_fetestexceptl libc_fetestexcept +#define libc_fesetenvl libc_fesetenv +#define libc_feupdateenv_testl libc_feupdateenv_test +#define libc_feupdateenvl libc_feupdateenv +#define libc_feholdsetroundl libc_feholdsetround +#define libc_feresetroundl libc_feresetround + +/* We have support for rounding mode context. */ +#define HAVE_RM_CTX 1 + +static __always_inline void +libc_feholdexcept_setround_sparc_ctx (struct rm_ctx *ctx, int round) +{ + fenv_t new; + + __fenv_stfsr(ctx->env); + new = ctx->env & ~((0x1f << 23) | FE_ALL_EXCEPT); + new = (new & ~__FE_ROUND_MASK) | round; + if (__glibc_unlikely (new != ctx->env)) + { + __fenv_ldfsr(new); + ctx->updated_status = true; + } + else + ctx->updated_status = false; +} + +static __always_inline void +libc_fesetenv_sparc_ctx (struct rm_ctx *ctx) +{ + libc_fesetenv(&ctx->env); +} + +static __always_inline void +libc_feupdateenv_sparc_ctx (struct rm_ctx *ctx) +{ + if (__glibc_unlikely (ctx->updated_status)) + libc_feupdateenv_test (&ctx->env, 0); +} + +static __always_inline void +libc_feholdsetround_sparc_ctx (struct rm_ctx *ctx, int round) +{ + fenv_t new; + + __fenv_stfsr(ctx->env); + new = (ctx->env & ~__FE_ROUND_MASK) | round; + if (__glibc_unlikely (new != ctx->env)) + { + __fenv_ldfsr(new); + ctx->updated_status = true; + } + else + ctx->updated_status = false; +} +#define libc_feholdexcept_setround_ctx libc_feholdexcept_setround_sparc_ctx +#define libc_feholdexcept_setroundf_ctx libc_feholdexcept_setround_sparc_ctx +#define libc_feholdexcept_setroundl_ctx libc_feholdexcept_setround_sparc_ctx +#define libc_fesetenv_ctx libc_fesetenv_sparc_ctx +#define libc_fesetenvf_ctx libc_fesetenv_sparc_ctx +#define libc_fesetenvl_ctx libc_fesetenv_sparc_ctx +#define libc_feupdateenv_ctx libc_feupdateenv_sparc_ctx +#define libc_feupdateenvf_ctx libc_feupdateenv_sparc_ctx +#define libc_feupdateenvl_ctx libc_feupdateenv_sparc_ctx +#define libc_feresetround_ctx libc_feupdateenv_sparc_ctx +#define libc_feresetroundf_ctx libc_feupdateenv_sparc_ctx +#define libc_feresetroundl_ctx libc_feupdateenv_sparc_ctx +#define libc_feholdsetround_ctx libc_feholdsetround_sparc_ctx +#define libc_feholdsetroundf_ctx libc_feholdsetround_sparc_ctx +#define libc_feholdsetroundl_ctx libc_feholdsetround_sparc_ctx + +#endif /* FENV_PRIVATE_H */ diff --git a/REORG.TODO/sysdeps/sparc/fpu/fesetenv.c b/REORG.TODO/sysdeps/sparc/fpu/fesetenv.c new file mode 100644 index 0000000000..22b80e22ea --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/fesetenv.c @@ -0,0 +1,55 @@ +/* Install given floating-point environment. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> +#include <shlib-compat.h> + +int +__fesetenv (const fenv_t *envp) +{ + fenv_t dummy; + + /* Put these constants in memory explicitly, so as to cope with a + -fPIC bug as of gcc 970624. Making them automatic is quicker + than loading up the pic register in this instance. */ + + if (envp == FE_DFL_ENV) + { + dummy = 0; + envp = &dummy; + } + else if (envp == FE_NOMASK_ENV) + { + dummy = 0x1f << 23; + envp = &dummy; + } + + __fenv_ldfsr (*envp); + + /* Success. */ + return 0; +} + +#if SHLIB_COMPAT (libm, GLIBC_2_1, GLIBC_2_2) +strong_alias (__fesetenv, __old_fesetenv) +compat_symbol (libm, __old_fesetenv, fesetenv, GLIBC_2_1); +#endif + +libm_hidden_def (__fesetenv) +libm_hidden_ver (__fesetenv, fesetenv) +versioned_symbol (libm, __fesetenv, fesetenv, GLIBC_2_2); diff --git a/REORG.TODO/sysdeps/sparc/fpu/fesetexcept.c b/REORG.TODO/sysdeps/sparc/fpu/fesetexcept.c new file mode 100644 index 0000000000..42ff865c07 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/fesetexcept.c @@ -0,0 +1,31 @@ +/* Set given exception flags. SPARC version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +fesetexcept (int excepts) +{ + fenv_t tmp; + + __fenv_stfsr (tmp); + tmp |= excepts & FE_ALL_EXCEPT; + __fenv_ldfsr (tmp); + + return 0; +} diff --git a/REORG.TODO/sysdeps/sparc/fpu/fesetmode.c b/REORG.TODO/sysdeps/sparc/fpu/fesetmode.c new file mode 100644 index 0000000000..c678c8b8d9 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/fesetmode.c @@ -0,0 +1,38 @@ +/* Install given floating-point control modes. SPARC version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> +#include <fpu_control.h> + +#define FPU_CONTROL_BITS 0xcfc00000UL + +int +fesetmode (const femode_t *modep) +{ + femode_t fsr; + + __fenv_stfsr (fsr); + fsr &= ~FPU_CONTROL_BITS; + if (modep == FE_DFL_MODE) + fsr |= _FPU_DEFAULT; + else + fsr |= *modep & FPU_CONTROL_BITS; + __fenv_ldfsr (fsr); + + return 0; +} diff --git a/REORG.TODO/sysdeps/sparc/fpu/fesetround.c b/REORG.TODO/sysdeps/sparc/fpu/fesetround.c new file mode 100644 index 0000000000..e2a528a4c5 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/fesetround.c @@ -0,0 +1,39 @@ +/* Set current rounding direction. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +__fesetround (int round) +{ + fenv_t tmp; + + if ((round & ~__FE_ROUND_MASK) != 0) + /* ROUND is no valid rounding mode. */ + return 1; + + __fenv_stfsr (tmp); + tmp &= ~__FE_ROUND_MASK; + tmp |= round; + __fenv_ldfsr (tmp); + + return 0; +} +libm_hidden_def (__fesetround) +weak_alias (__fesetround, fesetround) +libm_hidden_weak (fesetround) diff --git a/REORG.TODO/sysdeps/sparc/fpu/feupdateenv.c b/REORG.TODO/sysdeps/sparc/fpu/feupdateenv.c new file mode 100644 index 0000000000..08615640d7 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/feupdateenv.c @@ -0,0 +1,50 @@ +/* Install given floating-point environment and raise exceptions. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> +#include <shlib-compat.h> + +int +__feupdateenv (const fenv_t *envp) +{ + fexcept_t tmp; + + /* Save current exceptions. */ + __fenv_stfsr (tmp); + tmp &= FE_ALL_EXCEPT; + + /* Install new environment. */ + __fesetenv (envp); + + /* Raise the safed exception. Incidently for us the implementation + defined format of the values in objects of type fexcept_t is the + same as the ones specified using the FE_* constants. */ + __feraiseexcept ((int) tmp); + + /* Success. */ + return 0; +} + +#if SHLIB_COMPAT (libm, GLIBC_2_1, GLIBC_2_2) +strong_alias (__feupdateenv, __old_feupdateenv) +compat_symbol (libm, __old_feupdateenv, feupdateenv, GLIBC_2_1); +#endif + +libm_hidden_def (__feupdateenv) +libm_hidden_ver (__feupdateenv, feupdateenv) +versioned_symbol (libm, __feupdateenv, feupdateenv, GLIBC_2_2); diff --git a/REORG.TODO/sysdeps/sparc/fpu/fgetexcptflg.c b/REORG.TODO/sysdeps/sparc/fpu/fgetexcptflg.c new file mode 100644 index 0000000000..ab05a3caf8 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/fgetexcptflg.c @@ -0,0 +1,41 @@ +/* Store current representation for exceptions. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> +#include <shlib-compat.h> + +int +__fegetexceptflag (fexcept_t *flagp, int excepts) +{ + fexcept_t tmp; + + /* Get the current exceptions. */ + __fenv_stfsr (tmp); + + *flagp = tmp & excepts & FE_ALL_EXCEPT; + + /* Success. */ + return 0; +} + +#if SHLIB_COMPAT (libm, GLIBC_2_1, GLIBC_2_2) +strong_alias (__fegetexceptflag, __old_fegetexceptflag) +compat_symbol (libm, __old_fegetexceptflag, fegetexceptflag, GLIBC_2_1); +#endif + +versioned_symbol (libm, __fegetexceptflag, fegetexceptflag, GLIBC_2_2); diff --git a/REORG.TODO/sysdeps/sparc/fpu/fpu_control.h b/REORG.TODO/sysdeps/sparc/fpu/fpu_control.h new file mode 100644 index 0000000000..77acde9253 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/fpu_control.h @@ -0,0 +1,72 @@ +/* FPU control word bits. SPARC version. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Miguel de Icaza + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _FPU_CONTROL_H +#define _FPU_CONTROL_H 1 + + +#include <features.h> +#include <bits/wordsize.h> + +/* masking of interrupts */ +#define _FPU_MASK_IM 0x08000000 +#define _FPU_MASK_OM 0x04000000 +#define _FPU_MASK_UM 0x02000000 +#define _FPU_MASK_ZM 0x01000000 +#define _FPU_MASK_PM 0x00800000 + +/* precision control */ +#define _FPU_EXTENDED 0x00000000 /* RECOMMENDED */ +#define _FPU_DOUBLE 0x20000000 +#define _FPU_80BIT 0x30000000 +#define _FPU_SINGLE 0x10000000 /* DO NOT USE */ + +/* rounding control / Sparc */ +#define _FPU_RC_DOWN 0xc0000000 +#define _FPU_RC_UP 0x80000000 +#define _FPU_RC_ZERO 0x40000000 +#define _FPU_RC_NEAREST 0x0 /* RECOMMENDED */ + +#define _FPU_RESERVED 0x30300000 /* Reserved bits in cw */ + + +/* Now two recommended cw */ + +/* Linux and IEEE default: + - extended precision + - rounding to nearest + - no exceptions */ +#define _FPU_DEFAULT 0x0 +#define _FPU_IEEE 0x0 + +/* Type of the control word. */ +typedef unsigned long int fpu_control_t; + +#if __WORDSIZE == 64 +# define _FPU_GETCW(cw) __asm__ __volatile__ ("stx %%fsr,%0" : "=m" (*&cw)) +# define _FPU_SETCW(cw) __asm__ __volatile__ ("ldx %0,%%fsr" : : "m" (*&cw)) +#else +# define _FPU_GETCW(cw) __asm__ __volatile__ ("st %%fsr,%0" : "=m" (*&cw)) +# define _FPU_SETCW(cw) __asm__ __volatile__ ("ld %0,%%fsr" : : "m" (*&cw)) +#endif + +/* Default control word set at startup. */ +extern fpu_control_t __fpu_control; + +#endif /* fpu_control.h */ diff --git a/REORG.TODO/sysdeps/sparc/fpu/fraiseexcpt.c b/REORG.TODO/sysdeps/sparc/fpu/fraiseexcpt.c new file mode 100644 index 0000000000..954166ed64 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/fraiseexcpt.c @@ -0,0 +1,91 @@ +/* Raise given exceptions. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> +#include <float.h> +#include <math.h> +#include <shlib-compat.h> + +int +__feraiseexcept (int excepts) +{ + static const struct { + double zero, one, max, min, pi; + } c = { + 0.0, 1.0, DBL_MAX, DBL_MIN, M_PI + }; + double d; + + /* Raise exceptions represented by EXPECTS. But we must raise only + one signal at a time. It is important the if the overflow/underflow + exception and the inexact exception are given at the same time, + the overflow/underflow exception follows the inexact exception. */ + + /* First: invalid exception. */ + if ((FE_INVALID & excepts) != 0) + { + /* One example of an invalid operation is 0/0. */ + __asm ("" : "=e" (d) : "0" (c.zero)); + d /= c.zero; + __asm __volatile ("" : : "e" (d)); + } + + /* Next: division by zero. */ + if ((FE_DIVBYZERO & excepts) != 0) + { + __asm ("" : "=e" (d) : "0" (c.one)); + d /= c.zero; + __asm __volatile ("" : : "e" (d)); + } + + /* Next: overflow. */ + if ((FE_OVERFLOW & excepts) != 0) + { + __asm ("" : "=e" (d) : "0" (c.max)); + d *= d; + __asm __volatile ("" : : "e" (d)); + } + + /* Next: underflow. */ + if ((FE_UNDERFLOW & excepts) != 0) + { + __asm ("" : "=e" (d) : "0" (c.min)); + d *= d; + __asm __volatile ("" : : "e" (d)); + } + + /* Last: inexact. */ + if ((FE_INEXACT & excepts) != 0) + { + __asm ("" : "=e" (d) : "0" (c.one)); + d /= c.pi; + __asm __volatile ("" : : "e" (d)); + } + + /* Success. */ + return 0; +} + +#if SHLIB_COMPAT (libm, GLIBC_2_1, GLIBC_2_2) +strong_alias (__feraiseexcept, __old_feraiseexcept) +compat_symbol (libm, __old_feraiseexcept, feraiseexcept, GLIBC_2_1); +#endif + +libm_hidden_def (__feraiseexcept) +libm_hidden_ver (__feraiseexcept, feraiseexcept) +versioned_symbol (libm, __feraiseexcept, feraiseexcept, GLIBC_2_2); diff --git a/REORG.TODO/sysdeps/sparc/fpu/fsetexcptflg.c b/REORG.TODO/sysdeps/sparc/fpu/fsetexcptflg.c new file mode 100644 index 0000000000..3546fbf996 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/fsetexcptflg.c @@ -0,0 +1,44 @@ +/* Set floating-point environment exception handling. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> +#include <math.h> +#include <shlib-compat.h> + +int +__fesetexceptflag (const fexcept_t *flagp, int excepts) +{ + fenv_t tmp; + + __fenv_stfsr (tmp); + + tmp &= ~(excepts & FE_ALL_EXCEPT); + tmp |= *flagp & excepts & FE_ALL_EXCEPT; + + __fenv_ldfsr (tmp); + + /* Success. */ + return 0; +} + +#if SHLIB_COMPAT (libm, GLIBC_2_1, GLIBC_2_2) +strong_alias (__fesetexceptflag, __old_fesetexceptflag) +compat_symbol (libm, __old_fesetexceptflag, fesetexceptflag, GLIBC_2_1); +#endif + +versioned_symbol (libm, __fesetexceptflag, fesetexceptflag, GLIBC_2_2); diff --git a/REORG.TODO/sysdeps/sparc/fpu/ftestexcept.c b/REORG.TODO/sysdeps/sparc/fpu/ftestexcept.c new file mode 100644 index 0000000000..f2b51f4b12 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/ftestexcept.c @@ -0,0 +1,30 @@ +/* Test exception in current environment. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fenv.h> + +int +fetestexcept (int excepts) +{ + fenv_t tmp; + + __fenv_stfsr (tmp); + + return tmp & excepts & FE_ALL_EXCEPT; +} +libm_hidden_def (fetestexcept) diff --git a/REORG.TODO/sysdeps/sparc/fpu/libm-test-ulps b/REORG.TODO/sysdeps/sparc/fpu/libm-test-ulps new file mode 100644 index 0000000000..cf6a2929d3 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/libm-test-ulps @@ -0,0 +1,2262 @@ +# Begin of automatic generation + +# Maximal error of functions: +Function: "acos": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "acos_downward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "acos_towardzero": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "acos_upward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "acosh": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "acosh_downward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "acosh_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "acosh_upward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "asin": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "asin_downward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "asin_towardzero": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "asin_upward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "asinh": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: "asinh_downward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 4 +ldouble: 4 + +Function: "asinh_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "asinh_upward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 4 +ldouble: 4 + +Function: "atan": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "atan2": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "atan2_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "atan2_towardzero": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "atan2_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "atan_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "atan_towardzero": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "atan_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "atanh": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "atanh_downward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 4 +ldouble: 4 + +Function: "atanh_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "atanh_upward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 4 +ldouble: 4 + +Function: "cabs": +double: 1 +idouble: 1 +ildouble: 1 +ldouble: 1 + +Function: "cabs_downward": +double: 1 +idouble: 1 +ildouble: 1 +ldouble: 1 + +Function: "cabs_towardzero": +double: 1 +idouble: 1 +ildouble: 1 +ldouble: 1 + +Function: "cabs_upward": +double: 1 +idouble: 1 +ildouble: 1 +ldouble: 1 + +Function: Real part of "cacos": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "cacos": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "cacos_downward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "cacos_downward": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: Real part of "cacos_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "cacos_towardzero": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: Real part of "cacos_upward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "cacos_upward": +double: 4 +float: 4 +idouble: 4 +ifloat: 4 +ildouble: 5 +ldouble: 5 + +Function: Real part of "cacosh": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "cacosh": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "cacosh_downward": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "cacosh_downward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "cacosh_towardzero": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "cacosh_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "cacosh_upward": +double: 4 +float: 4 +idouble: 4 +ifloat: 4 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "cacosh_upward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "carg": +float: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "carg_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "carg_towardzero": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "carg_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "casin": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "casin": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "casin_downward": +double: 3 +float: 1 +idouble: 3 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "casin_downward": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: Real part of "casin_towardzero": +double: 3 +float: 1 +idouble: 3 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "casin_towardzero": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: Real part of "casin_upward": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "casin_upward": +double: 4 +float: 4 +idouble: 4 +ifloat: 4 +ildouble: 5 +ldouble: 5 + +Function: Real part of "casinh": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "casinh": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: Real part of "casinh_downward": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "casinh_downward": +double: 3 +float: 1 +idouble: 3 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: Real part of "casinh_towardzero": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "casinh_towardzero": +double: 3 +float: 1 +idouble: 3 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: Real part of "casinh_upward": +double: 4 +float: 4 +idouble: 4 +ifloat: 4 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "casinh_upward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Real part of "catan": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "catan": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Real part of "catan_downward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "catan_downward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Real part of "catan_towardzero": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "catan_towardzero": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: Real part of "catan_upward": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "catan_upward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "catanh": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "catanh": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Real part of "catanh_downward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "catanh_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "catanh_towardzero": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "catanh_towardzero": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "catanh_upward": +double: 4 +float: 3 +idouble: 4 +ifloat: 3 +ildouble: 4 +ldouble: 4 + +Function: Imaginary part of "catanh_upward": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "cbrt": +double: 3 +float: 1 +idouble: 3 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "cbrt_downward": +double: 4 +float: 1 +idouble: 4 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "cbrt_towardzero": +double: 3 +float: 1 +idouble: 3 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "cbrt_upward": +double: 5 +float: 1 +idouble: 5 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Real part of "ccos": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "ccos": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Real part of "ccos_downward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "ccos_downward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 2 +ldouble: 2 + +Function: Real part of "ccos_towardzero": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "ccos_towardzero": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 2 +ldouble: 2 + +Function: Real part of "ccos_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "ccos_upward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "ccosh": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "ccosh": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Real part of "ccosh_downward": +double: 1 +float: 3 +idouble: 1 +ifloat: 3 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "ccosh_downward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 2 +ldouble: 2 + +Function: Real part of "ccosh_towardzero": +double: 1 +float: 3 +idouble: 1 +ifloat: 3 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "ccosh_towardzero": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 2 +ldouble: 2 + +Function: Real part of "ccosh_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "ccosh_upward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "cexp": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "cexp": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: Real part of "cexp_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "cexp_downward": +double: 1 +float: 3 +idouble: 1 +ifloat: 3 +ildouble: 2 +ldouble: 2 + +Function: Real part of "cexp_towardzero": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "cexp_towardzero": +double: 1 +float: 3 +idouble: 1 +ifloat: 3 +ildouble: 2 +ldouble: 2 + +Function: Real part of "cexp_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "cexp_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Real part of "clog": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 4 +ldouble: 4 + +Function: Imaginary part of "clog": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Real part of "clog10": +double: 3 +float: 4 +idouble: 3 +ifloat: 4 +ildouble: 4 +ldouble: 4 + +Function: Imaginary part of "clog10": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "clog10_downward": +double: 6 +float: 6 +idouble: 6 +ifloat: 6 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "clog10_downward": +double: 2 +float: 4 +idouble: 2 +ifloat: 4 +ildouble: 3 +ldouble: 3 + +Function: Real part of "clog10_towardzero": +double: 5 +float: 5 +idouble: 5 +ifloat: 5 +ildouble: 6 +ldouble: 6 + +Function: Imaginary part of "clog10_towardzero": +double: 2 +float: 4 +idouble: 2 +ifloat: 4 +ildouble: 3 +ldouble: 3 + +Function: Real part of "clog10_upward": +double: 8 +float: 5 +idouble: 8 +ifloat: 5 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "clog10_upward": +double: 2 +float: 4 +idouble: 2 +ifloat: 4 +ildouble: 3 +ldouble: 3 + +Function: Real part of "clog_downward": +double: 7 +float: 5 +idouble: 7 +ifloat: 5 +ildouble: 6 +ldouble: 6 + +Function: Imaginary part of "clog_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "clog_towardzero": +double: 7 +float: 5 +idouble: 7 +ifloat: 5 +ildouble: 6 +ldouble: 6 + +Function: Imaginary part of "clog_towardzero": +double: 1 +float: 3 +idouble: 1 +ifloat: 3 +ildouble: 2 +ldouble: 2 + +Function: Real part of "clog_upward": +double: 8 +float: 5 +idouble: 8 +ifloat: 5 +ildouble: 6 +ldouble: 6 + +Function: Imaginary part of "clog_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "cos": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "cos_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "cos_towardzero": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "cos_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "cosh": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "cosh_downward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 2 + +Function: "cosh_towardzero": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 2 + +Function: "cosh_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 3 + +Function: Real part of "cpow": +double: 2 +float: 4 +idouble: 2 +ifloat: 4 +ildouble: 4 +ldouble: 4 + +Function: Imaginary part of "cpow": +float: 2 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: Real part of "cpow_downward": +double: 4 +float: 8 +idouble: 4 +ifloat: 8 +ildouble: 6 +ldouble: 6 + +Function: Imaginary part of "cpow_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "cpow_towardzero": +double: 4 +float: 8 +idouble: 4 +ifloat: 8 +ildouble: 6 +ldouble: 6 + +Function: Imaginary part of "cpow_towardzero": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "cpow_upward": +double: 4 +float: 1 +idouble: 4 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "cpow_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "csin": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "csin": +ildouble: 1 +ldouble: 1 + +Function: Real part of "csin_downward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "csin_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Real part of "csin_towardzero": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "csin_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Real part of "csin_upward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "csin_upward": +double: 1 +float: 3 +idouble: 1 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "csinh": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Imaginary part of "csinh": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: Real part of "csinh_downward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "csinh_downward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 2 +ldouble: 2 + +Function: Real part of "csinh_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "csinh_towardzero": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "csinh_upward": +double: 1 +float: 3 +idouble: 1 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "csinh_upward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 2 +ldouble: 2 + +Function: Real part of "csqrt": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Imaginary part of "csqrt": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: Real part of "csqrt_downward": +double: 5 +float: 4 +idouble: 5 +ifloat: 4 +ildouble: 4 +ldouble: 4 + +Function: Imaginary part of "csqrt_downward": +double: 4 +float: 3 +idouble: 4 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "csqrt_towardzero": +double: 4 +float: 3 +idouble: 4 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "csqrt_towardzero": +double: 4 +float: 3 +idouble: 4 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "csqrt_upward": +double: 5 +float: 4 +idouble: 5 +ifloat: 4 +ildouble: 4 +ldouble: 4 + +Function: Imaginary part of "csqrt_upward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "ctan": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "ctan": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: Real part of "ctan_downward": +double: 6 +float: 5 +idouble: 6 +ifloat: 5 +ildouble: 4 +ldouble: 4 + +Function: Imaginary part of "ctan_downward": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 5 +ldouble: 5 + +Function: Real part of "ctan_towardzero": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 4 +ldouble: 4 + +Function: Imaginary part of "ctan_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 5 +ldouble: 5 + +Function: Real part of "ctan_upward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "ctan_upward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: Real part of "ctanh": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: Imaginary part of "ctanh": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: Real part of "ctanh_downward": +double: 4 +float: 1 +idouble: 4 +ifloat: 1 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "ctanh_downward": +double: 6 +float: 5 +idouble: 6 +ifloat: 5 +ildouble: 4 +ldouble: 4 + +Function: Real part of "ctanh_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "ctanh_towardzero": +double: 5 +float: 3 +idouble: 5 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: Real part of "ctanh_upward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: Imaginary part of "ctanh_upward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: "erf": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "erf_downward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "erf_towardzero": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "erf_upward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "erfc": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "erfc_downward": +double: 5 +float: 6 +idouble: 5 +ifloat: 6 +ildouble: 5 +ldouble: 5 + +Function: "erfc_towardzero": +double: 3 +float: 4 +idouble: 3 +ifloat: 4 +ildouble: 4 +ldouble: 4 + +Function: "erfc_upward": +double: 5 +float: 6 +idouble: 5 +ifloat: 6 +ildouble: 5 +ldouble: 5 + +Function: "exp": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "exp10": +double: 2 +idouble: 2 +ildouble: 2 +ldouble: 2 + +Function: "exp10_downward": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: "exp10_towardzero": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: "exp10_upward": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: "exp2": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "exp2_downward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "exp2_towardzero": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "exp2_upward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "exp_downward": +double: 1 +idouble: 1 + +Function: "exp_towardzero": +double: 1 +idouble: 1 + +Function: "exp_upward": +double: 1 +idouble: 1 + +Function: "expm1": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "expm1_downward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "expm1_towardzero": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: "expm1_upward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: "gamma": +double: 4 +float: 4 +idouble: 4 +ifloat: 4 +ildouble: 5 +ldouble: 5 + +Function: "gamma_downward": +double: 5 +float: 4 +idouble: 5 +ifloat: 4 +ildouble: 8 +ldouble: 8 + +Function: "gamma_towardzero": +double: 5 +float: 4 +idouble: 5 +ifloat: 4 +ildouble: 5 +ldouble: 5 + +Function: "gamma_upward": +double: 5 +float: 5 +idouble: 5 +ifloat: 5 +ildouble: 8 +ldouble: 8 + +Function: "hypot": +double: 1 +idouble: 1 +ildouble: 1 +ldouble: 1 + +Function: "hypot_downward": +double: 1 +idouble: 1 +ildouble: 1 +ldouble: 1 + +Function: "hypot_towardzero": +double: 1 +idouble: 1 +ildouble: 1 +ldouble: 1 + +Function: "hypot_upward": +double: 1 +idouble: 1 +ildouble: 1 +ldouble: 1 + +Function: "j0": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "j0_downward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 4 +ldouble: 4 + +Function: "j0_towardzero": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "j0_upward": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 5 +ldouble: 5 + +Function: "j1": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: "j1_downward": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: "j1_towardzero": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: "j1_upward": +double: 3 +float: 5 +idouble: 3 +ifloat: 5 +ildouble: 3 +ldouble: 3 + +Function: "jn": +double: 4 +float: 4 +idouble: 4 +ifloat: 4 +ildouble: 7 +ldouble: 7 + +Function: "jn_downward": +double: 5 +float: 5 +idouble: 5 +ifloat: 5 +ildouble: 8 +ldouble: 8 + +Function: "jn_towardzero": +double: 5 +float: 5 +idouble: 5 +ifloat: 5 +ildouble: 8 +ldouble: 8 + +Function: "jn_upward": +double: 5 +float: 5 +idouble: 5 +ifloat: 5 +ildouble: 7 +ldouble: 7 + +Function: "lgamma": +double: 4 +float: 4 +idouble: 4 +ifloat: 4 +ildouble: 5 +ldouble: 5 + +Function: "lgamma_downward": +double: 5 +float: 4 +idouble: 5 +ifloat: 4 +ildouble: 8 +ldouble: 8 + +Function: "lgamma_towardzero": +double: 5 +float: 4 +idouble: 5 +ifloat: 4 +ildouble: 5 +ldouble: 5 + +Function: "lgamma_upward": +double: 5 +float: 5 +idouble: 5 +ifloat: 5 +ildouble: 8 +ldouble: 8 + +Function: "log": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "log10": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "log10_downward": +double: 2 +float: 3 +idouble: 2 +ifloat: 3 +ildouble: 1 +ldouble: 1 + +Function: "log10_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "log10_upward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "log1p": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "log1p_downward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "log1p_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "log1p_upward": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "log2": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "log2_downward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: "log2_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "log2_upward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 1 +ldouble: 1 + +Function: "log_downward": +float: 2 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "log_towardzero": +float: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "log_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "pow": +float: 3 +ifloat: 3 +ildouble: 2 +ldouble: 2 + +Function: "pow10": +double: 2 +idouble: 2 +ildouble: 2 +ldouble: 2 + +Function: "pow10_downward": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: "pow10_towardzero": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: "pow10_upward": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: "pow_downward": +double: 1 +float: 3 +idouble: 1 +ifloat: 3 +ildouble: 2 +ldouble: 2 + +Function: "pow_towardzero": +double: 1 +float: 4 +idouble: 1 +ifloat: 4 +ildouble: 2 +ldouble: 2 + +Function: "pow_upward": +double: 1 +float: 4 +idouble: 1 +ifloat: 4 +ildouble: 2 +ldouble: 2 + +Function: "sin": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "sin_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "sin_towardzero": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "sin_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "sincos": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "sincos_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "sincos_towardzero": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 2 +ldouble: 2 + +Function: "sincos_upward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "sinh": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "sinh_downward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: "sinh_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "sinh_upward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 4 +ldouble: 4 + +Function: "tan": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "tan_downward": +double: 1 +float: 2 +idouble: 1 +ifloat: 2 +ildouble: 1 +ldouble: 1 + +Function: "tan_towardzero": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "tan_upward": +double: 1 +float: 1 +idouble: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 + +Function: "tanh": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "tanh_downward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 4 +ldouble: 4 + +Function: "tanh_towardzero": +double: 2 +float: 2 +idouble: 2 +ifloat: 2 +ildouble: 3 +ldouble: 3 + +Function: "tanh_upward": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: "tgamma": +double: 5 +float: 5 +idouble: 5 +ifloat: 5 +ildouble: 4 +ldouble: 4 + +Function: "tgamma_downward": +double: 5 +float: 5 +idouble: 5 +ifloat: 5 +ildouble: 5 +ldouble: 5 + +Function: "tgamma_towardzero": +double: 5 +float: 5 +idouble: 5 +ifloat: 5 +ildouble: 5 +ldouble: 5 + +Function: "tgamma_upward": +double: 4 +float: 5 +idouble: 4 +ifloat: 5 +ildouble: 4 +ldouble: 4 + +Function: "y0": +double: 2 +float: 1 +idouble: 2 +ifloat: 1 +ildouble: 3 +ldouble: 3 + +Function: "y0_downward": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: "y0_towardzero": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 3 +ldouble: 3 + +Function: "y0_upward": +double: 3 +float: 4 +idouble: 3 +ifloat: 4 +ildouble: 3 +ldouble: 3 + +Function: "y1": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "y1_downward": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 4 +ldouble: 4 + +Function: "y1_towardzero": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 2 +ldouble: 2 + +Function: "y1_upward": +double: 7 +float: 2 +idouble: 7 +ifloat: 2 +ildouble: 5 +ldouble: 5 + +Function: "yn": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 5 +ldouble: 5 + +Function: "yn_downward": +double: 3 +float: 2 +idouble: 3 +ifloat: 2 +ildouble: 5 +ldouble: 5 + +Function: "yn_towardzero": +double: 3 +float: 3 +idouble: 3 +ifloat: 3 +ildouble: 5 +ldouble: 5 + +Function: "yn_upward": +double: 4 +float: 4 +idouble: 4 +ifloat: 4 +ildouble: 5 +ldouble: 5 + +# end of automatic generation diff --git a/REORG.TODO/sysdeps/sparc/fpu/libm-test-ulps-name b/REORG.TODO/sysdeps/sparc/fpu/libm-test-ulps-name new file mode 100644 index 0000000000..71240543c4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/libm-test-ulps-name @@ -0,0 +1 @@ +Sparc diff --git a/REORG.TODO/sysdeps/sparc/fpu/math_private.h b/REORG.TODO/sysdeps/sparc/fpu/math_private.h new file mode 100644 index 0000000000..27946cec7b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/fpu/math_private.h @@ -0,0 +1,7 @@ +#ifndef SPARC_MATH_PRIVATE_H +#define SPARC_MATH_PRIVATE_H 1 + +#include "fenv_private.h" +#include_next <math_private.h> + +#endif /* SPARC_MATH_PRIVATE_H */ diff --git a/REORG.TODO/sysdeps/sparc/gccframe.h b/REORG.TODO/sysdeps/sparc/gccframe.h new file mode 100644 index 0000000000..30228602e2 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/gccframe.h @@ -0,0 +1,21 @@ +/* Definition of object in frame unwind info. sparc version. + Copyright (C) 2001-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#define FIRST_PSEUDO_REGISTER 101 + +#include <sysdeps/generic/gccframe.h> diff --git a/REORG.TODO/sysdeps/sparc/ldsodefs.h b/REORG.TODO/sysdeps/sparc/ldsodefs.h new file mode 100644 index 0000000000..ad6c3ffe74 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/ldsodefs.h @@ -0,0 +1,55 @@ +/* Run-time dynamic linker data structures for loaded ELF shared objects. + Copyright (C) 1995-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _SPARC_LDSODEFS_H +#define _SPARC_LDSODEFS_H 1 + +#include <elf.h> + +struct La_sparc32_regs; +struct La_sparc32_retval; +struct La_sparc64_regs; +struct La_sparc64_retval; + +#define ARCH_PLTENTER_MEMBERS \ + Elf32_Addr (*sparc32_gnu_pltenter) (Elf32_Sym *, unsigned int, \ + uintptr_t *, uintptr_t *, \ + struct La_sparc32_regs *, \ + unsigned int *, const char *name, \ + long int *framesizep); \ + Elf64_Addr (*sparc64_gnu_pltenter) (Elf64_Sym *, unsigned int, \ + uintptr_t *, uintptr_t *, \ + struct La_sparc64_regs *, \ + unsigned int *, const char *name, \ + long int *framesizep) + +#define ARCH_PLTEXIT_MEMBERS \ + unsigned int (*sparc32_gnu_pltexit) (Elf32_Sym *, unsigned int, \ + uintptr_t *, uintptr_t *, \ + const struct La_sparc32_regs *, \ + struct La_sparc32_retval *, \ + const char *); \ + unsigned int (*sparc64_gnu_pltexit) (Elf64_Sym *, unsigned int, \ + uintptr_t *, uintptr_t *, \ + const struct La_sparc32_regs *, \ + struct La_sparc32_retval *, \ + const char *) + +#include_next <ldsodefs.h> + +#endif diff --git a/REORG.TODO/sysdeps/sparc/machine-gmon.h b/REORG.TODO/sysdeps/sparc/machine-gmon.h new file mode 100644 index 0000000000..361d98bb97 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/machine-gmon.h @@ -0,0 +1,32 @@ +/* sparc-specific implementation of profiling support. + Copyright (C) 2008-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2008 + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +/* We must not pollute the global namespace. */ +#define mcount_internal __mcount_internal + +extern void mcount_internal (u_long frompc, u_long selfpc) internal_function; + +#define _MCOUNT_DECL(frompc, selfpc) \ +void internal_function mcount_internal (u_long frompc, u_long selfpc) + +/* Define MCOUNT as empty since we have the implementation in another + file. */ +#define MCOUNT diff --git a/REORG.TODO/sysdeps/sparc/mempcpy.S b/REORG.TODO/sysdeps/sparc/mempcpy.S new file mode 100644 index 0000000000..4c98013757 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/mempcpy.S @@ -0,0 +1 @@ +/* mempcpy is in memcpy.S */ diff --git a/REORG.TODO/sysdeps/sparc/memusage.h b/REORG.TODO/sysdeps/sparc/memusage.h new file mode 100644 index 0000000000..529e966de4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/memusage.h @@ -0,0 +1,20 @@ +/* Copyright (C) 2000-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#define GETSP() ({ register uintptr_t stack_ptr asm ("%sp"); stack_ptr; }) + +#include <sysdeps/generic/memusage.h> diff --git a/REORG.TODO/sysdeps/sparc/nptl/Makefile b/REORG.TODO/sysdeps/sparc/nptl/Makefile new file mode 100644 index 0000000000..5372867dbd --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/nptl/Makefile @@ -0,0 +1,8 @@ +ifeq ($(subdir),csu) +gen-as-const-headers += tcb-offsets.sym +endif + +ifeq ($(subdir),nptl) +CPPFLAGS-pt-crti.S += -fPIC +CPPFLAGS-crtn.S += -fPIC +endif diff --git a/REORG.TODO/sysdeps/sparc/nptl/bits/pthreadtypes-arch.h b/REORG.TODO/sysdeps/sparc/nptl/bits/pthreadtypes-arch.h new file mode 100644 index 0000000000..1e188cf91f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/nptl/bits/pthreadtypes-arch.h @@ -0,0 +1,79 @@ +/* Machine-specific pthread type layouts. SPARC version. + Copyright (C) 2003-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _BITS_PTHREADTYPES_ARCH_H +#define _BITS_PTHREADTYPES_ARCH_H 1 + +#include <bits/wordsize.h> + +#if __WORDSIZE == 64 +# define __SIZEOF_PTHREAD_ATTR_T 56 +# define __SIZEOF_PTHREAD_MUTEX_T 40 +# define __SIZEOF_PTHREAD_CONDATTR_T 4 +# define __SIZEOF_PTHREAD_RWLOCK_T 56 +# define __SIZEOF_PTHREAD_BARRIER_T 32 +#else +# define __SIZEOF_PTHREAD_ATTR_T 36 +# define __SIZEOF_PTHREAD_MUTEX_T 24 +# define __SIZEOF_PTHREAD_CONDATTR_T 4 +# define __SIZEOF_PTHREAD_RWLOCK_T 32 +# define __SIZEOF_PTHREAD_BARRIER_T 20 +#endif +#define __SIZEOF_PTHREAD_MUTEXATTR_T 4 +#define __SIZEOF_PTHREAD_COND_T 48 +#define __SIZEOF_PTHREAD_RWLOCKATTR_T 8 +#define __SIZEOF_PTHREAD_BARRIERATTR_T 4 + +/* Definitions for internal mutex struct. */ +#define __PTHREAD_COMPAT_PADDING_MID +#define __PTHREAD_COMPAT_PADDING_END +#define __PTHREAD_MUTEX_LOCK_ELISION 0 + +#define __LOCK_ALIGNMENT +#define __ONCE_ALIGNMENT + +struct __pthread_rwlock_arch_t +{ + unsigned int __readers; + unsigned int __writers; + unsigned int __wrphase_futex; + unsigned int __writers_futex; + unsigned int __pad3; + unsigned int __pad4; +#if __WORDSIZE == 64 + int __cur_writer; + int __shared; + unsigned long int __pad1; + unsigned long int __pad2; + /* FLAGS must stay at this position in the structure to maintain + binary compatibility. */ + unsigned int __flags; +#else + unsigned char __pad1; + unsigned char __pad2; + unsigned char __shared; + /* FLAGS must stay at this position in the structure to maintain + binary compatibility. */ + unsigned char __flags; + int __cur_writer; +#endif +}; + +#define __PTHREAD_RWLOCK_ELISION_EXTRA 0 + +#endif /* bits/pthreadtypes.h */ diff --git a/REORG.TODO/sysdeps/sparc/nptl/bits/semaphore.h b/REORG.TODO/sysdeps/sparc/nptl/bits/semaphore.h new file mode 100644 index 0000000000..6f2e0155a2 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/nptl/bits/semaphore.h @@ -0,0 +1,40 @@ +/* Machine-specific POSIX semaphore type layouts. SPARC version. + Copyright (C) 2003-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jakub@redhat.com>, 2003. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _SEMAPHORE_H +# error "Never use <bits/semaphore.h> directly; include <semaphore.h> instead." +#endif + +#include <bits/wordsize.h> + +#if __WORDSIZE == 64 +# define __SIZEOF_SEM_T 32 +#else +# define __SIZEOF_SEM_T 16 +#endif + +/* Value returned if `sem_open' failed. */ +#define SEM_FAILED ((sem_t *) 0) + + +typedef union +{ + char __size[__SIZEOF_SEM_T]; + long int __align; +} sem_t; diff --git a/REORG.TODO/sysdeps/sparc/nptl/sparc-nptl.h b/REORG.TODO/sysdeps/sparc/nptl/sparc-nptl.h new file mode 100644 index 0000000000..baff918288 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/nptl/sparc-nptl.h @@ -0,0 +1,33 @@ +#ifndef _SPARC_NPTL_H + +union sparc_pthread_barrier +{ + struct pthread_barrier b; + struct sparc_pthread_barrier_s + { + unsigned int curr_event; + int lock; + unsigned int left; + unsigned int init_count; + unsigned char left_lock; + unsigned char pshared; + } s; +}; + +struct sparc_new_sem +{ + unsigned int value; + unsigned char lock; + unsigned char private; + unsigned char pad[2]; + unsigned long int nwaiters; +}; + +struct sparc_old_sem +{ + unsigned int value; + unsigned char lock; + unsigned char private; +}; + +#endif diff --git a/REORG.TODO/sysdeps/sparc/nptl/tcb-offsets.sym b/REORG.TODO/sysdeps/sparc/nptl/tcb-offsets.sym new file mode 100644 index 0000000000..f75d02065e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/nptl/tcb-offsets.sym @@ -0,0 +1,6 @@ +#include <sysdep.h> +#include <tls.h> + +MULTIPLE_THREADS_OFFSET offsetof (tcbhead_t, multiple_threads) +POINTER_GUARD offsetof (tcbhead_t, pointer_guard) +TID offsetof (struct pthread, tid) diff --git a/REORG.TODO/sysdeps/sparc/nptl/tls.h b/REORG.TODO/sysdeps/sparc/nptl/tls.h new file mode 100644 index 0000000000..f363b1958f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/nptl/tls.h @@ -0,0 +1,168 @@ +/* Definitions for thread-local data handling. NPTL/sparc version. + Copyright (C) 2003-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _TLS_H +#define _TLS_H + +#include <dl-sysdep.h> +#ifndef __ASSEMBLER__ +# include <stdbool.h> +# include <stddef.h> +# include <stdint.h> +# include <stdlib.h> +# include <list.h> +# include <kernel-features.h> +# include <dl-dtv.h> + +typedef struct +{ + void *tcb; /* Pointer to the TCB. Not necessary the + thread descriptor used by libpthread. */ + dtv_t *dtv; + void *self; + int multiple_threads; +#if __WORDSIZE == 64 + int gscope_flag; +#endif + uintptr_t sysinfo; + uintptr_t stack_guard; + uintptr_t pointer_guard; +#if __WORDSIZE != 64 + int gscope_flag; +#endif +#ifndef __ASSUME_PRIVATE_FUTEX + int private_futex; +#endif +} tcbhead_t; + +#else /* __ASSEMBLER__ */ +# include <tcb-offsets.h> +#endif /* __ASSEMBLER__ */ + + +#ifndef __ASSEMBLER__ +/* Get system call information. */ +# include <sysdep.h> + +register struct pthread *__thread_self __asm__("%g7"); + +/* This is the size of the initial TCB. Can't be just sizeof (tcbhead_t), + because NPTL getpid, __libc_alloca_cutoff etc. need (almost) the whole + struct pthread even when not linked with -lpthread. */ +# define TLS_INIT_TCB_SIZE sizeof (struct pthread) + +/* Alignment requirements for the initial TCB. */ +# define TLS_INIT_TCB_ALIGN __alignof__ (struct pthread) + +/* This is the size of the TCB. */ +# define TLS_TCB_SIZE sizeof (struct pthread) + +/* Alignment requirements for the TCB. */ +# define TLS_TCB_ALIGN __alignof__ (struct pthread) + +/* The TCB can have any size and the memory following the address the + thread pointer points to is unspecified. Allocate the TCB there. */ +# define TLS_TCB_AT_TP 1 +# define TLS_DTV_AT_TP 0 + +/* Get the thread descriptor definition. */ +# include <nptl/descr.h> + +/* Install the dtv pointer. The pointer passed is to the element with + index -1 which contain the length. */ +# define INSTALL_DTV(descr, dtvp) \ + ((tcbhead_t *) (descr))->dtv = (dtvp) + 1 + +/* Install new dtv for current thread. */ +# define INSTALL_NEW_DTV(DTV) \ + (((tcbhead_t *) __thread_self)->dtv = (DTV)) + +/* Return dtv of given thread descriptor. */ +# define GET_DTV(descr) \ + (((tcbhead_t *) (descr))->dtv) + +/* Code to initially initialize the thread pointer. */ +# define TLS_INIT_TP(descr) \ + (__thread_self = (__typeof (__thread_self)) (descr), NULL) + +/* Value passed to 'clone' for initialization of the thread register. */ +# define TLS_DEFINE_INIT_TP(tp, pd) void *tp = (pd) + +/* Return the address of the dtv for the current thread. */ +# define THREAD_DTV() \ + (((tcbhead_t *) __thread_self)->dtv) + +/* Return the thread descriptor for the current thread. */ +#define THREAD_SELF __thread_self + +/* Magic for libthread_db to know how to do THREAD_SELF. */ +# define DB_THREAD_SELF \ + REGISTER (32, 32, 10 * 4, 0) \ + REGISTER (64, __WORDSIZE, (6 * 8) + (__WORDSIZE==64?0:4), 0) + +/* Access to data in the thread descriptor is easy. */ +#define THREAD_GETMEM(descr, member) \ + descr->member +#define THREAD_GETMEM_NC(descr, member, idx) \ + descr->member[idx] +#define THREAD_SETMEM(descr, member, value) \ + descr->member = (value) +#define THREAD_SETMEM_NC(descr, member, idx, value) \ + descr->member[idx] = (value) + +/* Set the stack guard field in TCB head. */ +#define THREAD_SET_STACK_GUARD(value) \ + THREAD_SETMEM (THREAD_SELF, header.stack_guard, value) +# define THREAD_COPY_STACK_GUARD(descr) \ + ((descr)->header.stack_guard \ + = THREAD_GETMEM (THREAD_SELF, header.stack_guard)) + +/* Get/set the stack guard field in TCB head. */ +#define THREAD_GET_POINTER_GUARD() \ + THREAD_GETMEM (THREAD_SELF, header.pointer_guard) +#define THREAD_SET_POINTER_GUARD(value) \ + THREAD_SETMEM (THREAD_SELF, header.pointer_guard, value) +# define THREAD_COPY_POINTER_GUARD(descr) \ + ((descr)->header.pointer_guard = THREAD_GET_POINTER_GUARD ()) + +/* Get and set the global scope generation counter in struct pthread. */ +#define THREAD_GSCOPE_FLAG_UNUSED 0 +#define THREAD_GSCOPE_FLAG_USED 1 +#define THREAD_GSCOPE_FLAG_WAIT 2 +#define THREAD_GSCOPE_RESET_FLAG() \ + do \ + { int __res \ + = atomic_exchange_rel (&THREAD_SELF->header.gscope_flag, \ + THREAD_GSCOPE_FLAG_UNUSED); \ + if (__res == THREAD_GSCOPE_FLAG_WAIT) \ + lll_futex_wake (&THREAD_SELF->header.gscope_flag, 1, LLL_PRIVATE); \ + } \ + while (0) +#define THREAD_GSCOPE_SET_FLAG() \ + do \ + { \ + THREAD_SELF->header.gscope_flag = THREAD_GSCOPE_FLAG_USED; \ + atomic_write_barrier (); \ + } \ + while (0) +#define THREAD_GSCOPE_WAIT() \ + GL(dl_wait_lookup_done) () + +#endif /* !ASSEMBLER */ + +#endif /* tls.h */ diff --git a/REORG.TODO/sysdeps/sparc/preconfigure b/REORG.TODO/sysdeps/sparc/preconfigure new file mode 100644 index 0000000000..de86749573 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/preconfigure @@ -0,0 +1,24 @@ +# preconfigure fragment for sparc. + +case "$machine" in +sparc | sparcv[67]) + base_machine=sparc machine=sparc/sparc32 ;; +sparcv8 | supersparc | hypersparc) + base_machine=sparc machine=sparc/sparc32/sparcv8 ;; +sparcv8plus | sparcv8plusa | sparcv9) + base_machine=sparc machine=sparc/sparc32/sparcv9 ;; +sparcv8plusb | sparcv9b) + base_machine=sparc machine=sparc/sparc32/sparcv9/sparcv9b ;; +sparcv9v) + base_machine=sparc machine=sparc/sparc32/sparcv9/sparcv9v ;; +sparcv9v2) + base_machine=sparc machine=sparc/sparc32/sparcv9/sparcv9v2 ;; +sparc64) + base_machine=sparc machine=sparc/sparc64 ;; +sparc64b) + base_machine=sparc machine=sparc/sparc64/sparcv9b ;; +sparc64v) + base_machine=sparc machine=sparc/sparc64/sparcv9v ;; +sparc64v2) + base_machine=sparc machine=sparc/sparc64/sparcv9v2 ;; +esac diff --git a/REORG.TODO/sysdeps/sparc/sparc-ifunc.h b/REORG.TODO/sysdeps/sparc/sparc-ifunc.h new file mode 100644 index 0000000000..8cc86ff5e1 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc-ifunc.h @@ -0,0 +1,176 @@ +/* This file is part of the GNU C Library. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +#ifdef __ASSEMBLER__ + +# ifdef SHARED + +# define SPARC_ASM_IFUNC_DFLT(name, dflt) \ +ENTRY (__##name) \ + .type __##name, @gnu_indirect_function; \ + SETUP_PIC_REG_LEAF(o3, o5); \ + sethi %gdop_hix22(dflt), %o1; \ + xor %o1, %gdop_lox10(dflt), %o1; \ + add %o3, %o1, %o1; \ + retl; \ + mov %o1, %o0; \ +END (__##name) + +# define SPARC_ASM_IFUNC1(name, m1, f1, dflt) \ +ENTRY (__##name) \ + .type __##name, @gnu_indirect_function; \ + SETUP_PIC_REG_LEAF(o3, o5); \ + set m1, %o1; \ + andcc %o0, %o1, %g0; \ + be 9f; \ + nop; \ + sethi %gdop_hix22(f1), %o1; \ + xor %o1, %gdop_lox10(f1), %o1; \ + ba 10f; \ + nop; \ +9: sethi %gdop_hix22(dflt), %o1; \ + xor %o1, %gdop_lox10(dflt), %o1; \ +10: add %o3, %o1, %o1; \ + retl; \ + mov %o1, %o0; \ +END (__##name) + +# define SPARC_ASM_IFUNC2(name, m1, f1, m2, f2, dflt) \ +ENTRY (__##name) \ + .type __##name, @gnu_indirect_function; \ + SETUP_PIC_REG_LEAF(o3, o5); \ + set m1, %o1; \ + andcc %o0, %o1, %g0; \ + be 8f; \ + nop; \ + sethi %gdop_hix22(f1), %o1; \ + xor %o1, %gdop_lox10(f1), %o1; \ + ba 10f; \ + nop; \ +8: set m2, %o1; \ + andcc %o0, %o1, %g0; \ + be 9f; \ + nop; \ + sethi %gdop_hix22(f2), %o1; \ + xor %o1, %gdop_lox10(f2), %o1; \ + ba 10f; \ + nop; \ +9: sethi %gdop_hix22(dflt), %o1; \ + xor %o1, %gdop_lox10(dflt), %o1; \ +10: add %o3, %o1, %o1; \ + retl; \ + mov %o1, %o0; \ +END (__##name) + +# else /* SHARED */ + +# ifdef __arch64__ +# define SET(SYM, TMP, REG) setx SYM, TMP, REG +# else +# define SET(SYM, TMP, REG) set SYM, REG +# endif + +# define SPARC_ASM_IFUNC_DFLT(name, dflt) \ +ENTRY (__##name) \ + .type __##name, @gnu_indirect_function; \ + SET(dflt, %g1, %o1); \ + retl; \ + mov %o1, %o0; \ +END (__##name) + +# define SPARC_ASM_IFUNC1(name, m1, f1, dflt) \ +ENTRY (__##name) \ + .type __##name, @gnu_indirect_function; \ + set m1, %o1; \ + andcc %o0, %o1, %g0; \ + be 9f; \ + nop; \ + SET(f1, %g1, %o1); \ + ba 10f; \ + nop; \ +9: SET(dflt, %g1, %o1); \ +10: retl; \ + mov %o1, %o0; \ +END (__##name) + +# define SPARC_ASM_IFUNC2(name, m1, f1, m2, f2, dflt) \ +ENTRY (__##name) \ + .type __##name, @gnu_indirect_function; \ + set m1, %o1; \ + andcc %o0, %o1, %g0; \ + be 8f; \ + nop; \ + SET(f1, %g1, %o1); \ + ba 10f; \ + nop; \ +8: set m2, %o1; \ + andcc %o0, %o1, %g0; \ + be 9f; \ + nop; \ + SET(f2, %g1, %o1); \ + ba 10f; \ + nop; \ +9: SET(dflt, %g1, %o1); \ +10: retl; \ + mov %o1, %o0; \ +END (__##name) + +# endif /* SHARED */ + +#define SPARC_ASM_VIS2_IFUNC(name) \ + SPARC_ASM_IFUNC1(name, HWCAP_SPARC_VIS2, \ + __##name##_vis2, __##name##_generic) + +# ifdef HAVE_AS_VIS3_SUPPORT + +#define SPARC_ASM_VIS3_IFUNC(name) \ + SPARC_ASM_IFUNC1(name, HWCAP_SPARC_VIS3, \ + __##name##_vis3, __##name##_generic) + +#define SPARC_ASM_VIS3_VIS2_IFUNC(name) \ + SPARC_ASM_IFUNC2(name, HWCAP_SPARC_VIS3, \ + __##name##_vis3, \ + HWCAP_SPARC_VIS2, \ + __##name##_vis2, __##name##_generic) + +# else /* HAVE_AS_VIS3_SUPPORT */ + +#define SPARC_ASM_VIS3_IFUNC(name) \ + SPARC_ASM_IFUNC_DFLT(name, __##name##_generic) + +#define SPARC_ASM_VIS3_VIS2_IFUNC(name) \ + SPARC_ASM_VIS2_IFUNC(name) + +# endif /* HAVE_AS_VIS3_SUPPORT */ + + +#else /* __ASSEMBLER__ */ + +# define sparc_libm_ifunc(name, expr) \ + extern void *name##_ifunc (int) __asm__ (#name); \ + void *name##_ifunc (int hwcap) \ + { \ + __typeof (name) *res = expr; \ + return res; \ + } \ + __asm__ (".type " #name ", %gnu_indirect_function"); + +# define sparc_libc_ifunc(name, expr) sparc_libm_ifunc (name, expr) + +#endif /* __ASSEMBLER__ */ diff --git a/REORG.TODO/sysdeps/sparc/sparc-mcount.S b/REORG.TODO/sysdeps/sparc/sparc-mcount.S new file mode 100644 index 0000000000..9564a5548c --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc-mcount.S @@ -0,0 +1,28 @@ +/* sparc-specific implementation of profiling support. + Copyright (C) 2008-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2008. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(_mcount) + mov %i7, %o0 + ba __mcount_internal + mov %o7, %o1 +END(_mcount) + +weak_alias (_mcount, mcount) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/Implies b/REORG.TODO/sysdeps/sparc/sparc32/Implies new file mode 100644 index 0000000000..436436a651 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/Implies @@ -0,0 +1,6 @@ +wordsize-32 +# SPARC uses IEEE 754 floating point. +ieee754/ldbl-128 +ieee754/dbl-64 +ieee754/flt-32 +sparc/sparc32/soft-fp diff --git a/REORG.TODO/sysdeps/sparc/sparc32/Makefile b/REORG.TODO/sysdeps/sparc/sparc32/Makefile new file mode 100644 index 0000000000..14d6e03c6f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/Makefile @@ -0,0 +1,55 @@ +# Copyright (C) 1991-2017 Free Software Foundation, Inc. +# This file is part of the GNU C Library. + +# The GNU C Library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. + +# The GNU C Library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. + +# You should have received a copy of the GNU Lesser General Public +# License along with the GNU C Library; if not, see +# <http://www.gnu.org/licenses/>. + +ifeq ($(subdir),gnulib) +sysdep_routines = dotmul umul $(divrem) alloca +endif # gnulib + +# We distribute these files, even though they are generated, +# so as to avoid the need for a functioning m4 to build the library. +divrem := sdiv udiv rem urem + ++divrem-NAME-sdiv := div ++divrem-NAME-udiv := udiv ++divrem-NAME-rem := rem ++divrem-NAME-urem := urem ++divrem-NAME = $(+divrem-NAME-$(basename $(notdir $@))) ++divrem-OP-div := div ++divrem-OP-udiv := div ++divrem-OP-rem := rem ++divrem-OP-urem := rem ++divrem-S-div := true ++divrem-S-rem := true ++divrem-S-udiv := false ++divrem-S-urem := false +$(divrem:%=$(sysdep_dir)/sparc/sparc32/%.S): $(sysdep_dir)/sparc/sparc32/divrem.m4 + (echo "define(NAME,\`.$(+divrem-NAME)')\ + define(OP,\`$(+divrem-OP-$(+divrem-NAME))')\ + define(S,\`$(+divrem-S-$(+divrem-NAME))')\ + /* This file is generated from divrem.m4; DO NOT EDIT! */"; \ + cat $<) | $(M4) > $@-tmp +# Make it unwritable so noone will edit it by mistake. + -chmod a-w $@-tmp + mv -f $@-tmp $@ + +sysdep-realclean := $(sysdep-realclean) $(divrem:%=sysdeps/sparc/sparc32/%.S) + +# libgcc __divdi3 and __moddi3 uses .udiv and since it is also exported by +# libc.so linker will create PLTs for the symbol. To avoid it we strong alias +# the exported libc one to __wrap_.udiv and use linker option --wrap to make any +# call to .udiv to call the wrapper symbol. +libc.so-gnulib += -Wl,--wrap=.udiv diff --git a/REORG.TODO/sysdeps/sparc/sparc32/Versions b/REORG.TODO/sysdeps/sparc/sparc32/Versions new file mode 100644 index 0000000000..6d3bfe880e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/Versions @@ -0,0 +1,10 @@ +libc { + GLIBC_2.0 { + .div; .mul; .rem; .udiv; .umul; .urem; + } +} +libm { + GLIBC_2.23 { + __sqrtl_finite; + } +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/__longjmp.S b/REORG.TODO/sysdeps/sparc/sparc32/__longjmp.S new file mode 100644 index 0000000000..2cfb6c23e7 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/__longjmp.S @@ -0,0 +1,93 @@ +/* Copyright (C) 1991-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +#include <jmpbuf-offsets.h> +#define ENV(base,reg) [%base + (reg * 4)] +#define ST_FLUSH_WINDOWS 3 + +ENTRY(__longjmp) + /* Store our arguments in global registers so we can still + use them while unwinding frames and their register windows. */ + + ld ENV(o0,JB_FP), %g3 /* Cache target FP in register %g3. */ +#ifdef PTR_DEMANGLE + PTR_DEMANGLE (%g3, %g3, %g4) +#endif + mov %o0, %g1 /* ENV in %g1 */ + orcc %o1, %g0, %g2 /* VAL in %g2 */ + be,a 0f /* Branch if zero; else skip delay slot. */ + mov 1, %g2 /* Delay slot only hit if zero: VAL = 1. */ +0: + xor %fp, %g3, %o0 + add %fp, 512, %o1 + andncc %o0, 4095, %o0 + bne LOC(thread) + cmp %o1, %g3 + bl LOC(thread) + + /* Now we will loop, unwinding the register windows up the stack + until the restored %fp value matches the target value in %g3. */ + +LOC(loop): + cmp %fp, %g3 /* Have we reached the target frame? */ + bl,a LOC(loop) /* Loop while current fp is below target. */ + restore /* Unwind register window in delay slot. */ + be,a LOC(found) /* Better have hit it exactly. */ + ld ENV(g1,JB_SP), %o0 /* Delay slot: extract target SP. */ + +LOC(thread): + save %sp, -96, %sp + /* + * Do a "flush register windows trap". The trap handler in the + * kernel writes all the register windows to their stack slots, and + * marks them all as invalid (needing to be sucked up from the + * stack when used). This ensures that all information needed to + * unwind to these callers is in memory, not in the register + * windows. + */ + ta ST_FLUSH_WINDOWS +#ifdef PTR_DEMANGLE + ld ENV(g1,JB_PC), %g5 /* Set return PC. */ + ld ENV(g1,JB_SP), %g1 /* Set saved SP on restore below. */ + PTR_DEMANGLE2 (%i7, %g5, %g4) + PTR_DEMANGLE2 (%fp, %g1, %g4) +#else + ld ENV(g1,JB_PC), %i7 /* Set return PC. */ + ld ENV(g1,JB_SP), %fp /* Set saved SP on restore below. */ +#endif + jmp %i7 + 8 + restore %g2, 0, %o0 /* Restore values from above register frame. */ + +LOC(found): + /* We have unwound register windows so %fp matches the target. */ +#ifdef PTR_DEMANGLE + PTR_DEMANGLE2 (%sp, %o0, %g4) +#else + mov %o0, %sp /* OK, install new SP. */ +#endif + +LOC(sp_ok): + ld ENV(g1,JB_PC), %o0 /* Extract target return PC. */ +#ifdef PTR_DEMANGLE + PTR_DEMANGLE2 (%o0, %o0, %g4) +#endif + jmp %o0 + 8 /* Return there. */ + mov %g2, %o0 /* Delay slot: set return value. */ + +END(__longjmp) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/add_n.S b/REORG.TODO/sysdeps/sparc/sparc32/add_n.S new file mode 100644 index 0000000000..75289af5f9 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/add_n.S @@ -0,0 +1,237 @@ +! SPARC __mpn_add_n -- Add two limb vectors of the same length > 0 and store +! sum in a third limb vector. +! +! Copyright (C) 1995-2017 Free Software Foundation, Inc. +! +! This file is part of the GNU MP Library. +! +! The GNU MP Library is free software; you can redistribute it and/or modify +! it under the terms of the GNU Lesser General Public License as published by +! the Free Software Foundation; either version 2.1 of the License, or (at your +! option) any later version. +! +! The GNU MP Library is distributed in the hope that it will be useful, but +! WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +! or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +! License for more details. +! +! You should have received a copy of the GNU Lesser General Public License +! along with the GNU MP Library; see the file COPYING.LIB. If not, +! see <http://www.gnu.org/licenses/>. + + +! INPUT PARAMETERS +#define RES_PTR %o0 +#define S1_PTR %o1 +#define S2_PTR %o2 +#define SIZE %o3 + +#include <sysdep.h> + +ENTRY(__mpn_add_n) + xor S2_PTR,RES_PTR,%g1 + andcc %g1,4,%g0 + bne LOC(1) ! branch if alignment differs + nop +! ** V1a ** +LOC(0): andcc RES_PTR,4,%g0 ! RES_PTR unaligned? Side effect: cy=0 + be LOC(v1) ! if no, branch + nop +/* Add least significant limb separately to align RES_PTR and S2_PTR */ + ld [S1_PTR],%g4 + add S1_PTR,4,S1_PTR + ld [S2_PTR],%g2 + add S2_PTR,4,S2_PTR + add SIZE,-1,SIZE + addcc %g4,%g2,%o4 + st %o4,[RES_PTR] + add RES_PTR,4,RES_PTR +LOC(v1): + addx %g0,%g0,%o4 ! save cy in register + cmp SIZE,2 ! if SIZE < 2 ... + bl LOC(end2) ! ... branch to tail code + subcc %g0,%o4,%g0 ! restore cy + + ld [S1_PTR+0],%g4 + addcc SIZE,-10,SIZE + ld [S1_PTR+4],%g1 + ldd [S2_PTR+0],%g2 + blt LOC(fin1) + subcc %g0,%o4,%g0 ! restore cy +/* Add blocks of 8 limbs until less than 8 limbs remain */ +LOC(loop1): + addxcc %g4,%g2,%o4 + ld [S1_PTR+8],%g4 + addxcc %g1,%g3,%o5 + ld [S1_PTR+12],%g1 + ldd [S2_PTR+8],%g2 + std %o4,[RES_PTR+0] + addxcc %g4,%g2,%o4 + ld [S1_PTR+16],%g4 + addxcc %g1,%g3,%o5 + ld [S1_PTR+20],%g1 + ldd [S2_PTR+16],%g2 + std %o4,[RES_PTR+8] + addxcc %g4,%g2,%o4 + ld [S1_PTR+24],%g4 + addxcc %g1,%g3,%o5 + ld [S1_PTR+28],%g1 + ldd [S2_PTR+24],%g2 + std %o4,[RES_PTR+16] + addxcc %g4,%g2,%o4 + ld [S1_PTR+32],%g4 + addxcc %g1,%g3,%o5 + ld [S1_PTR+36],%g1 + ldd [S2_PTR+32],%g2 + std %o4,[RES_PTR+24] + addx %g0,%g0,%o4 ! save cy in register + addcc SIZE,-8,SIZE + add S1_PTR,32,S1_PTR + add S2_PTR,32,S2_PTR + add RES_PTR,32,RES_PTR + bge LOC(loop1) + subcc %g0,%o4,%g0 ! restore cy + +LOC(fin1): + addcc SIZE,8-2,SIZE + blt LOC(end1) + subcc %g0,%o4,%g0 ! restore cy +/* Add blocks of 2 limbs until less than 2 limbs remain */ +LOC(loope1): + addxcc %g4,%g2,%o4 + ld [S1_PTR+8],%g4 + addxcc %g1,%g3,%o5 + ld [S1_PTR+12],%g1 + ldd [S2_PTR+8],%g2 + std %o4,[RES_PTR+0] + addx %g0,%g0,%o4 ! save cy in register + addcc SIZE,-2,SIZE + add S1_PTR,8,S1_PTR + add S2_PTR,8,S2_PTR + add RES_PTR,8,RES_PTR + bge LOC(loope1) + subcc %g0,%o4,%g0 ! restore cy +LOC(end1): + addxcc %g4,%g2,%o4 + addxcc %g1,%g3,%o5 + std %o4,[RES_PTR+0] + addx %g0,%g0,%o4 ! save cy in register + + andcc SIZE,1,%g0 + be LOC(ret1) + subcc %g0,%o4,%g0 ! restore cy +/* Add last limb */ + ld [S1_PTR+8],%g4 + ld [S2_PTR+8],%g2 + addxcc %g4,%g2,%o4 + st %o4,[RES_PTR+8] + +LOC(ret1): + retl + addx %g0,%g0,%o0 ! return carry-out from most sign. limb + +LOC(1): xor S1_PTR,RES_PTR,%g1 + andcc %g1,4,%g0 + bne LOC(2) + nop +! ** V1b ** + mov S2_PTR,%g1 + mov S1_PTR,S2_PTR + b LOC(0) + mov %g1,S1_PTR + +! ** V2 ** +/* If we come here, the alignment of S1_PTR and RES_PTR as well as the + alignment of S2_PTR and RES_PTR differ. Since there are only two ways + things can be aligned (that we care about) we now know that the alignment + of S1_PTR and S2_PTR are the same. */ + +LOC(2): cmp SIZE,1 + be LOC(jone) + nop + andcc S1_PTR,4,%g0 ! S1_PTR unaligned? Side effect: cy=0 + be LOC(v2) ! if no, branch + nop +/* Add least significant limb separately to align S1_PTR and S2_PTR */ + ld [S1_PTR],%g4 + add S1_PTR,4,S1_PTR + ld [S2_PTR],%g2 + add S2_PTR,4,S2_PTR + add SIZE,-1,SIZE + addcc %g4,%g2,%o4 + st %o4,[RES_PTR] + add RES_PTR,4,RES_PTR + +LOC(v2): + addx %g0,%g0,%o4 ! save cy in register + addcc SIZE,-8,SIZE + blt LOC(fin2) + subcc %g0,%o4,%g0 ! restore cy +/* Add blocks of 8 limbs until less than 8 limbs remain */ +LOC(loop2): + ldd [S1_PTR+0],%g2 + ldd [S2_PTR+0],%o4 + addxcc %g2,%o4,%g2 + st %g2,[RES_PTR+0] + addxcc %g3,%o5,%g3 + st %g3,[RES_PTR+4] + ldd [S1_PTR+8],%g2 + ldd [S2_PTR+8],%o4 + addxcc %g2,%o4,%g2 + st %g2,[RES_PTR+8] + addxcc %g3,%o5,%g3 + st %g3,[RES_PTR+12] + ldd [S1_PTR+16],%g2 + ldd [S2_PTR+16],%o4 + addxcc %g2,%o4,%g2 + st %g2,[RES_PTR+16] + addxcc %g3,%o5,%g3 + st %g3,[RES_PTR+20] + ldd [S1_PTR+24],%g2 + ldd [S2_PTR+24],%o4 + addxcc %g2,%o4,%g2 + st %g2,[RES_PTR+24] + addxcc %g3,%o5,%g3 + st %g3,[RES_PTR+28] + addx %g0,%g0,%o4 ! save cy in register + addcc SIZE,-8,SIZE + add S1_PTR,32,S1_PTR + add S2_PTR,32,S2_PTR + add RES_PTR,32,RES_PTR + bge LOC(loop2) + subcc %g0,%o4,%g0 ! restore cy + +LOC(fin2): + addcc SIZE,8-2,SIZE + blt LOC(end2) + subcc %g0,%o4,%g0 ! restore cy +LOC(loope2): + ldd [S1_PTR+0],%g2 + ldd [S2_PTR+0],%o4 + addxcc %g2,%o4,%g2 + st %g2,[RES_PTR+0] + addxcc %g3,%o5,%g3 + st %g3,[RES_PTR+4] + addx %g0,%g0,%o4 ! save cy in register + addcc SIZE,-2,SIZE + add S1_PTR,8,S1_PTR + add S2_PTR,8,S2_PTR + add RES_PTR,8,RES_PTR + bge LOC(loope2) + subcc %g0,%o4,%g0 ! restore cy +LOC(end2): + andcc SIZE,1,%g0 + be LOC(ret2) + subcc %g0,%o4,%g0 ! restore cy +/* Add last limb */ +LOC(jone): + ld [S1_PTR],%g4 + ld [S2_PTR],%g2 + addxcc %g4,%g2,%o4 + st %o4,[RES_PTR] + +LOC(ret2): + retl + addx %g0,%g0,%o0 ! return carry-out from most sign. limb + +END(__mpn_add_n) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/addmul_1.S b/REORG.TODO/sysdeps/sparc/sparc32/addmul_1.S new file mode 100644 index 0000000000..080e5f3d06 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/addmul_1.S @@ -0,0 +1,146 @@ +! SPARC __mpn_addmul_1 -- Multiply a limb vector with a limb and add +! the result to a second limb vector. +! +! Copyright (C) 1992-2017 Free Software Foundation, Inc. +! +! This file is part of the GNU MP Library. +! +! The GNU MP Library is free software; you can redistribute it and/or modify +! it under the terms of the GNU Lesser General Public License as published by +! the Free Software Foundation; either version 2.1 of the License, or (at your +! option) any later version. +! +! The GNU MP Library is distributed in the hope that it will be useful, but +! WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +! or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +! License for more details. +! +! You should have received a copy of the GNU Lesser General Public License +! along with the GNU MP Library; see the file COPYING.LIB. If not, +! see <http://www.gnu.org/licenses/>. + + +! INPUT PARAMETERS +! RES_PTR o0 +! S1_PTR o1 +! SIZE o2 +! S2_LIMB o3 + +#include <sysdep.h> + +ENTRY(__mpn_addmul_1) + ! Make S1_PTR and RES_PTR point at the end of their blocks + ! and put (- 4 x SIZE) in index/loop counter. + sll %o2,2,%o2 + add %o0,%o2,%o4 ! RES_PTR in o4 since o0 is retval + add %o1,%o2,%o1 + sub %g0,%o2,%o2 + + cmp %o3,0xfff + bgu LOC(large) + nop + + ld [%o1+%o2],%o5 + mov 0,%o0 + b LOC(0) + add %o4,-4,%o4 +LOC(loop0): + addcc %o5,%g1,%g1 + ld [%o1+%o2],%o5 + addx %o0,%g0,%o0 + st %g1,[%o4+%o2] +LOC(0): wr %g0,%o3,%y + sra %o5,31,%g2 + and %o3,%g2,%g2 + andcc %g1,0,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,0,%g1 + sra %g1,20,%g4 + sll %g1,12,%g1 + rd %y,%g3 + srl %g3,20,%g3 + or %g1,%g3,%g1 + + addcc %g1,%o0,%g1 + addx %g2,%g4,%o0 ! add sign-compensation and cy to hi limb + addcc %o2,4,%o2 ! loop counter + bne LOC(loop0) + ld [%o4+%o2],%o5 + + addcc %o5,%g1,%g1 + addx %o0,%g0,%o0 + retl + st %g1,[%o4+%o2] + + +LOC(large): + ld [%o1+%o2],%o5 + mov 0,%o0 + sra %o3,31,%g4 ! g4 = mask of ones iff S2_LIMB < 0 + b LOC(1) + add %o4,-4,%o4 +LOC(loop): + addcc %o5,%g3,%g3 + ld [%o1+%o2],%o5 + addx %o0,%g0,%o0 + st %g3,[%o4+%o2] +LOC(1): wr %g0,%o5,%y + and %o5,%g4,%g2 + andcc %g0,%g0,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%g0,%g1 + rd %y,%g3 + addcc %g3,%o0,%g3 + addx %g2,%g1,%o0 + addcc %o2,4,%o2 + bne LOC(loop) + ld [%o4+%o2],%o5 + + addcc %o5,%g3,%g3 + addx %o0,%g0,%o0 + retl + st %g3,[%o4+%o2] + +END(__mpn_addmul_1) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/alloca.S b/REORG.TODO/sysdeps/sparc/sparc32/alloca.S new file mode 100644 index 0000000000..60cd800800 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/alloca.S @@ -0,0 +1,28 @@ +/* Copyright (C) 1994-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +/* Code produced by Sun's C compiler calls this function with two extra + arguments which it makes relocatable symbols but seem always to be + the constant 96; I have no idea what they are for. */ + +ENTRY (__builtin_alloca) + sub %sp, %o0, %sp /* Push some stack space. */ + retl /* Return; the returned buffer leaves 96 */ + add %sp, 96, %o0 /* bytes of register save area at the top. */ +END (__builtin_alloca) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/atomic-machine.h b/REORG.TODO/sysdeps/sparc/sparc32/atomic-machine.h new file mode 100644 index 0000000000..a2fe8485b4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/atomic-machine.h @@ -0,0 +1,363 @@ +/* Atomic operations. sparc32 version. + Copyright (C) 2003-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jakub@redhat.com>, 2003. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _ATOMIC_MACHINE_H +#define _ATOMIC_MACHINE_H 1 + +#include <stdint.h> + +typedef int8_t atomic8_t; +typedef uint8_t uatomic8_t; +typedef int_fast8_t atomic_fast8_t; +typedef uint_fast8_t uatomic_fast8_t; + +typedef int16_t atomic16_t; +typedef uint16_t uatomic16_t; +typedef int_fast16_t atomic_fast16_t; +typedef uint_fast16_t uatomic_fast16_t; + +typedef int32_t atomic32_t; +typedef uint32_t uatomic32_t; +typedef int_fast32_t atomic_fast32_t; +typedef uint_fast32_t uatomic_fast32_t; + +typedef int64_t atomic64_t; +typedef uint64_t uatomic64_t; +typedef int_fast64_t atomic_fast64_t; +typedef uint_fast64_t uatomic_fast64_t; + +typedef intptr_t atomicptr_t; +typedef uintptr_t uatomicptr_t; +typedef intmax_t atomic_max_t; +typedef uintmax_t uatomic_max_t; + +#define __HAVE_64B_ATOMICS 0 +#define USE_ATOMIC_COMPILER_BUILTINS 0 + +/* XXX Is this actually correct? */ +#define ATOMIC_EXCHANGE_USES_CAS 1 + + +/* We have no compare and swap, just test and set. + The following implementation contends on 64 global locks + per library and assumes no variable will be accessed using atomic.h + macros from two different libraries. */ + +__make_section_unallocated + (".gnu.linkonce.b.__sparc32_atomic_locks, \"aw\", %nobits"); + +volatile unsigned char __sparc32_atomic_locks[64] + __attribute__ ((nocommon, section (".gnu.linkonce.b.__sparc32_atomic_locks" + __sec_comment), + visibility ("hidden"))); + +#define __sparc32_atomic_do_lock(addr) \ + do \ + { \ + unsigned int __old_lock; \ + unsigned int __idx = (((long) addr >> 2) ^ ((long) addr >> 12)) \ + & 63; \ + do \ + __asm __volatile ("ldstub %1, %0" \ + : "=r" (__old_lock), \ + "=m" (__sparc32_atomic_locks[__idx]) \ + : "m" (__sparc32_atomic_locks[__idx]) \ + : "memory"); \ + while (__old_lock); \ + } \ + while (0) + +#define __sparc32_atomic_do_unlock(addr) \ + do \ + { \ + __sparc32_atomic_locks[(((long) addr >> 2) \ + ^ ((long) addr >> 12)) & 63] = 0; \ + __asm __volatile ("" ::: "memory"); \ + } \ + while (0) + +#define __sparc32_atomic_do_lock24(addr) \ + do \ + { \ + unsigned int __old_lock; \ + do \ + __asm __volatile ("ldstub %1, %0" \ + : "=r" (__old_lock), "=m" (*(addr)) \ + : "m" (*(addr)) \ + : "memory"); \ + while (__old_lock); \ + } \ + while (0) + +#define __sparc32_atomic_do_unlock24(addr) \ + do \ + { \ + __asm __volatile ("" ::: "memory"); \ + *(char *) (addr) = 0; \ + } \ + while (0) + + +#ifndef SHARED +# define __v9_compare_and_exchange_val_32_acq(mem, newval, oldval) \ +({union { __typeof (oldval) a; uint32_t v; } oldval_arg = { .a = (oldval) }; \ + union { __typeof (newval) a; uint32_t v; } newval_arg = { .a = (newval) }; \ + register uint32_t __acev_tmp __asm ("%g6"); \ + register __typeof (mem) __acev_mem __asm ("%g1") = (mem); \ + register uint32_t __acev_oldval __asm ("%g5"); \ + __acev_tmp = newval_arg.v; \ + __acev_oldval = oldval_arg.v; \ + /* .word 0xcde05005 is cas [%g1], %g5, %g6. Can't use cas here though, \ + because as will then mark the object file as V8+ arch. */ \ + __asm __volatile (".word 0xcde05005" \ + : "+r" (__acev_tmp), "=m" (*__acev_mem) \ + : "r" (__acev_oldval), "m" (*__acev_mem), \ + "r" (__acev_mem) : "memory"); \ + (__typeof (oldval)) __acev_tmp; }) +#endif + +/* The only basic operation needed is compare and exchange. */ +#define __v7_compare_and_exchange_val_acq(mem, newval, oldval) \ + ({ __typeof (mem) __acev_memp = (mem); \ + __typeof (*mem) __acev_ret; \ + __typeof (*mem) __acev_newval = (newval); \ + \ + __sparc32_atomic_do_lock (__acev_memp); \ + __acev_ret = *__acev_memp; \ + if (__acev_ret == (oldval)) \ + *__acev_memp = __acev_newval; \ + __sparc32_atomic_do_unlock (__acev_memp); \ + __acev_ret; }) + +#define __v7_compare_and_exchange_bool_acq(mem, newval, oldval) \ + ({ __typeof (mem) __aceb_memp = (mem); \ + int __aceb_ret; \ + __typeof (*mem) __aceb_newval = (newval); \ + \ + __sparc32_atomic_do_lock (__aceb_memp); \ + __aceb_ret = 0; \ + if (*__aceb_memp == (oldval)) \ + *__aceb_memp = __aceb_newval; \ + else \ + __aceb_ret = 1; \ + __sparc32_atomic_do_unlock (__aceb_memp); \ + __aceb_ret; }) + +#define __v7_exchange_acq(mem, newval) \ + ({ __typeof (mem) __acev_memp = (mem); \ + __typeof (*mem) __acev_ret; \ + __typeof (*mem) __acev_newval = (newval); \ + \ + __sparc32_atomic_do_lock (__acev_memp); \ + __acev_ret = *__acev_memp; \ + *__acev_memp = __acev_newval; \ + __sparc32_atomic_do_unlock (__acev_memp); \ + __acev_ret; }) + +#define __v7_exchange_and_add(mem, value) \ + ({ __typeof (mem) __acev_memp = (mem); \ + __typeof (*mem) __acev_ret; \ + \ + __sparc32_atomic_do_lock (__acev_memp); \ + __acev_ret = *__acev_memp; \ + *__acev_memp = __acev_ret + (value); \ + __sparc32_atomic_do_unlock (__acev_memp); \ + __acev_ret; }) + +/* Special versions, which guarantee that top 8 bits of all values + are cleared and use those bits as the ldstub lock. */ +#define __v7_compare_and_exchange_val_24_acq(mem, newval, oldval) \ + ({ __typeof (mem) __acev_memp = (mem); \ + __typeof (*mem) __acev_ret; \ + __typeof (*mem) __acev_newval = (newval); \ + \ + __sparc32_atomic_do_lock24 (__acev_memp); \ + __acev_ret = *__acev_memp & 0xffffff; \ + if (__acev_ret == (oldval)) \ + *__acev_memp = __acev_newval; \ + else \ + __sparc32_atomic_do_unlock24 (__acev_memp); \ + __asm __volatile ("" ::: "memory"); \ + __acev_ret; }) + +#define __v7_exchange_24_rel(mem, newval) \ + ({ __typeof (mem) __acev_memp = (mem); \ + __typeof (*mem) __acev_ret; \ + __typeof (*mem) __acev_newval = (newval); \ + \ + __sparc32_atomic_do_lock24 (__acev_memp); \ + __acev_ret = *__acev_memp & 0xffffff; \ + *__acev_memp = __acev_newval; \ + __asm __volatile ("" ::: "memory"); \ + __acev_ret; }) + +#ifdef SHARED + +/* When dynamically linked, we assume pre-v9 libraries are only ever + used on pre-v9 CPU. */ +# define __atomic_is_v9 0 + +# define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \ + __v7_compare_and_exchange_val_acq (mem, newval, oldval) + +# define atomic_compare_and_exchange_bool_acq(mem, newval, oldval) \ + __v7_compare_and_exchange_bool_acq (mem, newval, oldval) + +# define atomic_exchange_acq(mem, newval) \ + __v7_exchange_acq (mem, newval) + +# define atomic_exchange_and_add(mem, value) \ + __v7_exchange_and_add (mem, value) + +# define atomic_compare_and_exchange_val_24_acq(mem, newval, oldval) \ + ({ \ + if (sizeof (*mem) != 4) \ + abort (); \ + __v7_compare_and_exchange_val_24_acq (mem, newval, oldval); }) + +# define atomic_exchange_24_rel(mem, newval) \ + ({ \ + if (sizeof (*mem) != 4) \ + abort (); \ + __v7_exchange_24_rel (mem, newval); }) + +# define atomic_full_barrier() __asm ("" ::: "memory") +# define atomic_read_barrier() atomic_full_barrier () +# define atomic_write_barrier() atomic_full_barrier () + +#else + +/* In libc.a/libpthread.a etc. we don't know if we'll be run on + pre-v9 or v9 CPU. To be interoperable with dynamically linked + apps on v9 CPUs e.g. with process shared primitives, use cas insn + on v9 CPUs and ldstub on pre-v9. */ + +extern uint64_t _dl_hwcap __attribute__((weak)); +# define __atomic_is_v9 \ + (__builtin_expect (&_dl_hwcap != 0, 1) \ + && __builtin_expect (_dl_hwcap & HWCAP_SPARC_V9, HWCAP_SPARC_V9)) + +# define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \ + ({ \ + __typeof (*mem) __acev_wret; \ + if (sizeof (*mem) != 4) \ + abort (); \ + if (__atomic_is_v9) \ + __acev_wret \ + = __v9_compare_and_exchange_val_32_acq (mem, newval, oldval);\ + else \ + __acev_wret \ + = __v7_compare_and_exchange_val_acq (mem, newval, oldval); \ + __acev_wret; }) + +# define atomic_compare_and_exchange_bool_acq(mem, newval, oldval) \ + ({ \ + int __acev_wret; \ + if (sizeof (*mem) != 4) \ + abort (); \ + if (__atomic_is_v9) \ + { \ + __typeof (oldval) __acev_woldval = (oldval); \ + __acev_wret \ + = __v9_compare_and_exchange_val_32_acq (mem, newval, \ + __acev_woldval) \ + != __acev_woldval; \ + } \ + else \ + __acev_wret \ + = __v7_compare_and_exchange_bool_acq (mem, newval, oldval); \ + __acev_wret; }) + +# define atomic_exchange_rel(mem, newval) \ + ({ \ + __typeof (*mem) __acev_wret; \ + if (sizeof (*mem) != 4) \ + abort (); \ + if (__atomic_is_v9) \ + { \ + __typeof (mem) __acev_wmemp = (mem); \ + __typeof (*(mem)) __acev_wval = (newval); \ + do \ + __acev_wret = *__acev_wmemp; \ + while (__builtin_expect \ + (__v9_compare_and_exchange_val_32_acq (__acev_wmemp,\ + __acev_wval, \ + __acev_wret) \ + != __acev_wret, 0)); \ + } \ + else \ + __acev_wret = __v7_exchange_acq (mem, newval); \ + __acev_wret; }) + +# define atomic_compare_and_exchange_val_24_acq(mem, newval, oldval) \ + ({ \ + __typeof (*mem) __acev_wret; \ + if (sizeof (*mem) != 4) \ + abort (); \ + if (__atomic_is_v9) \ + __acev_wret \ + = __v9_compare_and_exchange_val_32_acq (mem, newval, oldval);\ + else \ + __acev_wret \ + = __v7_compare_and_exchange_val_24_acq (mem, newval, oldval);\ + __acev_wret; }) + +# define atomic_exchange_24_rel(mem, newval) \ + ({ \ + __typeof (*mem) __acev_w24ret; \ + if (sizeof (*mem) != 4) \ + abort (); \ + if (__atomic_is_v9) \ + __acev_w24ret = atomic_exchange_rel (mem, newval); \ + else \ + __acev_w24ret = __v7_exchange_24_rel (mem, newval); \ + __acev_w24ret; }) + +#define atomic_full_barrier() \ + do { \ + if (__atomic_is_v9) \ + /* membar #LoadLoad | #LoadStore | #StoreLoad | #StoreStore */ \ + __asm __volatile (".word 0x8143e00f" : : : "memory"); \ + else \ + __asm __volatile ("" : : : "memory"); \ + } while (0) + +#define atomic_read_barrier() \ + do { \ + if (__atomic_is_v9) \ + /* membar #LoadLoad | #LoadStore */ \ + __asm __volatile (".word 0x8143e005" : : : "memory"); \ + else \ + __asm __volatile ("" : : : "memory"); \ + } while (0) + +#define atomic_write_barrier() \ + do { \ + if (__atomic_is_v9) \ + /* membar #LoadStore | #StoreStore */ \ + __asm __volatile (".word 0x8143e00c" : : : "memory"); \ + else \ + __asm __volatile ("" : : : "memory"); \ + } while (0) + +#endif + +#include <sysdep.h> + +#endif /* atomic-machine.h */ diff --git a/REORG.TODO/sysdeps/sparc/sparc32/backtrace.h b/REORG.TODO/sysdeps/sparc/sparc32/backtrace.h new file mode 100644 index 0000000000..089f8b4d28 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/backtrace.h @@ -0,0 +1,7 @@ +/* Private macros for guiding the backtrace implementation, sparc32 + version. */ + +#define backtrace_flush_register_windows() \ + asm volatile ("ta %0" : : "i" (ST_FLUSH_WINDOWS)) + +#define BACKTRACE_STACK_BIAS 0 diff --git a/REORG.TODO/sysdeps/sparc/sparc32/bits/setjmp.h b/REORG.TODO/sysdeps/sparc/sparc32/bits/setjmp.h new file mode 100644 index 0000000000..fbab934d6b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/bits/setjmp.h @@ -0,0 +1,26 @@ +/* Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +/* Define the machine-dependent type `jmp_buf'. SPARC version. */ + +#ifndef _SETJMP_H +# error "Never include <bits/setjmp.h> directly; use <setjmp.h> instead." +#endif + +#ifndef _ASM +typedef int __jmp_buf[3]; +#endif diff --git a/REORG.TODO/sysdeps/sparc/sparc32/bits/wordsize.h b/REORG.TODO/sysdeps/sparc/sparc32/bits/wordsize.h new file mode 100644 index 0000000000..2f66f10d72 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/bits/wordsize.h @@ -0,0 +1,11 @@ +/* Determine the wordsize from the preprocessor defines. */ + +#if defined __arch64__ || defined __sparcv9 +# define __WORDSIZE 64 +# define __WORDSIZE_TIME64_COMPAT32 1 +#else +# define __WORDSIZE 32 +# define __WORDSIZE_TIME64_COMPAT32 0 +# define __WORDSIZE32_SIZE_ULONG 0 +# define __WORDSIZE32_PTRDIFF_LONG 0 +#endif diff --git a/REORG.TODO/sysdeps/sparc/sparc32/bsd-_setjmp.S b/REORG.TODO/sysdeps/sparc/sparc32/bsd-_setjmp.S new file mode 100644 index 0000000000..4e6a2da560 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/bsd-_setjmp.S @@ -0,0 +1 @@ +/* _setjmp is in setjmp.S */ diff --git a/REORG.TODO/sysdeps/sparc/sparc32/bsd-setjmp.S b/REORG.TODO/sysdeps/sparc/sparc32/bsd-setjmp.S new file mode 100644 index 0000000000..1da848d2f1 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/bsd-setjmp.S @@ -0,0 +1 @@ +/* setjmp is in setjmp.S */ diff --git a/REORG.TODO/sysdeps/sparc/sparc32/bzero.c b/REORG.TODO/sysdeps/sparc/sparc32/bzero.c new file mode 100644 index 0000000000..37f0f6f993 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/bzero.c @@ -0,0 +1 @@ +/* bzero is in memset.S */ diff --git a/REORG.TODO/sysdeps/sparc/sparc32/divrem.m4 b/REORG.TODO/sysdeps/sparc/sparc32/divrem.m4 new file mode 100644 index 0000000000..30d532ad77 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/divrem.m4 @@ -0,0 +1,232 @@ +/* + * Division and remainder, from Appendix E of the Sparc Version 8 + * Architecture Manual, with fixes from Gordon Irlam. + */ + +/* + * Input: dividend and divisor in %o0 and %o1 respectively. + * + * m4 parameters: + * NAME name of function to generate + * OP OP=div => %o0 / %o1; OP=rem => %o0 % %o1 + * S S=true => signed; S=false => unsigned + * + * Algorithm parameters: + * N how many bits per iteration we try to get (4) + * WORDSIZE total number of bits (32) + * + * Derived constants: + * TOPBITS number of bits in the top `decade' of a number + * + * Important variables: + * Q the partial quotient under development (initially 0) + * R the remainder so far, initially the dividend + * ITER number of main division loop iterations required; + * equal to ceil(log2(quotient) / N). Note that this + * is the log base (2^N) of the quotient. + * V the current comparand, initially divisor*2^(ITER*N-1) + * + * Cost: + * Current estimate for non-large dividend is + * ceil(log2(quotient) / N) * (10 + 7N/2) + C + * A large dividend is one greater than 2^(31-TOPBITS) and takes a + * different path, as the upper bits of the quotient must be developed + * one bit at a time. + */ + +define(N, `4')dnl +define(WORDSIZE, `32')dnl +define(TOPBITS, eval(WORDSIZE - N*((WORDSIZE-1)/N)))dnl +dnl +define(dividend, `%o0')dnl +define(divisor, `%o1')dnl +define(Q, `%o2')dnl +define(R, `%o3')dnl +define(ITER, `%o4')dnl +define(V, `%o5')dnl +dnl +dnl m4 reminder: ifelse(a,b,c,d) => if a is b, then c, else d +define(T, `%g1')dnl +define(SC, `%g2')dnl +ifelse(S, `true', `define(SIGN, `%g3')')dnl + +dnl +dnl This is the recursive definition for developing quotient digits. +dnl +dnl Parameters: +dnl $1 the current depth, 1 <= $1 <= N +dnl $2 the current accumulation of quotient bits +dnl N max depth +dnl +dnl We add a new bit to $2 and either recurse or insert the bits in +dnl the quotient. R, Q, and V are inputs and outputs as defined above; +dnl the condition codes are expected to reflect the input R, and are +dnl modified to reflect the output R. +dnl +define(DEVELOP_QUOTIENT_BITS, +` ! depth $1, accumulated bits $2 + bl LOC($1.eval(2**N+$2)) + srl V,1,V + ! remainder is positive + subcc R,V,R + ifelse($1, N, + ` b 9f + add Q, ($2*2+1), Q + ', ` DEVELOP_QUOTIENT_BITS(incr($1), `eval(2*$2+1)')') +LOC($1.eval(2**N+$2)): + ! remainder is negative + addcc R,V,R + ifelse($1, N, + ` b 9f + add Q, ($2*2-1), Q + ', ` DEVELOP_QUOTIENT_BITS(incr($1), `eval(2*$2-1)')') + ifelse($1, 1, `9:')')dnl + +#include <sysdep.h> +#include <sys/trap.h> + +ENTRY(NAME) +ifelse(S, `true', +` ! compute sign of result; if neither is negative, no problem + orcc divisor, dividend, %g0 ! either negative? + bge 2f ! no, go do the divide +ifelse(OP, `div', +` xor divisor, dividend, SIGN ! compute sign in any case', +` mov dividend, SIGN ! sign of remainder matches dividend') + tst divisor + bge 1f + tst dividend + ! divisor is definitely negative; dividend might also be negative + bge 2f ! if dividend not negative... + sub %g0, divisor, divisor ! in any case, make divisor nonneg +1: ! dividend is negative, divisor is nonnegative + sub %g0, dividend, dividend ! make dividend nonnegative +2: +') + ! Ready to divide. Compute size of quotient; scale comparand. + orcc divisor, %g0, V + bne 1f + mov dividend, R + + ! Divide by zero trap. If it returns, return 0 (about as + ! wrong as possible, but that is what SunOS does...). + ta ST_DIV0 + retl + clr %o0 + +1: + cmp R, V ! if divisor exceeds dividend, done + blu LOC(got_result) ! (and algorithm fails otherwise) + clr Q + sethi %hi(1 << (WORDSIZE - TOPBITS - 1)), T + cmp R, T + blu LOC(not_really_big) + clr ITER + + ! `Here the dividend is >= 2**(31-N) or so. We must be careful here, + ! as our usual N-at-a-shot divide step will cause overflow and havoc. + ! The number of bits in the result here is N*ITER+SC, where SC <= N. + ! Compute ITER in an unorthodox manner: know we need to shift V into + ! the top decade: so do not even bother to compare to R.' + 1: + cmp V, T + bgeu 3f + mov 1, SC + sll V, N, V + b 1b + add ITER, 1, ITER + + ! Now compute SC. + 2: addcc V, V, V + bcc LOC(not_too_big) + add SC, 1, SC + + ! We get here if the divisor overflowed while shifting. + ! This means that R has the high-order bit set. + ! Restore V and subtract from R. + sll T, TOPBITS, T ! high order bit + srl V, 1, V ! rest of V + add V, T, V + b LOC(do_single_div) + sub SC, 1, SC + + LOC(not_too_big): + 3: cmp V, R + blu 2b + nop + be LOC(do_single_div) + nop + /* NB: these are commented out in the V8-Sparc manual as well */ + /* (I do not understand this) */ + ! V > R: went too far: back up 1 step + ! srl V, 1, V + ! dec SC + ! do single-bit divide steps + ! + ! We have to be careful here. We know that R >= V, so we can do the + ! first divide step without thinking. BUT, the others are conditional, + ! and are only done if R >= 0. Because both R and V may have the high- + ! order bit set in the first step, just falling into the regular + ! division loop will mess up the first time around. + ! So we unroll slightly... + LOC(do_single_div): + subcc SC, 1, SC + bl LOC(end_regular_divide) + nop + sub R, V, R + mov 1, Q + b LOC(end_single_divloop) + nop + LOC(single_divloop): + sll Q, 1, Q + bl 1f + srl V, 1, V + ! R >= 0 + sub R, V, R + b 2f + add Q, 1, Q + 1: ! R < 0 + add R, V, R + sub Q, 1, Q + 2: + LOC(end_single_divloop): + subcc SC, 1, SC + bge LOC(single_divloop) + tst R + b,a LOC(end_regular_divide) + +LOC(not_really_big): +1: + sll V, N, V + cmp V, R + bleu 1b + addcc ITER, 1, ITER + be LOC(got_result) + sub ITER, 1, ITER + + tst R ! set up for initial iteration +LOC(divloop): + sll Q, N, Q + DEVELOP_QUOTIENT_BITS(1, 0) +LOC(end_regular_divide): + subcc ITER, 1, ITER + bge LOC(divloop) + tst R + bl,a LOC(got_result) + ! non-restoring fixup here (one instruction only!) +ifelse(OP, `div', +` sub Q, 1, Q +', ` add R, divisor, R +') + +LOC(got_result): +ifelse(S, `true', +` ! check to see if answer should be < 0 + tst SIGN + bl,a 1f + ifelse(OP, `div', `sub %g0, Q, Q', `sub %g0, R, R') +1:') + retl + ifelse(OP, `div', `mov Q, %o0', `mov R, %o0') + +END(NAME) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/dl-irel.h b/REORG.TODO/sysdeps/sparc/sparc32/dl-irel.h new file mode 100644 index 0000000000..56c155e4d5 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/dl-irel.h @@ -0,0 +1,62 @@ +/* Machine-dependent ELF indirect relocation inline functions. + SPARC 32-bit version. + Copyright (C) 2010-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _DL_IREL_H +#define _DL_IREL_H + +#include <stdio.h> +#include <unistd.h> +#include <dl-plt.h> +#include <ldsodefs.h> + +#define ELF_MACHINE_IRELA 1 + +static inline Elf32_Addr +__attribute ((always_inline)) +elf_ifunc_invoke (Elf32_Addr addr) +{ + return ((Elf32_Addr (*) (int)) (addr)) (GLRO(dl_hwcap)); +} + +static inline void +__attribute ((always_inline)) +elf_irela (const Elf32_Rela *reloc) +{ + unsigned int r_type = ELF32_R_TYPE (reloc->r_info); + + if (__glibc_likely (r_type == R_SPARC_IRELATIVE)) + { + Elf32_Addr *const reloc_addr = (void *) reloc->r_offset; + Elf32_Addr value = elf_ifunc_invoke(reloc->r_addend); + *reloc_addr = value; + } + else if (__glibc_likely (r_type == R_SPARC_JMP_IREL)) + { + Elf32_Addr *const reloc_addr = (void *) reloc->r_offset; + Elf32_Addr value = elf_ifunc_invoke(reloc->r_addend); + + sparc_fixup_plt (reloc, reloc_addr, value, 0, 1); + } + else if (r_type == R_SPARC_NONE) + ; + else + __libc_fatal ("unexpected reloc type in static binary"); +} + +#endif /* dl-irel.h */ diff --git a/REORG.TODO/sysdeps/sparc/sparc32/dl-machine.h b/REORG.TODO/sysdeps/sparc/sparc32/dl-machine.h new file mode 100644 index 0000000000..95f673270e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/dl-machine.h @@ -0,0 +1,568 @@ +/* Machine-dependent ELF dynamic relocation inline functions. SPARC version. + Copyright (C) 1996-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef dl_machine_h +#define dl_machine_h + +#define ELF_MACHINE_NAME "sparc" + +#include <string.h> +#include <sys/param.h> +#include <ldsodefs.h> +#include <sysdep.h> +#include <tls.h> +#include <dl-plt.h> +#include <elf/dl-hwcaps.h> + +/* Return nonzero iff ELF header is compatible with the running host. */ +static inline int +elf_machine_matches_host (const Elf32_Ehdr *ehdr) +{ + if (ehdr->e_machine == EM_SPARC) + return 1; + else if (ehdr->e_machine == EM_SPARC32PLUS) + { +#if HAVE_TUNABLES || defined SHARED + uint64_t hwcap_mask = GET_HWCAP_MASK(); + return GLRO(dl_hwcap) & hwcap_mask & HWCAP_SPARC_V9; +#else + return GLRO(dl_hwcap) & HWCAP_SPARC_V9; +#endif + } + else + return 0; +} + +/* We have to do this because elf_machine_{dynamic,load_address} can be + invoked from functions that have no GOT references, and thus the compiler + has no obligation to load the PIC register. */ +#define LOAD_PIC_REG(PIC_REG) \ +do { register Elf32_Addr pc __asm("o7"); \ + __asm("sethi %%hi(_GLOBAL_OFFSET_TABLE_-4), %1\n\t" \ + "call 1f\n\t" \ + "add %1, %%lo(_GLOBAL_OFFSET_TABLE_+4), %1\n" \ + "1:\tadd %1, %0, %1" \ + : "=r" (pc), "=r" (PIC_REG)); \ +} while (0) + +/* Return the link-time address of _DYNAMIC. Conveniently, this is the + first element of the GOT. This must be inlined in a function which + uses global data. */ +static inline Elf32_Addr +elf_machine_dynamic (void) +{ + register Elf32_Addr *got asm ("%l7"); + + LOAD_PIC_REG (got); + + return *got; +} + +/* Return the run-time load address of the shared object. */ +static inline Elf32_Addr +elf_machine_load_address (void) +{ + register Elf32_Addr *pc __asm ("%o7"), *got __asm ("%l7"); + + __asm ("sethi %%hi(_GLOBAL_OFFSET_TABLE_-4), %1\n\t" + "call 1f\n\t" + " add %1, %%lo(_GLOBAL_OFFSET_TABLE_+4), %1\n\t" + "call _DYNAMIC\n\t" + "call _GLOBAL_OFFSET_TABLE_\n" + "1:\tadd %1, %0, %1\n\t" : "=r" (pc), "=r" (got)); + + /* got is now l_addr + _GLOBAL_OFFSET_TABLE_ + *got is _DYNAMIC + pc[2]*4 is l_addr + _DYNAMIC - (long)pc - 8 + pc[3]*4 is l_addr + _GLOBAL_OFFSET_TABLE_ - (long)pc - 12 */ + return (Elf32_Addr) got - *got + (pc[2] - pc[3]) * 4 - 4; +} + +/* Set up the loaded object described by L so its unrelocated PLT + entries will jump to the on-demand fixup code in dl-runtime.c. */ + +static inline int +elf_machine_runtime_setup (struct link_map *l, int lazy, int profile) +{ + Elf32_Addr *plt; + extern void _dl_runtime_resolve (Elf32_Word); + extern void _dl_runtime_profile (Elf32_Word); + + if (l->l_info[DT_JMPREL] && lazy) + { + Elf32_Addr rfunc; + + /* The entries for functions in the PLT have not yet been filled in. + Their initial contents will arrange when called to set the high 22 + bits of %g1 with an offset into the .rela.plt section and jump to + the beginning of the PLT. */ + plt = (Elf32_Addr *) D_PTR (l, l_info[DT_PLTGOT]); + if (__builtin_expect(profile, 0)) + { + rfunc = (Elf32_Addr) &_dl_runtime_profile; + + if (GLRO(dl_profile) != NULL + && _dl_name_match_p (GLRO(dl_profile), l)) + GL(dl_profile_map) = l; + } + else + { + rfunc = (Elf32_Addr) &_dl_runtime_resolve; + } + + /* The beginning of the PLT does: + + sethi %hi(_dl_runtime_{resolve,profile}), %g2 + pltpc: jmpl %g2 + %lo(_dl_runtime_{resolve,profile}), %g2 + nop + .word MAP + + The PC value (pltpc) saved in %g2 by the jmpl points near the + location where we store the link_map pointer for this object. */ + + plt[0] = 0x05000000 | ((rfunc >> 10) & 0x003fffff); + plt[1] = 0x85c0a000 | (rfunc & 0x3ff); + plt[2] = OPCODE_NOP; /* Fill call delay slot. */ + plt[3] = (Elf32_Addr) l; + if (__builtin_expect (l->l_info[VALIDX(DT_GNU_PRELINKED)] != NULL, 0) + || __builtin_expect (l->l_info [VALIDX (DT_GNU_LIBLISTSZ)] != NULL, 0)) + { + /* Need to reinitialize .plt to undo prelinking. */ + Elf32_Rela *rela = (Elf32_Rela *) D_PTR (l, l_info[DT_JMPREL]); + Elf32_Rela *relaend + = (Elf32_Rela *) ((char *) rela + + l->l_info[DT_PLTRELSZ]->d_un.d_val); +#if !defined RTLD_BOOTSTRAP && !defined __sparc_v9__ + /* Note that we don't mask the hwcap here, as the flush is + essential to functionality on those cpu's that implement it. + For sparcv9 we can assume flush is present. */ + const int do_flush = GLRO(dl_hwcap) & HWCAP_SPARC_FLUSH; +#else + const int do_flush = 1; +#endif + + /* prelink must ensure there are no R_SPARC_NONE relocs left + in .rela.plt. */ + while (rela < relaend) + { + *(unsigned int *) (rela->r_offset + l->l_addr) + = OPCODE_SETHI_G1 | (rela->r_offset + l->l_addr + - (Elf32_Addr) plt); + *(unsigned int *) (rela->r_offset + l->l_addr + 4) + = OPCODE_BA | ((((Elf32_Addr) plt + - rela->r_offset - l->l_addr - 4) >> 2) + & 0x3fffff); + if (do_flush) + { + __asm __volatile ("flush %0" : : "r" (rela->r_offset + + l->l_addr)); + __asm __volatile ("flush %0+4" : : "r" (rela->r_offset + + l->l_addr)); + } + ++rela; + } + } + } + + return lazy; +} + +/* ELF_RTYPE_CLASS_PLT iff TYPE describes relocation of a PLT entry, so + PLT entries should not be allowed to define the value. + ELF_RTYPE_CLASS_COPY iff TYPE should not be allowed to resolve to one + of the main executable's symbols, as for a COPY reloc. */ +#define elf_machine_type_class(type) \ + ((((type) == R_SPARC_JMP_SLOT \ + || ((type) >= R_SPARC_TLS_GD_HI22 && (type) <= R_SPARC_TLS_TPOFF64)) \ + * ELF_RTYPE_CLASS_PLT) \ + | (((type) == R_SPARC_COPY) * ELF_RTYPE_CLASS_COPY)) + +/* A reloc type used for ld.so cmdline arg lookups to reject PLT entries. */ +#define ELF_MACHINE_JMP_SLOT R_SPARC_JMP_SLOT + +/* The SPARC never uses Elf32_Rel relocations. */ +#define ELF_MACHINE_NO_REL 1 +#define ELF_MACHINE_NO_RELA 0 + +/* Undo the sub %sp, 6*4, %sp; add %sp, 22*4, %o0 below to get at the + value we want in __libc_stack_end. */ +#define DL_STACK_END(cookie) \ + ((void *) (((long) (cookie)) - (22 - 6) * 4)) + +/* Initial entry point code for the dynamic linker. + The C function `_dl_start' is the real entry point; + its return value is the user program's entry point. */ + +#define RTLD_GOT_ADDRESS(pic_reg, reg, symbol) \ + "sethi %gdop_hix22(" #symbol "), " #reg "\n\t" \ + "xor " #reg ", %gdop_lox10(" #symbol "), " #reg "\n\t" \ + "ld [" #pic_reg " + " #reg "], " #reg ", %gdop(" #symbol ")" + +#define RTLD_START __asm__ ("\ + .text\n\ + .globl _start\n\ + .type _start, @function\n\ + .align 32\n\ +_start:\n\ + /* Allocate space for functions to drop their arguments. */\n\ + sub %sp, 6*4, %sp\n\ + /* Pass pointer to argument block to _dl_start. */\n\ + call _dl_start\n\ + add %sp, 22*4, %o0\n\ + /* FALTHRU */\n\ + .globl _dl_start_user\n\ + .type _dl_start_user, @function\n\ +_dl_start_user:\n\ + /* Load the PIC register. */\n\ +1: call 2f\n\ + sethi %hi(_GLOBAL_OFFSET_TABLE_-(1b-.)), %l7\n\ +2: or %l7, %lo(_GLOBAL_OFFSET_TABLE_-(1b-.)), %l7\n\ + add %l7, %o7, %l7\n\ + /* Save the user entry point address in %l0 */\n\ + mov %o0, %l0\n\ + /* See if we were run as a command with the executable file name as an\n\ + extra leading argument. If so, adjust the contents of the stack. */\n\ + " RTLD_GOT_ADDRESS(%l7, %g2, _dl_skip_args) "\n\ + ld [%g2], %i0\n\ + tst %i0\n\ + beq 3f\n\ + ld [%sp+22*4], %i5 /* load argc */\n\ + /* Find out how far to shift. */\n\ + " RTLD_GOT_ADDRESS(%l7, %l3, _dl_argv) "\n\ + sub %i5, %i0, %i5\n\ + ld [%l3], %l4\n\ + sll %i0, 2, %i2\n\ + st %i5, [%sp+22*4]\n\ + sub %l4, %i2, %l4\n\ + add %sp, 23*4, %i1\n\ + add %i1, %i2, %i2\n\ + st %l4, [%l3]\n\ + /* Copy down argv */\n\ +21: ld [%i2], %i3\n\ + add %i2, 4, %i2\n\ + tst %i3\n\ + st %i3, [%i1]\n\ + bne 21b\n\ + add %i1, 4, %i1\n\ + /* Copy down env */\n\ +22: ld [%i2], %i3\n\ + add %i2, 4, %i2\n\ + tst %i3\n\ + st %i3, [%i1]\n\ + bne 22b\n\ + add %i1, 4, %i1\n\ + /* Copy down auxiliary table. */\n\ +23: ld [%i2], %i3\n\ + ld [%i2+4], %i4\n\ + add %i2, 8, %i2\n\ + tst %i3\n\ + st %i3, [%i1]\n\ + st %i4, [%i1+4]\n\ + bne 23b\n\ + add %i1, 8, %i1\n\ + /* %o0 = _dl_loaded, %o1 = argc, %o2 = argv, %o3 = envp. */\n\ +3: " RTLD_GOT_ADDRESS(%l7, %o0, _rtld_local) "\n\ + add %sp, 23*4, %o2\n\ + sll %i5, 2, %o3\n\ + add %o3, 4, %o3\n\ + mov %i5, %o1\n\ + add %o2, %o3, %o3\n\ + call _dl_init\n\ + ld [%o0], %o0\n\ + /* Pass our finalizer function to the user in %g1. */\n\ + " RTLD_GOT_ADDRESS(%l7, %g1, _dl_fini) "\n\ + /* Jump to the user's entry point and deallocate the extra stack we got. */\n\ + jmp %l0\n\ + add %sp, 6*4, %sp\n\ + .size _dl_start_user, . - _dl_start_user\n\ + .previous"); + +static inline Elf32_Addr +elf_machine_fixup_plt (struct link_map *map, lookup_t t, + const Elf32_Rela *reloc, + Elf32_Addr *reloc_addr, Elf32_Addr value) +{ +#ifdef __sparc_v9__ + /* Sparc v9 can assume flush is always present. */ + const int do_flush = 1; +#else + /* Note that we don't mask the hwcap here, as the flush is essential to + functionality on those cpu's that implement it. */ + const int do_flush = GLRO(dl_hwcap) & HWCAP_SPARC_FLUSH; +#endif + return sparc_fixup_plt (reloc, reloc_addr, value, 1, do_flush); +} + +/* Return the final value of a plt relocation. */ +static inline Elf32_Addr +elf_machine_plt_value (struct link_map *map, const Elf32_Rela *reloc, + Elf32_Addr value) +{ + return value + reloc->r_addend; +} + +#endif /* dl_machine_h */ + +#define ARCH_LA_PLTENTER sparc32_gnu_pltenter +#define ARCH_LA_PLTEXIT sparc32_gnu_pltexit + +#ifdef RESOLVE_MAP + +/* Perform the relocation specified by RELOC and SYM (which is fully resolved). + MAP is the object containing the reloc. */ + +auto inline void +__attribute__ ((always_inline)) +elf_machine_rela (struct link_map *map, const Elf32_Rela *reloc, + const Elf32_Sym *sym, const struct r_found_version *version, + void *const reloc_addr_arg, int skip_ifunc) +{ + Elf32_Addr *const reloc_addr = reloc_addr_arg; +#if !defined RTLD_BOOTSTRAP && !defined RESOLVE_CONFLICT_FIND_MAP + const Elf32_Sym *const refsym = sym; +#endif + Elf32_Addr value; + const unsigned int r_type = ELF32_R_TYPE (reloc->r_info); +#if !defined RESOLVE_CONFLICT_FIND_MAP + struct link_map *sym_map = NULL; +#endif + +#if !defined RTLD_BOOTSTRAP && !defined HAVE_Z_COMBRELOC + /* This is defined in rtld.c, but nowhere in the static libc.a; make the + reference weak so static programs can still link. This declaration + cannot be done when compiling rtld.c (i.e. #ifdef RTLD_BOOTSTRAP) + because rtld.c contains the common defn for _dl_rtld_map, which is + incompatible with a weak decl in the same file. */ + weak_extern (_dl_rtld_map); +#endif + + if (__glibc_unlikely (r_type == R_SPARC_NONE)) + return; + + if (__glibc_unlikely (r_type == R_SPARC_SIZE32)) + { + *reloc_addr = sym->st_size + reloc->r_addend; + return; + } + +#if !defined RTLD_BOOTSTRAP || !defined HAVE_Z_COMBRELOC + if (__glibc_unlikely (r_type == R_SPARC_RELATIVE)) + { +# if !defined RTLD_BOOTSTRAP && !defined HAVE_Z_COMBRELOC + if (map != &_dl_rtld_map) /* Already done in rtld itself. */ +# endif + *reloc_addr += map->l_addr + reloc->r_addend; + return; + } +#endif + +#ifndef RESOLVE_CONFLICT_FIND_MAP + if (__builtin_expect (ELF32_ST_BIND (sym->st_info) == STB_LOCAL, 0) + && sym->st_shndx != SHN_UNDEF) + { + value = map->l_addr; + } + else + { + sym_map = RESOLVE_MAP (&sym, version, r_type); + value = sym_map == NULL ? 0 : sym_map->l_addr + sym->st_value; + } +#else + value = 0; +#endif + + value += reloc->r_addend; /* Assume copy relocs have zero addend. */ + + if (sym != NULL + && __builtin_expect (ELFW(ST_TYPE) (sym->st_info) == STT_GNU_IFUNC, 0) + && __builtin_expect (sym->st_shndx != SHN_UNDEF, 1) + && __builtin_expect (!skip_ifunc, 1)) + { + value = ((Elf32_Addr (*) (int)) value) (GLRO(dl_hwcap)); + } + + switch (r_type) + { +#if !defined RTLD_BOOTSTRAP && !defined RESOLVE_CONFLICT_FIND_MAP + case R_SPARC_COPY: + if (sym == NULL) + /* This can happen in trace mode if an object could not be + found. */ + break; + if (sym->st_size > refsym->st_size + || (GLRO(dl_verbose) && sym->st_size < refsym->st_size)) + { + const char *strtab; + + strtab = (const void *) D_PTR (map, l_info[DT_STRTAB]); + _dl_error_printf ("\ +%s: Symbol `%s' has different size in shared object, consider re-linking\n", + RTLD_PROGNAME, strtab + refsym->st_name); + } + memcpy (reloc_addr_arg, (void *) value, + MIN (sym->st_size, refsym->st_size)); + break; +#endif + case R_SPARC_GLOB_DAT: + case R_SPARC_32: + *reloc_addr = value; + break; + case R_SPARC_IRELATIVE: + value = ((Elf32_Addr (*) (int)) value) (GLRO(dl_hwcap)); + *reloc_addr = value; + break; + case R_SPARC_JMP_IREL: + value = ((Elf32_Addr (*) (int)) value) (GLRO(dl_hwcap)); + /* Fall thru */ + case R_SPARC_JMP_SLOT: + { +#if !defined RTLD_BOOTSTRAP && !defined __sparc_v9__ + /* Note that we don't mask the hwcap here, as the flush is + essential to functionality on those cpu's that implement + it. For sparcv9 we can assume flush is present. */ + const int do_flush = GLRO(dl_hwcap) & HWCAP_SPARC_FLUSH; +#else + /* Unfortunately, this is necessary, so that we can ensure + ld.so will not execute corrupt PLT entry instructions. */ + const int do_flush = 1; +#endif + /* At this point we don't need to bother with thread safety, + so we can optimize the first instruction of .plt out. */ + sparc_fixup_plt (reloc, reloc_addr, value, 0, do_flush); + } + break; +#ifndef RESOLVE_CONFLICT_FIND_MAP + case R_SPARC_TLS_DTPMOD32: + /* Get the information from the link map returned by the + resolv function. */ + if (sym_map != NULL) + *reloc_addr = sym_map->l_tls_modid; + break; + case R_SPARC_TLS_DTPOFF32: + /* During relocation all TLS symbols are defined and used. + Therefore the offset is already correct. */ + *reloc_addr = (sym == NULL ? 0 : sym->st_value) + reloc->r_addend; + break; + case R_SPARC_TLS_TPOFF32: + /* The offset is negative, forward from the thread pointer. */ + /* We know the offset of object the symbol is contained in. + It is a negative value which will be added to the + thread pointer. */ + if (sym != NULL) + { + CHECK_STATIC_TLS (map, sym_map); + *reloc_addr = sym->st_value - sym_map->l_tls_offset + + reloc->r_addend; + } + break; +# ifndef RTLD_BOOTSTRAP + case R_SPARC_TLS_LE_HIX22: + case R_SPARC_TLS_LE_LOX10: + if (sym != NULL) + { + CHECK_STATIC_TLS (map, sym_map); + value = sym->st_value - sym_map->l_tls_offset + + reloc->r_addend; + if (r_type == R_SPARC_TLS_LE_HIX22) + *reloc_addr = (*reloc_addr & 0xffc00000) | ((~value) >> 10); + else + *reloc_addr = (*reloc_addr & 0xffffe000) | (value & 0x3ff) + | 0x1c00; + } + break; +# endif +#endif +#ifndef RTLD_BOOTSTRAP + case R_SPARC_8: + *(char *) reloc_addr = value; + break; + case R_SPARC_16: + *(short *) reloc_addr = value; + break; + case R_SPARC_DISP8: + *(char *) reloc_addr = (value - (Elf32_Addr) reloc_addr); + break; + case R_SPARC_DISP16: + *(short *) reloc_addr = (value - (Elf32_Addr) reloc_addr); + break; + case R_SPARC_DISP32: + *reloc_addr = (value - (Elf32_Addr) reloc_addr); + break; + case R_SPARC_LO10: + *reloc_addr = (*reloc_addr & ~0x3ff) | (value & 0x3ff); + break; + case R_SPARC_WDISP30: + *reloc_addr = ((*reloc_addr & 0xc0000000) + | ((value - (unsigned int) reloc_addr) >> 2)); + break; + case R_SPARC_HI22: + *reloc_addr = (*reloc_addr & 0xffc00000) | (value >> 10); + break; + case R_SPARC_UA16: + ((unsigned char *) reloc_addr_arg) [0] = value >> 8; + ((unsigned char *) reloc_addr_arg) [1] = value; + break; + case R_SPARC_UA32: + ((unsigned char *) reloc_addr_arg) [0] = value >> 24; + ((unsigned char *) reloc_addr_arg) [1] = value >> 16; + ((unsigned char *) reloc_addr_arg) [2] = value >> 8; + ((unsigned char *) reloc_addr_arg) [3] = value; + break; +#endif +#if !defined RTLD_BOOTSTRAP || defined _NDEBUG + default: + _dl_reloc_bad_type (map, r_type, 0); + break; +#endif + } +} + +auto inline void +__attribute__ ((always_inline)) +elf_machine_rela_relative (Elf32_Addr l_addr, const Elf32_Rela *reloc, + void *const reloc_addr_arg) +{ + Elf32_Addr *const reloc_addr = reloc_addr_arg; + *reloc_addr += l_addr + reloc->r_addend; +} + +auto inline void +__attribute__ ((always_inline)) +elf_machine_lazy_rel (struct link_map *map, + Elf32_Addr l_addr, const Elf32_Rela *reloc, + int skip_ifunc) +{ + Elf32_Addr *const reloc_addr = (void *) (l_addr + reloc->r_offset); + const unsigned int r_type = ELF32_R_TYPE (reloc->r_info); + + if (__glibc_likely (r_type == R_SPARC_JMP_SLOT)) + ; + else if (r_type == R_SPARC_JMP_IREL) + { + Elf32_Addr value = map->l_addr + reloc->r_addend; + if (__glibc_likely (!skip_ifunc)) + value = ((Elf32_Addr (*) (int)) value) (GLRO(dl_hwcap)); + sparc_fixup_plt (reloc, reloc_addr, value, 1, 1); + } + else if (r_type == R_SPARC_NONE) + ; + else + _dl_reloc_bad_type (map, r_type, 1); +} + +#endif /* RESOLVE_MAP */ diff --git a/REORG.TODO/sysdeps/sparc/sparc32/dl-plt.h b/REORG.TODO/sysdeps/sparc/sparc32/dl-plt.h new file mode 100644 index 0000000000..0a583713d7 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/dl-plt.h @@ -0,0 +1,100 @@ +/* PLT fixups. Sparc 32-bit version. + Copyright (C) 1996-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _DL_PLT_H +#define _DL_PLT_H + +/* Some SPARC opcodes we need to use for self-modifying code. */ +#define OPCODE_NOP 0x01000000 /* nop */ +#define OPCODE_CALL 0x40000000 /* call ?; add PC-rel word address */ +#define OPCODE_SETHI_G1 0x03000000 /* sethi ?, %g1; add value>>10 */ +#define OPCODE_JMP_G1 0x81c06000 /* jmp %g1+?; add lo 10 bits of value */ +#define OPCODE_SAVE_SP 0x9de3bfa8 /* save %sp, -(16+6)*4, %sp */ +#define OPCODE_BA 0x30800000 /* b,a ?; add PC-rel word address */ +#define OPCODE_BA_PT 0x30480000 /* ba,a,pt %icc, ?; add PC-rel word address */ + +static inline __attribute__ ((always_inline)) Elf32_Addr +sparc_fixup_plt (const Elf32_Rela *reloc, Elf32_Addr *reloc_addr, + Elf32_Addr value, int t, int do_flush) +{ + Elf32_Sword disp; + + /* 't' is '0' if we are resolving this PLT entry for RTLD bootstrap, + in which case we'll be resolving all PLT entries and thus can + optimize by overwriting instructions starting at the first PLT entry + instruction and we need not be mindful of thread safety. + + Otherwise, 't' is '1'. */ + reloc_addr += t; + disp = value - (Elf32_Addr) reloc_addr; + + if (disp >= -0x800000 && disp < 0x800000) + { + unsigned int insn = OPCODE_BA | ((disp >> 2) & 0x3fffff); + +#ifdef __sparc_v9__ + /* On V9 we can do even better by using a branch with + prediction if we fit into the even smaller 19-bit + displacement field. */ + if (disp >= -0x100000 && disp < 0x100000) + insn = OPCODE_BA_PT | ((disp >> 2) & 0x07ffff); +#endif + + /* Even if we are writing just a single branch, we must not + ignore the 't' offset. Consider a case where we have some + PLT slots which can be optimized into a single branch and + some which cannot. Then we can end up with a PLT which looks + like: + + PLT4.0: sethi %(PLT_4_INDEX), %g1 + sethi %(fully_resolved_sym_4), %g1 + jmp %g1 + %lo(fully_resolved_sym_4) + PLT5.0: ba,a fully_resolved_sym_5 + ba,a PLT0.0 + ... + + The delay slot of that jmp must always be either a sethi to + %g1 or a nop. But if we try to place this displacement + branch there, PLT4.0 will jump to fully_resolved_sym_4 for 1 + instruction and then go immediately to + fully_resolved_sym_5. */ + + reloc_addr[0] = insn; + if (do_flush) + __asm __volatile ("flush %0" : : "r"(reloc_addr)); + } + else + { + /* For thread safety, write the instructions from the bottom and + flush before we overwrite the critical "b,a". This of course + need not be done during bootstrapping, since there are no threads. + But we also can't tell if we _can_ use flush, so don't. */ + + reloc_addr[1] = OPCODE_JMP_G1 | (value & 0x3ff); + if (do_flush) + __asm __volatile ("flush %0+4" : : "r"(reloc_addr)); + + reloc_addr[0] = OPCODE_SETHI_G1 | (value >> 10); + if (do_flush) + __asm __volatile ("flush %0" : : "r"(reloc_addr)); + } + + return value; +} + +#endif /* dl-plt.h */ diff --git a/REORG.TODO/sysdeps/sparc/sparc32/dl-trampoline.S b/REORG.TODO/sysdeps/sparc/sparc32/dl-trampoline.S new file mode 100644 index 0000000000..acfc9d9208 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/dl-trampoline.S @@ -0,0 +1,187 @@ +/* PLT trampolines. Sparc 32-bit version. + Copyright (C) 2005-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .text + .align 32 + + /* %g1: PLT offset loaded by PLT entry + * %g2: callers PC, which is PLT0 + 4, and we store the + * link map at PLT0 + 12, therefore we add 8 to get + * the address of the link map + */ + .globl _dl_runtime_resolve + .type _dl_runtime_resolve, @function +_dl_runtime_resolve: + cfi_startproc + + save %sp, -104, %sp + cfi_def_cfa_register(%fp) + cfi_window_save + cfi_register (%o7, %i7) + + ld [%g2 + 8], %o0 + srl %g1, 10, %o1 + call _dl_fixup + sub %o1, 4*12, %o1 + jmp %o0 + restore + + cfi_endproc + + .size _dl_runtime_resolve, .-_dl_runtime_resolve + + /* For the profiling cases we pass in our stack frame + * as the base of the La_sparc32_regs, so it looks + * like: + * %l0 %sp + (0 * 8) + * %l1 %sp + (0 * 8) + 4 + * ... + * %l6 %sp + (3 * 8) + * %l7 %sp + (3 * 8) + 4 + * %i0 %sp + (4 * 8) + * %i1 %sp + (4 * 8) + 4 + * ... + * %i6 %sp + (7 * 8) + * %i7 %sp + (7 * 8) + 4 + * struct_ret_ptr %sp + (8 * 8) + * framesize %sp + (9 * 8) + */ + + .globl _dl_profile_save_regs + .type _dl_profile_save_regs, @function +_dl_profile_save_regs: + cfi_startproc + + std %l0, [%sp + ( 0 * 8)] + std %l2, [%sp + ( 1 * 8)] + std %l4, [%sp + ( 2 * 8)] + std %l6, [%sp + ( 3 * 8)] + std %i0, [%sp + ( 4 * 8)] + std %i2, [%sp + ( 5 * 8)] + std %i4, [%sp + ( 6 * 8)] + std %i6, [%sp + ( 7 * 8)] + ld [%fp + (8 * 8)], %l4 + retl + st %l4, [%sp + (8 * 8)] + + cfi_endproc + + .size _dl_profile_save_regs, .-_dl_profile_save_regs + + /* If we are going to call pltexit, then we must replicate + * the caller's stack frame. + * %o0: PLT resolved function address + */ + .globl _dl_profile_invoke + .type _dl_profile_invoke, @function +_dl_profile_invoke: + cfi_startproc + + add %l0, 7, %l0 + andn %l0, 7, %l0 + add %l0, 2 * 8, %g1 + + sub %sp, %g1, %sp + srl %l0, 3, %l7 + mov %o0, %l1 + mov %i0, %o0 + mov %i1, %o1 + mov %i2, %o2 + mov %i3, %o3 + mov %i4, %o4 + mov %i5, %o5 + cmp %l0, 0 + mov %fp, %l2 + be 2f + add %sp, (11 * 8), %l3 +1: ldd [%l2], %g2 + add %l2, 0x8, %l2 + subcc %l7, 1, %l7 + std %g2, [%l3] + bne 1b + add %l3, 0x8, %l3 + +2: jmpl %l1, %o7 + nop + + std %o0, [%sp + ( 9 * 8)] + std %f0, [%sp + (10 * 8)] + + mov %l5, %o0 + mov %l6, %o1 + add %sp, (11 * 8), %o2 + call _dl_call_pltexit + add %sp, ( 9 * 8), %o3 + + ldd [%sp + ( 9 * 8)], %i0 + ldd [%sp + (10 * 8)], %f0 + + jmpl %i7 + 8, %g0 + restore + + cfi_endproc + + .size _dl_profile_invoke, .-_dl_profile_invoke + + /* %g1: PLT offset loaded by PLT entry + * %g2: callers PC, which is PLT0 + 4, and we store the + * link map at PLT0 + 12, therefore we add 8 to get + * the address of the link map + */ + .align 32 + .globl _dl_runtime_profile + .type _dl_runtime_profile, @function +_dl_runtime_profile: + cfi_startproc + + save %sp, -104, %sp + cfi_def_cfa_register(%fp) + cfi_window_save + cfi_register(%o7, %i7) + + ld [%g2 + 8], %o0 + srl %g1, 10, %o1 + mov %i7, %o2 + sub %o1, 4*12, %o1 + + mov %o0, %l5 + mov %o1, %l6 + + call _dl_profile_save_regs + nop + + mov %sp, %o3 + call _dl_profile_fixup + add %sp, (9 * 8), %o4 + + ld [%sp + (9 * 8)], %l0 + cmp %l0, 0 + bl 1f + nop + + call _dl_profile_invoke + nop + +1: jmp %o0 + restore + + cfi_endproc + + .size _dl_runtime_profile, .-_dl_runtime_profile diff --git a/REORG.TODO/sysdeps/sparc/sparc32/dotmul.S b/REORG.TODO/sysdeps/sparc/sparc32/dotmul.S new file mode 100644 index 0000000000..d497ca672d --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/dotmul.S @@ -0,0 +1,127 @@ +/* + * Signed multiply, from Appendix E of the Sparc Version 8 + * Architecture Manual. + */ + +/* + * Returns %o0 * %o1 in %o1%o0 (i.e., %o1 holds the upper 32 bits of + * the 64-bit product). + * + * This code optimizes short (less than 13-bit) multiplies. + */ + +#include <sysdep.h> + + +ENTRY(.mul) + mov %o0, %y ! multiplier -> Y + andncc %o0, 0xfff, %g0 ! test bits 12..31 + be LOC(mul_shortway) ! if zero, can do it the short way + andcc %g0, %g0, %o4 ! zero the partial product and clear N and V + + /* + * Long multiply. 32 steps, followed by a final shift step. + */ + mulscc %o4, %o1, %o4 ! 1 + mulscc %o4, %o1, %o4 ! 2 + mulscc %o4, %o1, %o4 ! 3 + mulscc %o4, %o1, %o4 ! 4 + mulscc %o4, %o1, %o4 ! 5 + mulscc %o4, %o1, %o4 ! 6 + mulscc %o4, %o1, %o4 ! 7 + mulscc %o4, %o1, %o4 ! 8 + mulscc %o4, %o1, %o4 ! 9 + mulscc %o4, %o1, %o4 ! 10 + mulscc %o4, %o1, %o4 ! 11 + mulscc %o4, %o1, %o4 ! 12 + mulscc %o4, %o1, %o4 ! 13 + mulscc %o4, %o1, %o4 ! 14 + mulscc %o4, %o1, %o4 ! 15 + mulscc %o4, %o1, %o4 ! 16 + mulscc %o4, %o1, %o4 ! 17 + mulscc %o4, %o1, %o4 ! 18 + mulscc %o4, %o1, %o4 ! 19 + mulscc %o4, %o1, %o4 ! 20 + mulscc %o4, %o1, %o4 ! 21 + mulscc %o4, %o1, %o4 ! 22 + mulscc %o4, %o1, %o4 ! 23 + mulscc %o4, %o1, %o4 ! 24 + mulscc %o4, %o1, %o4 ! 25 + mulscc %o4, %o1, %o4 ! 26 + mulscc %o4, %o1, %o4 ! 27 + mulscc %o4, %o1, %o4 ! 28 + mulscc %o4, %o1, %o4 ! 29 + mulscc %o4, %o1, %o4 ! 30 + mulscc %o4, %o1, %o4 ! 31 + mulscc %o4, %o1, %o4 ! 32 + mulscc %o4, %g0, %o4 ! final shift + + ! If %o0 was negative, the result is + ! (%o0 * %o1) + (%o1 << 32)) + ! We fix that here. + +#if 0 + tst %o0 + bge 1f + rd %y, %o0 + + ! %o0 was indeed negative; fix upper 32 bits of result by subtracting + ! %o1 (i.e., return %o4 - %o1 in %o1). + retl + sub %o4, %o1, %o1 + +1: + retl + mov %o4, %o1 +#else + /* Faster code adapted from tege@sics.se's code for umul.S. */ + sra %o0, 31, %o2 ! make mask from sign bit + and %o1, %o2, %o2 ! %o2 = 0 or %o1, depending on sign of %o0 + rd %y, %o0 ! get lower half of product + retl + sub %o4, %o2, %o1 ! subtract compensation + ! and put upper half in place +#endif + +LOC(mul_shortway): + /* + * Short multiply. 12 steps, followed by a final shift step. + * The resulting bits are off by 12 and (32-12) = 20 bit positions, + * but there is no problem with %o0 being negative (unlike above). + */ + mulscc %o4, %o1, %o4 ! 1 + mulscc %o4, %o1, %o4 ! 2 + mulscc %o4, %o1, %o4 ! 3 + mulscc %o4, %o1, %o4 ! 4 + mulscc %o4, %o1, %o4 ! 5 + mulscc %o4, %o1, %o4 ! 6 + mulscc %o4, %o1, %o4 ! 7 + mulscc %o4, %o1, %o4 ! 8 + mulscc %o4, %o1, %o4 ! 9 + mulscc %o4, %o1, %o4 ! 10 + mulscc %o4, %o1, %o4 ! 11 + mulscc %o4, %o1, %o4 ! 12 + mulscc %o4, %g0, %o4 ! final shift + + /* + * %o4 has 20 of the bits that should be in the low part of the + * result; %y has the bottom 12 (as %y's top 12). That is: + * + * %o4 %y + * +----------------+----------------+ + * | -12- | -20- | -12- | -20- | + * +------(---------+------)---------+ + * --hi-- ----low-part---- + * + * The upper 12 bits of %o4 should be sign-extended to form the + * high part of the product (i.e., highpart = %o4 >> 20). + */ + + rd %y, %o5 + sll %o4, 12, %o0 ! shift middle bits left 12 + srl %o5, 20, %o5 ! shift low bits right 20, zero fill at left + or %o5, %o0, %o0 ! construct low part of result + retl + sra %o4, 20, %o1 ! ... and extract high part of result + +END(.mul) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/e_sqrt.c b/REORG.TODO/sysdeps/sparc/sparc32/e_sqrt.c new file mode 100644 index 0000000000..4886b0a615 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/e_sqrt.c @@ -0,0 +1,33 @@ +/* Copyright (C) 1991-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <errno.h> +#include <math.h> + +#ifndef __GNUC__ + #error This file uses GNU C extensions; you must compile with GCC. +#endif + +/* Return the square root of X. */ +double +__ieee754_sqrt (double x) +{ + register double result; + asm ("fsqrtd %1, %0" : "=f" (result) : "f" (x)); + return result; +} +strong_alias (__ieee754_sqrt, __sqrt_finite) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/fpu/e_sqrtl.c b/REORG.TODO/sysdeps/sparc/sparc32/fpu/e_sqrtl.c new file mode 100644 index 0000000000..1592d58849 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/fpu/e_sqrtl.c @@ -0,0 +1,30 @@ +/* Long double square root, sparc32 version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math.h> + +extern long double _Q_sqrt(const long double a); + +long double +__ieee754_sqrtl (long double x) +{ + return _Q_sqrt (x); +} + +#include <shlib-compat.h> +versioned_symbol (libm, __ieee754_sqrtl, __sqrtl_finite, GLIBC_2_23); diff --git a/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_copysign.S b/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_copysign.S new file mode 100644 index 0000000000..bddbfb2386 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_copysign.S @@ -0,0 +1,31 @@ +/* copysign function, sparc32 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__copysign) + sethi %hi(0x80000000), %g1 + and %o2, %g1, %o4 + andn %o0, %g1, %o0 + or %o0, %o4, %o0 + std %o0, [%sp + 72] + retl + ldd [%sp + 72], %f0 +END (__copysign) +weak_alias (__copysign, copysign)
\ No newline at end of file diff --git a/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_copysignf.S b/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_copysignf.S new file mode 100644 index 0000000000..f2e78962a9 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_copysignf.S @@ -0,0 +1,31 @@ +/* float copysign function, sparc32 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__copysignf) + sethi %hi(0x80000000), %g1 + and %o1, %g1, %o4 + andn %o0, %g1, %o0 + or %o0, %o4, %o0 + st %o0, [%sp + 68] + retl + ld [%sp + 68], %f0 +END (__copysignf) +weak_alias (__copysignf, copysignf)
\ No newline at end of file diff --git a/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_fabs.S b/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_fabs.S new file mode 100644 index 0000000000..fdeda68898 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_fabs.S @@ -0,0 +1,28 @@ +/* Float absolute value, sparc32 version. + Copyright (C) 2011-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__fabs) + st %o0, [%sp+72] + st %o1, [%sp+76] + ldd [%sp+72], %f0 + retl + fabss %f0, %f0 +END (__fabs) +weak_alias (__fabs, fabs) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_fabsf.S b/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_fabsf.S new file mode 100644 index 0000000000..12ac9de5c8 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_fabsf.S @@ -0,0 +1,28 @@ +/* Float absolute value, sparc32 version. + Copyright (C) 2006-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jakub@redhat.com>, 2006. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__fabsf) + st %o0, [%sp+68] + ld [%sp+68], %f0 + retl + fabss %f0, %f0 +END (__fabsf) +weak_alias (__fabsf, fabsf) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_fabsl.c b/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_fabsl.c new file mode 100644 index 0000000000..3c03b92828 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_fabsl.c @@ -0,0 +1,8 @@ +#include <math.h> +#include <math_ldbl_opt.h> + +long double __fabsl (long double x) +{ + return __builtin_fabsl (x); +} +long_double_symbol (libm, __fabsl, fabsl); diff --git a/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_fma.c b/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_fma.c new file mode 100644 index 0000000000..8f62605870 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_fma.c @@ -0,0 +1,2 @@ +/* Always use dbl-64 version because long double is emulated in software. */ +#include <sysdeps/ieee754/dbl-64/s_fma.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_signbit.S b/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_signbit.S new file mode 100644 index 0000000000..956517022f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_signbit.S @@ -0,0 +1,30 @@ +/* signbit(). sparc32 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__signbit) + retl + srl %o0, 31, %o0 +END (__signbit) + +/* On 32-bit the double version will also always work for + single-precision since in both cases the word with the + sign bit in it is passed always in register %o0. */ +strong_alias (__signbit, __signbitf) +hidden_def (__signbitf) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_signbitf.S b/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_signbitf.S new file mode 100644 index 0000000000..91886af6d5 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_signbitf.S @@ -0,0 +1 @@ +/* signbitf is implemented in s_signbit.S */
\ No newline at end of file diff --git a/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_signbitl.S b/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_signbitl.S new file mode 100644 index 0000000000..5688186d39 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/fpu/s_signbitl.S @@ -0,0 +1,32 @@ +/* signbitl(). sparc32 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <math_ldbl_opt.h> + +ENTRY (___signbitl) + ld [%o0], %o1 + retl + srl %o1, 31, %o0 +END (___signbitl) + +#if IS_IN (libm) +long_double_symbol (libm, ___signbitl, __signbitl); +#else +long_double_symbol (libc, ___signbitl, __signbitl); +#endif diff --git a/REORG.TODO/sysdeps/sparc/sparc32/fpu/w_sqrt_compat.S b/REORG.TODO/sysdeps/sparc/sparc32/fpu/w_sqrt_compat.S new file mode 100644 index 0000000000..703f228766 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/fpu/w_sqrt_compat.S @@ -0,0 +1,53 @@ +/* sqrt function. sparc32 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__sqrt) + clr %g1 + std %g0, [%sp + 72] + std %o0, [%sp + 80] + ldd [%sp + 72], %f8 + ldd [%sp + 80], %f0 + fcmpd %f0, %f8 + fbl 1f + nop +8: retl + fsqrtd %f0, %f0 +1: +#ifdef SHARED + SETUP_PIC_REG_LEAF(o5, g1) + sethi %gdop_hix22(_LIB_VERSION), %g1 + xor %g1, %gdop_lox10(_LIB_VERSION), %g1 + ld [%o5 + %g1], %g1, %gdop(_LIB_VERSION) +#else + sethi %hi(_LIB_VERSION), %g1 + or %g1, %lo(_LIB_VERSION), %g1 +#endif + ld [%g1], %g1 + cmp %g1, -1 + be 8b + mov %o0, %o2 + mov %o1, %o3 + mov 26, %o4 + mov %o7, %g1 + call __kernel_standard + mov %g1, %o7 +END (__sqrt) + +weak_alias (__sqrt, sqrt) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/fpu/w_sqrtf_compat.S b/REORG.TODO/sysdeps/sparc/sparc32/fpu/w_sqrtf_compat.S new file mode 100644 index 0000000000..05d1160378 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/fpu/w_sqrtf_compat.S @@ -0,0 +1,51 @@ +/* sqrtf function. sparc32 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__sqrtf) + st %g0, [%sp + 68] + st %o0, [%sp + 72] + ld [%sp + 68], %f8 + ld [%sp + 72], %f0 + fcmps %f0, %f8 + fbl 1f + nop +8: retl + fsqrts %f0, %f0 +1: +#ifdef SHARED + SETUP_PIC_REG_LEAF(o5, g1) + sethi %gdop_hix22(_LIB_VERSION), %g1 + xor %g1, %gdop_lox10(_LIB_VERSION), %g1 + ld [%o5 + %g1], %g1, %gdop(_LIB_VERSION) +#else + sethi %hi(_LIB_VERSION), %g1 + or %g1, %lo(_LIB_VERSION), %g1 +#endif + ld [%g1], %g1 + cmp %g1, -1 + be 8b + mov %o0, %o1 + mov 126, %o2 + mov %o7, %g1 + call __kernel_standard_f + mov %g1, %o7 +END (__sqrtf) + +weak_alias (__sqrtf, sqrtf) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/ieee754.h b/REORG.TODO/sysdeps/sparc/sparc32/ieee754.h new file mode 100644 index 0000000000..94662a350f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/ieee754.h @@ -0,0 +1,170 @@ +/* Copyright (C) 1992-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _IEEE754_H + +#define _IEEE754_H 1 +#include <features.h> + +#include <endian.h> + +__BEGIN_DECLS + +union ieee754_float + { + float f; + + /* This is the IEEE 754 single-precision format. */ + struct + { +#if __BYTE_ORDER == __BIG_ENDIAN + unsigned int negative:1; + unsigned int exponent:8; + unsigned int mantissa:23; +#endif /* Big endian. */ +#if __BYTE_ORDER == __LITTLE_ENDIAN + unsigned int mantissa:23; + unsigned int exponent:8; + unsigned int negative:1; +#endif /* Little endian. */ + } ieee; + + /* This format makes it easier to see if a NaN is a signalling NaN. */ + struct + { +#if __BYTE_ORDER == __BIG_ENDIAN + unsigned int negative:1; + unsigned int exponent:8; + unsigned int quiet_nan:1; + unsigned int mantissa:22; +#endif /* Big endian. */ +#if __BYTE_ORDER == __LITTLE_ENDIAN + unsigned int mantissa:22; + unsigned int quiet_nan:1; + unsigned int exponent:8; + unsigned int negative:1; +#endif /* Little endian. */ + } ieee_nan; + }; + +#define IEEE754_FLOAT_BIAS 0x7f /* Added to exponent. */ + + +union ieee754_double + { + double d; + + /* This is the IEEE 754 double-precision format. */ + struct + { +#if __BYTE_ORDER == __BIG_ENDIAN + unsigned int negative:1; + unsigned int exponent:11; + /* Together these comprise the mantissa. */ + unsigned int mantissa0:20; + unsigned int mantissa1:32; +#endif /* Big endian. */ +#if __BYTE_ORDER == __LITTLE_ENDIAN + /* Together these comprise the mantissa. */ + unsigned int mantissa1:32; + unsigned int mantissa0:20; + unsigned int exponent:11; + unsigned int negative:1; +#endif /* Little endian. */ + } ieee; + + /* This format makes it easier to see if a NaN is a signalling NaN. */ + struct + { +#if __BYTE_ORDER == __BIG_ENDIAN + unsigned int negative:1; + unsigned int exponent:11; + unsigned int quiet_nan:1; + /* Together these comprise the mantissa. */ + unsigned int mantissa0:19; + unsigned int mantissa1:32; +#else + /* Together these comprise the mantissa. */ + unsigned int mantissa1:32; + unsigned int mantissa0:19; + unsigned int quiet_nan:1; + unsigned int exponent:11; + unsigned int negative:1; +#endif + } ieee_nan; + }; + +#define IEEE754_DOUBLE_BIAS 0x3ff /* Added to exponent. */ + + +union ieee854_long_double + { + long double d; + + /* This is the IEEE 854 quad-precision format. */ + struct + { +#if __BYTE_ORDER == __BIG_ENDIAN + unsigned int negative:1; + unsigned int exponent:15; + /* Together these comprise the mantissa. */ + unsigned int mantissa0:16; + unsigned int mantissa1:32; + unsigned int mantissa2:32; + unsigned int mantissa3:32; +#endif /* Big endian. */ +#if __BYTE_ORDER == __LITTLE_ENDIAN + /* Together these comprise the mantissa. */ + unsigned int mantissa3:32; + unsigned int mantissa2:32; + unsigned int mantissa1:32; + unsigned int mantissa0:16; + unsigned int exponent:15; + unsigned int negative:1; +#endif /* Little endian. */ + } ieee; + + /* This format makes it easier to see if a NaN is a signalling NaN. */ + struct + { +#if __BYTE_ORDER == __BIG_ENDIAN + unsigned int negative:1; + unsigned int exponent:15; + unsigned int quiet_nan:1; + /* Together these comprise the mantissa. */ + unsigned int mantissa0:15; + unsigned int mantissa1:32; + unsigned int mantissa2:32; + unsigned int mantissa3:32; +#else + /* Together these comprise the mantissa. */ + unsigned int mantissa3:32; + unsigned int mantissa2:32; + unsigned int mantissa1:32; + unsigned int mantissa0:15; + unsigned int quiet_nan:1; + unsigned int exponent:15; + unsigned int negative:1; +#endif + } ieee_nan; + }; + +#define IEEE854_LONG_DOUBLE_BIAS 0x3fff /* Added to exponent. */ + +__END_DECLS + +#endif /* ieee754.h */ diff --git a/REORG.TODO/sysdeps/sparc/sparc32/jmpbuf-offsets.h b/REORG.TODO/sysdeps/sparc/sparc32/jmpbuf-offsets.h new file mode 100644 index 0000000000..679c1fa595 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/jmpbuf-offsets.h @@ -0,0 +1,21 @@ +/* Private macros for accessing __jmp_buf contents. SPARC version. + Copyright (C) 2006-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#define JB_SP 0 +#define JB_FP 1 +#define JB_PC 2 diff --git a/REORG.TODO/sysdeps/sparc/sparc32/jmpbuf-unwind.h b/REORG.TODO/sysdeps/sparc/sparc32/jmpbuf-unwind.h new file mode 100644 index 0000000000..b497febd91 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/jmpbuf-unwind.h @@ -0,0 +1,47 @@ +/* Copyright (C) 2003-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jakub@redhat.com>, 2003. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <setjmp.h> +#include <jmpbuf-offsets.h> +#include <stdint.h> +#include <unwind.h> +#include <sysdep.h> + +/* Test if longjmp to JMPBUF would unwind the frame + containing a local variable at ADDRESS. */ +#define _JMPBUF_UNWINDS(jmpbuf, address, demangle) \ + ((int) (address) < demangle ((jmpbuf)[JB_SP])) + +#define _JMPBUF_CFA_UNWINDS_ADJ(_jmpbuf, _context, _adj) \ + _JMPBUF_UNWINDS_ADJ (_jmpbuf, (void *) _Unwind_GetCFA (_context), _adj) + +static inline uintptr_t __attribute__ ((unused)) +_jmpbuf_sp (__jmp_buf regs) +{ + uintptr_t sp = regs[JB_SP]; +#ifdef PTR_DEMANGLE + PTR_DEMANGLE (sp); +#endif + return sp; +} + +#define _JMPBUF_UNWINDS_ADJ(_jmpbuf, _address, _adj) \ + ((uintptr_t) (_address) - (_adj) < _jmpbuf_sp (_jmpbuf) - (_adj)) + +/* We use the normal lobngjmp for unwinding. */ +#define __libc_unwind_longjmp(buf, val) __libc_longjmp (buf, val) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/lll_timedlock_wait.c b/REORG.TODO/sysdeps/sparc/sparc32/lll_timedlock_wait.c new file mode 100644 index 0000000000..c2c93faf1b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/lll_timedlock_wait.c @@ -0,0 +1 @@ +/* __lll_timedlock_wait is in lowlevellock.c. */ diff --git a/REORG.TODO/sysdeps/sparc/sparc32/lll_timedwait_tid.c b/REORG.TODO/sysdeps/sparc/sparc32/lll_timedwait_tid.c new file mode 100644 index 0000000000..511608ead9 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/lll_timedwait_tid.c @@ -0,0 +1 @@ +/* __lll_timedwait_tid is in lowlevellock.c. */ diff --git a/REORG.TODO/sysdeps/sparc/sparc32/lowlevellock.c b/REORG.TODO/sysdeps/sparc/sparc32/lowlevellock.c new file mode 100644 index 0000000000..e502bf6f25 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/lowlevellock.c @@ -0,0 +1,131 @@ +/* low level locking for pthread library. SPARC version. + Copyright (C) 2003-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <errno.h> +#include <sysdep.h> +#include <lowlevellock.h> +#include <sys/time.h> + + +void +__lll_lock_wait_private (int *futex) +{ + do + { + int oldval = atomic_compare_and_exchange_val_24_acq (futex, 2, 1); + if (oldval != 0) + lll_futex_wait (futex, 2, LLL_PRIVATE); + } + while (atomic_compare_and_exchange_val_24_acq (futex, 2, 0) != 0); +} + + +/* These functions don't get included in libc.so */ +#if IS_IN (libpthread) +void +__lll_lock_wait (int *futex, int private) +{ + do + { + int oldval = atomic_compare_and_exchange_val_24_acq (futex, 2, 1); + if (oldval != 0) + lll_futex_wait (futex, 2, private); + } + while (atomic_compare_and_exchange_val_24_acq (futex, 2, 0) != 0); +} + + +int +__lll_timedlock_wait (int *futex, const struct timespec *abstime, int private) +{ + /* Reject invalid timeouts. */ + if (abstime->tv_nsec < 0 || abstime->tv_nsec >= 1000000000) + return EINVAL; + + do + { + struct timeval tv; + struct timespec rt; + + /* Get the current time. */ + (void) __gettimeofday (&tv, NULL); + + /* Compute relative timeout. */ + rt.tv_sec = abstime->tv_sec - tv.tv_sec; + rt.tv_nsec = abstime->tv_nsec - tv.tv_usec * 1000; + if (rt.tv_nsec < 0) + { + rt.tv_nsec += 1000000000; + --rt.tv_sec; + } + + /* Already timed out? */ + if (rt.tv_sec < 0) + return ETIMEDOUT; + + /* Wait. */ + int oldval = atomic_compare_and_exchange_val_24_acq (futex, 2, 1); + if (oldval != 0) + lll_futex_timed_wait (futex, 2, &rt, private); + } + while (atomic_compare_and_exchange_val_24_acq (futex, 2, 0) != 0); + + return 0; +} + + +int +__lll_timedwait_tid (int *tidp, const struct timespec *abstime) +{ + int tid; + + if (abstime->tv_nsec < 0 || abstime->tv_nsec >= 1000000000) + return EINVAL; + + /* Repeat until thread terminated. */ + while ((tid = *tidp) != 0) + { + struct timeval tv; + struct timespec rt; + + /* Get the current time. */ + (void) __gettimeofday (&tv, NULL); + + /* Compute relative timeout. */ + rt.tv_sec = abstime->tv_sec - tv.tv_sec; + rt.tv_nsec = abstime->tv_nsec - tv.tv_usec * 1000; + if (rt.tv_nsec < 0) + { + rt.tv_nsec += 1000000000; + --rt.tv_sec; + } + + /* Already timed out? */ + if (rt.tv_sec < 0) + return ETIMEDOUT; + + /* Wait until thread terminates. The kernel so far does not use + the private futex operations for this. */ + if (lll_futex_timed_wait (tidp, tid, &rt, LLL_SHARED) == -ETIMEDOUT) + return ETIMEDOUT; + } + + return 0; +} +#endif diff --git a/REORG.TODO/sysdeps/sparc/sparc32/lshift.S b/REORG.TODO/sysdeps/sparc/sparc32/lshift.S new file mode 100644 index 0000000000..5deebdba41 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/lshift.S @@ -0,0 +1,96 @@ +! Sparc __mpn_lshift -- +! +! Copyright (C) 1995-2017 Free Software Foundation, Inc. +! +! This file is part of the GNU MP Library. +! +! The GNU MP Library is free software; you can redistribute it and/or modify +! it under the terms of the GNU Lesser General Public License as published by +! the Free Software Foundation; either version 2.1 of the License, or (at your +! option) any later version. +! +! The GNU MP Library is distributed in the hope that it will be useful, but +! WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +! or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +! License for more details. +! +! You should have received a copy of the GNU Lesser General Public License +! along with the GNU MP Library; see the file COPYING.LIB. If not, +! see <http://www.gnu.org/licenses/>. + + +! INPUT PARAMETERS +! RES_PTR %o0 +! SRC_PTR %o1 +! SIZE %o2 +! CNT %o3 + +#include <sysdep.h> + +ENTRY(__mpn_lshift) + sll %o2,2,%g1 + add %o1,%g1,%o1 ! make %o1 point at end of src + ld [%o1-4],%g2 ! load first limb + sub %g0,%o3,%o5 ! negate shift count + add %o0,%g1,%o0 ! make %o0 point at end of res + add %o2,-1,%o2 + andcc %o2,4-1,%g4 ! number of limbs in first loop + srl %g2,%o5,%g1 ! compute function result + be LOC(0) ! if multiple of 4 limbs, skip first loop + st %g1,[%sp+80] + + sub %o2,%g4,%o2 ! adjust count for main loop + +LOC(loop0): + ld [%o1-8],%g3 + add %o0,-4,%o0 + add %o1,-4,%o1 + addcc %g4,-1,%g4 + sll %g2,%o3,%o4 + srl %g3,%o5,%g1 + mov %g3,%g2 + or %o4,%g1,%o4 + bne LOC(loop0) + st %o4,[%o0+0] + +LOC(0): tst %o2 + be LOC(end) + nop + +LOC(loop): + ld [%o1-8],%g3 + add %o0,-16,%o0 + addcc %o2,-4,%o2 + sll %g2,%o3,%o4 + srl %g3,%o5,%g1 + + ld [%o1-12],%g2 + sll %g3,%o3,%g4 + or %o4,%g1,%o4 + st %o4,[%o0+12] + srl %g2,%o5,%g1 + + ld [%o1-16],%g3 + sll %g2,%o3,%o4 + or %g4,%g1,%g4 + st %g4,[%o0+8] + srl %g3,%o5,%g1 + + ld [%o1-20],%g2 + sll %g3,%o3,%g4 + or %o4,%g1,%o4 + st %o4,[%o0+4] + srl %g2,%o5,%g1 + + add %o1,-16,%o1 + or %g4,%g1,%g4 + bne LOC(loop) + st %g4,[%o0+0] + +LOC(end): + sll %g2,%o3,%g2 + st %g2,[%o0-4] + retl + ld [%sp+80],%o0 + +END(__mpn_lshift) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/memchr.S b/REORG.TODO/sysdeps/sparc/sparc32/memchr.S new file mode 100644 index 0000000000..d00e2fef46 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/memchr.S @@ -0,0 +1,142 @@ +/* memchr (str, ch, n) -- Return pointer to first occurrence of CH in STR less + than N. + For SPARC v7. + Copyright (C) 1996-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jj@ultra.linux.cz> and + David S. Miller <davem@caip.rutgers.edu>. + This version is developed using the same algorithm as the fast C + version which carries the following introduction: + Based on strlen implementation by Torbjorn Granlund (tege@sics.se), + with help from Dan Sahlin (dan@sics.se) and + commentary by Jim Blandy (jimb@ai.mit.edu); + adaptation to memchr suggested by Dick Karpinski (dick@cca.ucsf.edu), + and implemented by Roland McGrath (roland@ai.mit.edu). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .text + .align 4 +ENTRY(__memchr) + andcc %o1, 0xff, %o1 + sll %o1, 8, %g6 + andcc %o0, 3, %g0 + or %o1, %g6, %g6 + sll %g6, 16, %o3 + be 10f + or %o3, %g6, %g2 + cmp %o2, 0 + be 9f + sethi %hi(0x80808080), %o4 + ldub [%o0], %g4 + cmp %g4, %o1 + be 1f + add %o0, 1, %o0 + subcc %o2, 1, %o2 + be 9f + andcc %o0, 3, %g0 + be 4f + or %o4, %lo(0x80808080), %o3 + ldub [%o0], %g4 + cmp %g4, %o1 + be 1f + add %o0, 1, %o0 + subcc %o2, 1, %o2 + be 9f + andcc %o0, 3, %g0 + be 5f + sethi %hi(0x01010101), %o5 + ldub [%o0], %g4 + cmp %g4, %o1 + be 1f + add %o0, 1, %o0 + subcc %o2, 1, %o2 + bne,a 7f + and %o2, 3, %g1 + retl + clr %o0 +1: retl + sub %o0, 1, %o0 +10: sethi %hi(0x80808080), %o4 + or %o4, %lo(0x80808080), %o3 +4: sethi %hi(0x01010101), %o5 +5: and %o2, 3, %g1 +7: andcc %o2, 0xfffffffc, %o2 + be 0f + or %o5, %lo(0x01010101), %g6 + ld [%o0], %g4 +6: xor %g4, %g2, %g5 + add %o0, 4, %o0 + sub %g5, %g6, %g5 + andcc %g5, %o3, %g0 + bne 8f + subcc %o2, 4, %o2 + bne,a 6b + ld [%o0], %g4 +0: cmp %g1, 0 +1: be 9f + add %o0, 4, %o0 + ldub [%o0 - 4], %g4 + cmp %g4, %o1 + be 4f + cmp %g1, 1 + be 9f + ldub [%o0 - 3], %g4 + cmp %g4, %o1 + be 3f + cmp %g1, 2 + be 9f + ldub [%o0 - 2], %g4 + cmp %g4, %o1 + be 2f + nop +9: retl + clr %o0 + + /* Check every byte. */ +8: srl %g4, 24, %g5 + and %g5, 0xff, %g5 + cmp %g5, %o1 + be 4f + srl %g4, 16, %g5 + and %g5, 0xff, %g5 + cmp %g5, %o1 + be 3f + srl %g4, 8, %g5 + and %g5, 0xff, %g5 + cmp %g5, %o1 + be 2f + and %g4, 0xff, %g5 + cmp %g5, %o1 + be 1f + cmp %o2, 0 + bne,a 6b + ld [%o0], %g4 + b 1b + cmp %g1, 0 +1: retl + sub %o0, 1, %o0 +2: retl + sub %o0, 2, %o0 +3: retl + sub %o0, 3, %o0 +4: retl + sub %o0, 4, %o0 +END(__memchr) + +weak_alias (__memchr, memchr) +libc_hidden_builtin_def (memchr) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/memcpy.S b/REORG.TODO/sysdeps/sparc/sparc32/memcpy.S new file mode 100644 index 0000000000..da672bd120 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/memcpy.S @@ -0,0 +1,653 @@ +/* Copy SIZE bytes from SRC to DEST. + For SPARC v7. + Copyright (C) 1996-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@caip.rutgers.edu>, + Eddie C. Dost <ecd@skynet.be> and + Jakub Jelinek <jj@ultra.linux.cz>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +/* Both these macros have to start with exactly the same insn */ +#define MOVE_BIGCHUNK(src, dst, offset, t0, t1, t2, t3, t4, t5, t6, t7) \ + ldd [%src + offset + 0x00], %t0; \ + ldd [%src + offset + 0x08], %t2; \ + ldd [%src + offset + 0x10], %t4; \ + ldd [%src + offset + 0x18], %t6; \ + st %t0, [%dst + offset + 0x00]; \ + st %t1, [%dst + offset + 0x04]; \ + st %t2, [%dst + offset + 0x08]; \ + st %t3, [%dst + offset + 0x0c]; \ + st %t4, [%dst + offset + 0x10]; \ + st %t5, [%dst + offset + 0x14]; \ + st %t6, [%dst + offset + 0x18]; \ + st %t7, [%dst + offset + 0x1c]; + +#define MOVE_BIGALIGNCHUNK(src, dst, offset, t0, t1, t2, t3, t4, t5, t6, t7) \ + ldd [%src + offset + 0x00], %t0; \ + ldd [%src + offset + 0x08], %t2; \ + ldd [%src + offset + 0x10], %t4; \ + ldd [%src + offset + 0x18], %t6; \ + std %t0, [%dst + offset + 0x00]; \ + std %t2, [%dst + offset + 0x08]; \ + std %t4, [%dst + offset + 0x10]; \ + std %t6, [%dst + offset + 0x18]; + +#define MOVE_LASTCHUNK(src, dst, offset, t0, t1, t2, t3) \ + ldd [%src - offset - 0x10], %t0; \ + ldd [%src - offset - 0x08], %t2; \ + st %t0, [%dst - offset - 0x10]; \ + st %t1, [%dst - offset - 0x0c]; \ + st %t2, [%dst - offset - 0x08]; \ + st %t3, [%dst - offset - 0x04]; + +#define MOVE_LASTALIGNCHUNK(src, dst, offset, t0, t1, t2, t3) \ + ldd [%src - offset - 0x10], %t0; \ + ldd [%src - offset - 0x08], %t2; \ + std %t0, [%dst - offset - 0x10]; \ + std %t2, [%dst - offset - 0x08]; + +#define MOVE_SHORTCHUNK(src, dst, offset, t0, t1) \ + ldub [%src - offset - 0x02], %t0; \ + ldub [%src - offset - 0x01], %t1; \ + stb %t0, [%dst - offset - 0x02]; \ + stb %t1, [%dst - offset - 0x01]; + +#define SMOVE_CHUNK(src, dst, offset, t0, t1, t2, t3, t4, t5, t6, prev, shil, shir, offset2) \ + ldd [%src + offset + 0x00], %t0; \ + ldd [%src + offset + 0x08], %t2; \ + srl %t0, shir, %t5; \ + srl %t1, shir, %t6; \ + sll %t0, shil, %t0; \ + or %t5, %prev, %t5; \ + sll %t1, shil, %prev; \ + or %t6, %t0, %t0; \ + srl %t2, shir, %t1; \ + srl %t3, shir, %t6; \ + sll %t2, shil, %t2; \ + or %t1, %prev, %t1; \ + std %t4, [%dst + offset + offset2 - 0x04]; \ + std %t0, [%dst + offset + offset2 + 0x04]; \ + sll %t3, shil, %prev; \ + or %t6, %t2, %t4; + +#define SMOVE_ALIGNCHUNK(src, dst, offset, t0, t1, t2, t3, t4, t5, t6, prev, shil, shir, offset2) \ + ldd [%src + offset + 0x00], %t0; \ + ldd [%src + offset + 0x08], %t2; \ + srl %t0, shir, %t4; \ + srl %t1, shir, %t5; \ + sll %t0, shil, %t6; \ + or %t4, %prev, %t0; \ + sll %t1, shil, %prev; \ + or %t5, %t6, %t1; \ + srl %t2, shir, %t4; \ + srl %t3, shir, %t5; \ + sll %t2, shil, %t6; \ + or %t4, %prev, %t2; \ + sll %t3, shil, %prev; \ + or %t5, %t6, %t3; \ + std %t0, [%dst + offset + offset2 + 0x00]; \ + std %t2, [%dst + offset + offset2 + 0x08]; + + .text +ENTRY(__mempcpy) + add %o0, %o2, %g1 + ba 101f + st %g1, [%sp + 64] +END(__mempcpy) + + .align 4 +ENTRY(memcpy) /* %o0=dst %o1=src %o2=len */ + st %o0, [%sp + 64] +101: + sub %o0, %o1, %o4 +9: andcc %o4, 3, %o5 +0: bne 86f + cmp %o2, 15 + + bleu 90f + andcc %o1, 3, %g0 + + be 78f + andcc %o1, 4, %g0 + + andcc %o1, 1, %g0 + be 4f + andcc %o1, 2, %g0 + + ldub [%o1], %g2 + add %o1, 1, %o1 + stb %g2, [%o0] + sub %o2, 1, %o2 + bne 77f + add %o0, 1, %o0 +4: lduh [%o1], %g2 + add %o1, 2, %o1 + sth %g2, [%o0] + sub %o2, 2, %o2 + add %o0, 2, %o0 + +77: andcc %o1, 4, %g0 +78: be 2f + mov %o2, %g1 + + ld [%o1], %o4 + sub %g1, 4, %g1 + st %o4, [%o0] + add %o1, 4, %o1 + add %o0, 4, %o0 +2: andcc %g1, 0xffffff80, %g6 + be 3f + andcc %o0, 4, %g0 + + be 82f + 4 +5: MOVE_BIGCHUNK(o1, o0, 0x00, o2, o3, o4, o5, g2, g3, g4, g5) + MOVE_BIGCHUNK(o1, o0, 0x20, o2, o3, o4, o5, g2, g3, g4, g5) + MOVE_BIGCHUNK(o1, o0, 0x40, o2, o3, o4, o5, g2, g3, g4, g5) + MOVE_BIGCHUNK(o1, o0, 0x60, o2, o3, o4, o5, g2, g3, g4, g5) + subcc %g6, 128, %g6 + add %o1, 128, %o1 + bne 5b + add %o0, 128, %o0 +3: andcc %g1, 0x70, %g6 + be 80f + andcc %g1, 8, %g0 + + srl %g6, 1, %o4 + mov %o7, %g2 + add %g6, %o4, %o4 + add %o1, %g6, %o1 +104: call 100f + add %o0, %g6, %o0 + jmpl %o5 + (80f - 104b), %g0 + mov %g2, %o7 + +79: MOVE_LASTCHUNK(o1, o0, 0x60, g2, g3, g4, g5) + MOVE_LASTCHUNK(o1, o0, 0x50, g2, g3, g4, g5) + MOVE_LASTCHUNK(o1, o0, 0x40, g2, g3, g4, g5) + MOVE_LASTCHUNK(o1, o0, 0x30, g2, g3, g4, g5) + MOVE_LASTCHUNK(o1, o0, 0x20, g2, g3, g4, g5) + MOVE_LASTCHUNK(o1, o0, 0x10, g2, g3, g4, g5) + MOVE_LASTCHUNK(o1, o0, 0x00, g2, g3, g4, g5) + +80: be 81f + andcc %g1, 4, %g0 + + ldd [%o1], %g2 + add %o0, 8, %o0 + st %g2, [%o0 - 0x08] + add %o1, 8, %o1 + st %g3, [%o0 - 0x04] + +81: be 1f + andcc %g1, 2, %g0 + + ld [%o1], %g2 + add %o1, 4, %o1 + st %g2, [%o0] + add %o0, 4, %o0 +1: be 1f + andcc %g1, 1, %g0 + + lduh [%o1], %g2 + add %o1, 2, %o1 + sth %g2, [%o0] + add %o0, 2, %o0 +1: be 1f + nop + + ldub [%o1], %g2 + stb %g2, [%o0] +1: retl + ld [%sp + 64], %o0 + +82: /* ldd_std */ + MOVE_BIGALIGNCHUNK(o1, o0, 0x00, o2, o3, o4, o5, g2, g3, g4, g5) + MOVE_BIGALIGNCHUNK(o1, o0, 0x20, o2, o3, o4, o5, g2, g3, g4, g5) + MOVE_BIGALIGNCHUNK(o1, o0, 0x40, o2, o3, o4, o5, g2, g3, g4, g5) + MOVE_BIGALIGNCHUNK(o1, o0, 0x60, o2, o3, o4, o5, g2, g3, g4, g5) + subcc %g6, 128, %g6 + add %o1, 128, %o1 + bne 82b + add %o0, 128, %o0 + + andcc %g1, 0x70, %g6 + be 84f + andcc %g1, 8, %g0 + + mov %o7, %g2 +111: call 110f + add %o1, %g6, %o1 + mov %g2, %o7 + jmpl %o5 + (84f - 111b), %g0 + add %o0, %g6, %o0 + +83: MOVE_LASTALIGNCHUNK(o1, o0, 0x60, g2, g3, g4, g5) + MOVE_LASTALIGNCHUNK(o1, o0, 0x50, g2, g3, g4, g5) + MOVE_LASTALIGNCHUNK(o1, o0, 0x40, g2, g3, g4, g5) + MOVE_LASTALIGNCHUNK(o1, o0, 0x30, g2, g3, g4, g5) + MOVE_LASTALIGNCHUNK(o1, o0, 0x20, g2, g3, g4, g5) + MOVE_LASTALIGNCHUNK(o1, o0, 0x10, g2, g3, g4, g5) + MOVE_LASTALIGNCHUNK(o1, o0, 0x00, g2, g3, g4, g5) + +84: be 85f + andcc %g1, 4, %g0 + + ldd [%o1], %g2 + add %o0, 8, %o0 + std %g2, [%o0 - 0x08] + add %o1, 8, %o1 +85: be 1f + andcc %g1, 2, %g0 + + ld [%o1], %g2 + add %o1, 4, %o1 + st %g2, [%o0] + add %o0, 4, %o0 +1: be 1f + andcc %g1, 1, %g0 + + lduh [%o1], %g2 + add %o1, 2, %o1 + sth %g2, [%o0] + add %o0, 2, %o0 +1: be 1f + nop + + ldub [%o1], %g2 + stb %g2, [%o0] +1: retl + ld [%sp + 64], %o0 + +86: cmp %o2, 6 + bleu 88f + + cmp %o2, 256 + bcc 87f + + andcc %o0, 3, %g0 + be 61f + andcc %o0, 1, %g0 + be 60f + andcc %o0, 2, %g0 + + ldub [%o1], %g5 + add %o1, 1, %o1 + stb %g5, [%o0] + sub %o2, 1, %o2 + bne 61f + add %o0, 1, %o0 +60: ldub [%o1], %g3 + add %o1, 2, %o1 + stb %g3, [%o0] + sub %o2, 2, %o2 + ldub [%o1 - 1], %g3 + add %o0, 2, %o0 + stb %g3, [%o0 - 1] +61: and %o1, 3, %g2 + and %o2, 0xc, %g3 + and %o1, -4, %o1 + cmp %g3, 4 + sll %g2, 3, %g4 + mov 32, %g2 + be 4f + sub %g2, %g4, %g6 + + blu 3f + cmp %g3, 0x8 + + be 2f + srl %o2, 2, %g3 + + ld [%o1], %o3 + add %o0, -8, %o0 + ld [%o1 + 4], %o4 + b 8f + add %g3, 1, %g3 +2: ld [%o1], %o4 + add %o0, -12, %o0 + ld [%o1 + 4], %o5 + add %g3, 2, %g3 + b 9f + add %o1, -4, %o1 +3: ld [%o1], %g1 + add %o0, -4, %o0 + ld [%o1 + 4], %o3 + srl %o2, 2, %g3 + b 7f + add %o1, 4, %o1 +4: ld [%o1], %o5 + cmp %o2, 7 + ld [%o1 + 4], %g1 + srl %o2, 2, %g3 + bleu 10f + add %o1, 8, %o1 + + ld [%o1], %o3 + add %g3, -1, %g3 +5: sll %o5, %g4, %g2 + srl %g1, %g6, %g5 + or %g2, %g5, %g2 + st %g2, [%o0] +7: ld [%o1 + 4], %o4 + sll %g1, %g4, %g2 + srl %o3, %g6, %g5 + or %g2, %g5, %g2 + st %g2, [%o0 + 4] +8: ld [%o1 + 8], %o5 + sll %o3, %g4, %g2 + srl %o4, %g6, %g5 + or %g2, %g5, %g2 + st %g2, [%o0 + 8] +9: ld [%o1 + 12], %g1 + sll %o4, %g4, %g2 + srl %o5, %g6, %g5 + addcc %g3, -4, %g3 + or %g2, %g5, %g2 + add %o1, 16, %o1 + st %g2, [%o0 + 12] + add %o0, 16, %o0 + bne,a 5b + ld [%o1], %o3 +10: sll %o5, %g4, %g2 + srl %g1, %g6, %g5 + srl %g6, 3, %g3 + or %g2, %g5, %g2 + sub %o1, %g3, %o1 + andcc %o2, 2, %g0 + st %g2, [%o0] + be 1f + andcc %o2, 1, %g0 + + ldub [%o1], %g2 + add %o1, 2, %o1 + stb %g2, [%o0 + 4] + add %o0, 2, %o0 + ldub [%o1 - 1], %g2 + stb %g2, [%o0 + 3] +1: be 1f + nop + ldub [%o1], %g2 + stb %g2, [%o0 + 4] +1: retl + ld [%sp + 64], %o0 + +87: andcc %o1, 3, %g0 + be 3f + andcc %o1, 1, %g0 + + be 4f + andcc %o1, 2, %g0 + + ldub [%o1], %g2 + add %o1, 1, %o1 + stb %g2, [%o0] + sub %o2, 1, %o2 + bne 3f + add %o0, 1, %o0 +4: lduh [%o1], %g2 + add %o1, 2, %o1 + srl %g2, 8, %g3 + sub %o2, 2, %o2 + stb %g3, [%o0] + add %o0, 2, %o0 + stb %g2, [%o0 - 1] +3: andcc %o1, 4, %g0 + + bne 2f + cmp %o5, 1 + + ld [%o1], %o4 + srl %o4, 24, %g2 + stb %g2, [%o0] + srl %o4, 16, %g3 + stb %g3, [%o0 + 1] + srl %o4, 8, %g2 + stb %g2, [%o0 + 2] + sub %o2, 4, %o2 + stb %o4, [%o0 + 3] + add %o1, 4, %o1 + add %o0, 4, %o0 +2: be 33f + cmp %o5, 2 + be 32f + sub %o2, 4, %o2 +31: ld [%o1], %g2 + add %o1, 4, %o1 + srl %g2, 24, %g3 + and %o0, 7, %g5 + stb %g3, [%o0] + cmp %g5, 7 + sll %g2, 8, %g1 + add %o0, 4, %o0 + be 41f + and %o2, 0xffffffc0, %o3 + ld [%o0 - 7], %o4 +4: SMOVE_CHUNK(o1, o0, 0x00, g2, g3, g4, g5, o4, o5, g6, g1, 8, 24, -3) + SMOVE_CHUNK(o1, o0, 0x10, g2, g3, g4, g5, o4, o5, g6, g1, 8, 24, -3) + SMOVE_CHUNK(o1, o0, 0x20, g2, g3, g4, g5, o4, o5, g6, g1, 8, 24, -3) + SMOVE_CHUNK(o1, o0, 0x30, g2, g3, g4, g5, o4, o5, g6, g1, 8, 24, -3) + subcc %o3, 64, %o3 + add %o1, 64, %o1 + bne 4b + add %o0, 64, %o0 + + andcc %o2, 0x30, %o3 + be,a 1f + srl %g1, 16, %g2 +4: SMOVE_CHUNK(o1, o0, 0x00, g2, g3, g4, g5, o4, o5, g6, g1, 8, 24, -3) + subcc %o3, 16, %o3 + add %o1, 16, %o1 + bne 4b + add %o0, 16, %o0 + + srl %g1, 16, %g2 +1: st %o4, [%o0 - 7] + sth %g2, [%o0 - 3] + srl %g1, 8, %g4 + b 88f + stb %g4, [%o0 - 1] +32: ld [%o1], %g2 + add %o1, 4, %o1 + srl %g2, 16, %g3 + and %o0, 7, %g5 + sth %g3, [%o0] + cmp %g5, 6 + sll %g2, 16, %g1 + add %o0, 4, %o0 + be 42f + and %o2, 0xffffffc0, %o3 + ld [%o0 - 6], %o4 +4: SMOVE_CHUNK(o1, o0, 0x00, g2, g3, g4, g5, o4, o5, g6, g1, 16, 16, -2) + SMOVE_CHUNK(o1, o0, 0x10, g2, g3, g4, g5, o4, o5, g6, g1, 16, 16, -2) + SMOVE_CHUNK(o1, o0, 0x20, g2, g3, g4, g5, o4, o5, g6, g1, 16, 16, -2) + SMOVE_CHUNK(o1, o0, 0x30, g2, g3, g4, g5, o4, o5, g6, g1, 16, 16, -2) + subcc %o3, 64, %o3 + add %o1, 64, %o1 + bne 4b + add %o0, 64, %o0 + + andcc %o2, 0x30, %o3 + be,a 1f + srl %g1, 16, %g2 +4: SMOVE_CHUNK(o1, o0, 0x00, g2, g3, g4, g5, o4, o5, g6, g1, 16, 16, -2) + subcc %o3, 16, %o3 + add %o1, 16, %o1 + bne 4b + add %o0, 16, %o0 + + srl %g1, 16, %g2 +1: st %o4, [%o0 - 6] + b 88f + sth %g2, [%o0 - 2] +33: ld [%o1], %g2 + sub %o2, 4, %o2 + srl %g2, 24, %g3 + and %o0, 7, %g5 + stb %g3, [%o0] + cmp %g5, 5 + srl %g2, 8, %g4 + sll %g2, 24, %g1 + sth %g4, [%o0 + 1] + add %o1, 4, %o1 + be 43f + and %o2, 0xffffffc0, %o3 + + ld [%o0 - 1], %o4 + add %o0, 4, %o0 +4: SMOVE_CHUNK(o1, o0, 0x00, g2, g3, g4, g5, o4, o5, g6, g1, 24, 8, -1) + SMOVE_CHUNK(o1, o0, 0x10, g2, g3, g4, g5, o4, o5, g6, g1, 24, 8, -1) + SMOVE_CHUNK(o1, o0, 0x20, g2, g3, g4, g5, o4, o5, g6, g1, 24, 8, -1) + SMOVE_CHUNK(o1, o0, 0x30, g2, g3, g4, g5, o4, o5, g6, g1, 24, 8, -1) + subcc %o3, 64, %o3 + add %o1, 64, %o1 + bne 4b + add %o0, 64, %o0 + + andcc %o2, 0x30, %o3 + be,a 1f + srl %g1, 24, %g2 +4: SMOVE_CHUNK(o1, o0, 0x00, g2, g3, g4, g5, o4, o5, g6, g1, 24, 8, -1) + subcc %o3, 16, %o3 + add %o1, 16, %o1 + bne 4b + add %o0, 16, %o0 + + srl %g1, 24, %g2 +1: st %o4, [%o0 - 5] + b 88f + stb %g2, [%o0 - 1] +41: SMOVE_ALIGNCHUNK(o1, o0, 0x00, g2, g3, g4, g5, o4, o5, g6, g1, 8, 24, -3) + SMOVE_ALIGNCHUNK(o1, o0, 0x10, g2, g3, g4, g5, o4, o5, g6, g1, 8, 24, -3) + SMOVE_ALIGNCHUNK(o1, o0, 0x20, g2, g3, g4, g5, o4, o5, g6, g1, 8, 24, -3) + SMOVE_ALIGNCHUNK(o1, o0, 0x30, g2, g3, g4, g5, o4, o5, g6, g1, 8, 24, -3) + subcc %o3, 64, %o3 + add %o1, 64, %o1 + bne 41b + add %o0, 64, %o0 + + andcc %o2, 0x30, %o3 + be,a 1f + srl %g1, 16, %g2 +4: SMOVE_ALIGNCHUNK(o1, o0, 0x00, g2, g3, g4, g5, o4, o5, g6, g1, 8, 24, -3) + subcc %o3, 16, %o3 + add %o1, 16, %o1 + bne 4b + add %o0, 16, %o0 + + srl %g1, 16, %g2 +1: sth %g2, [%o0 - 3] + srl %g1, 8, %g4 + b 88f + stb %g4, [%o0 - 1] +43: SMOVE_ALIGNCHUNK(o1, o0, 0x00, g2, g3, g4, g5, o4, o5, g6, g1, 24, 8, 3) + SMOVE_ALIGNCHUNK(o1, o0, 0x10, g2, g3, g4, g5, o4, o5, g6, g1, 24, 8, 3) + SMOVE_ALIGNCHUNK(o1, o0, 0x20, g2, g3, g4, g5, o4, o5, g6, g1, 24, 8, 3) + SMOVE_ALIGNCHUNK(o1, o0, 0x30, g2, g3, g4, g5, o4, o5, g6, g1, 24, 8, 3) + subcc %o3, 64, %o3 + add %o1, 64, %o1 + bne 43b + add %o0, 64, %o0 + + andcc %o2, 0x30, %o3 + be,a 1f + srl %g1, 24, %g2 +4: SMOVE_ALIGNCHUNK(o1, o0, 0x00, g2, g3, g4, g5, o4, o5, g6, g1, 24, 8, 3) + subcc %o3, 16, %o3 + add %o1, 16, %o1 + bne 4b + add %o0, 16, %o0 + + srl %g1, 24, %g2 +1: stb %g2, [%o0 + 3] + b 88f + add %o0, 4, %o0 +42: SMOVE_ALIGNCHUNK(o1, o0, 0x00, g2, g3, g4, g5, o4, o5, g6, g1, 16, 16, -2) + SMOVE_ALIGNCHUNK(o1, o0, 0x10, g2, g3, g4, g5, o4, o5, g6, g1, 16, 16, -2) + SMOVE_ALIGNCHUNK(o1, o0, 0x20, g2, g3, g4, g5, o4, o5, g6, g1, 16, 16, -2) + SMOVE_ALIGNCHUNK(o1, o0, 0x30, g2, g3, g4, g5, o4, o5, g6, g1, 16, 16, -2) + subcc %o3, 64, %o3 + add %o1, 64, %o1 + bne 42b + add %o0, 64, %o0 + + andcc %o2, 0x30, %o3 + be,a 1f + srl %g1, 16, %g2 +4: SMOVE_ALIGNCHUNK(o1, o0, 0x00, g2, g3, g4, g5, o4, o5, g6, g1, 16, 16, -2) + subcc %o3, 16, %o3 + add %o1, 16, %o1 + bne 4b + add %o0, 16, %o0 + + srl %g1, 16, %g2 +1: sth %g2, [%o0 - 2] + + /* Fall through */ + +88: and %o2, 0xe, %o3 + mov %o7, %g2 + sll %o3, 3, %o4 + add %o0, %o3, %o0 +106: call 100f + add %o1, %o3, %o1 + mov %g2, %o7 + jmpl %o5 + (89f - 106b), %g0 + andcc %o2, 1, %g0 + + MOVE_SHORTCHUNK(o1, o0, 0x0c, g2, g3) + MOVE_SHORTCHUNK(o1, o0, 0x0a, g2, g3) + MOVE_SHORTCHUNK(o1, o0, 0x08, g2, g3) + MOVE_SHORTCHUNK(o1, o0, 0x06, g2, g3) + MOVE_SHORTCHUNK(o1, o0, 0x04, g2, g3) + MOVE_SHORTCHUNK(o1, o0, 0x02, g2, g3) + MOVE_SHORTCHUNK(o1, o0, 0x00, g2, g3) + +89: be 1f + nop + + ldub [%o1], %g2 + stb %g2, [%o0] +1: retl + ld [%sp + 64], %o0 + +90: bne 88b + andcc %o2, 8, %g0 + + be 1f + andcc %o2, 4, %g0 + + ld [%o1 + 0x00], %g2 + ld [%o1 + 0x04], %g3 + add %o1, 8, %o1 + st %g2, [%o0 + 0x00] + st %g3, [%o0 + 0x04] + add %o0, 8, %o0 +1: b 81b + mov %o2, %g1 + +100: retl + sub %o7, %o4, %o5 +110: retl + sub %o7, %g6, %o5 +END(memcpy) + +libc_hidden_builtin_def (memcpy) + +libc_hidden_def (__mempcpy) +weak_alias (__mempcpy, mempcpy) +libc_hidden_builtin_def (mempcpy) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/memset.S b/REORG.TODO/sysdeps/sparc/sparc32/memset.S new file mode 100644 index 0000000000..db44115047 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/memset.S @@ -0,0 +1,154 @@ +/* Set a block of memory to some byte value. + For SPARC v7. + Copyright (C) 1996-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@caip.rutgers.edu> and + Jakub Jelinek <jj@ultra.linux.cz>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* Store 64 bytes at (BASE + OFFSET) using value SOURCE. */ +#define ZERO_BIG_BLOCK(base, offset, source) \ + std source, [base + offset + 0x00]; \ + std source, [base + offset + 0x08]; \ + std source, [base + offset + 0x10]; \ + std source, [base + offset + 0x18]; \ + std source, [base + offset + 0x20]; \ + std source, [base + offset + 0x28]; \ + std source, [base + offset + 0x30]; \ + std source, [base + offset + 0x38]; + +#define ZERO_LAST_BLOCKS(base, offset, source) \ + std source, [base - offset - 0x38]; \ + std source, [base - offset - 0x30]; \ + std source, [base - offset - 0x28]; \ + std source, [base - offset - 0x20]; \ + std source, [base - offset - 0x18]; \ + std source, [base - offset - 0x10]; \ + std source, [base - offset - 0x08]; \ + std source, [base - offset - 0x00]; + + .text + .align 4 +ENTRY(__bzero) + b 1f + mov %g0, %g3 + +3: cmp %o2, 3 + be 2f + stb %g3, [%o0] + + cmp %o2, 2 + be 2f + stb %g3, [%o0 + 0x01] + + stb %g3, [%o0 + 0x02] +2: sub %o2, 4, %o2 + add %o1, %o2, %o1 + b 4f + sub %o0, %o2, %o0 +END(__bzero) + +ENTRY(memset) + and %o1, 0xff, %g3 + sll %g3, 8, %g2 + or %g3, %g2, %g3 + sll %g3, 16, %g2 + or %g3, %g2, %g3 + orcc %o2, %g0, %o1 +1: cmp %o1, 7 + bleu 7f + mov %o0, %g1 + + andcc %o0, 3, %o2 + bne 3b +4: andcc %o0, 4, %g0 + + be 2f + mov %g3, %g2 + + st %g3, [%o0] + sub %o1, 4, %o1 + add %o0, 4, %o0 +2: andcc %o1, 0xffffff80, %o3 + be 9f + andcc %o1, 0x78, %o2 +4: ZERO_BIG_BLOCK (%o0, 0x00, %g2) + subcc %o3, 128, %o3 + ZERO_BIG_BLOCK (%o0, 0x40, %g2) + bne 4b + add %o0, 128, %o0 + + orcc %o2, %g0, %g0 +9: be 6f + andcc %o1, 7, %o1 + + mov %o7, %g4 +101: call 100f + srl %o2, 1, %o3 + mov %g4, %o7 + jmpl %o4 + (20f + 64 - 101b), %g0 + add %o0, %o2, %o0 + +100: retl + sub %o7, %o3, %o4 + +20: ZERO_LAST_BLOCKS(%o0, 0x48, %g2) + ZERO_LAST_BLOCKS(%o0, 0x08, %g2) + +6: be 8f + andcc %o1, 4, %g0 + be 1f + andcc %o1, 2, %g0 + st %g3, [%o0] + add %o0, 4, %o0 +1: be 1f + andcc %o1, 1, %g0 + sth %g3, [%o0] + add %o0, 2, %o0 +1: bne,a 8f + stb %g3, [%o0] +8: retl + mov %g1, %o0 +7: orcc %o1, 0, %g0 + be 0f + subcc %o1, 1, %o1 + stb %g3, [%o0] + be 0f + subcc %o1, 1, %o1 + stb %g3, [%o0 + 1] + be 0f + subcc %o1, 1, %o1 + stb %g3, [%o0 + 2] + be 0f + subcc %o1, 1, %o1 + stb %g3, [%o0 + 3] + be 0f + subcc %o1, 1, %o1 + stb %g3, [%o0 + 4] + be 0f + subcc %o1, 1, %o1 + stb %g3, [%o0 + 5] + be 0f + subcc %o1, 1, %o1 + stb %g3, [%o0 + 6] +0: retl + nop +END(memset) +libc_hidden_builtin_def (memset) + +weak_alias (__bzero, bzero) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/mul_1.S b/REORG.TODO/sysdeps/sparc/sparc32/mul_1.S new file mode 100644 index 0000000000..8f7cd752a4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/mul_1.S @@ -0,0 +1,198 @@ +! SPARC __mpn_mul_1 -- Multiply a limb vector with a limb and store +! the result in a second limb vector. +! +! Copyright (C) 1992-2017 Free Software Foundation, Inc. +! +! This file is part of the GNU MP Library. +! +! The GNU MP Library is free software; you can redistribute it and/or modify +! it under the terms of the GNU Lesser General Public License as published by +! the Free Software Foundation; either version 2.1 of the License, or (at your +! option) any later version. +! +! The GNU MP Library is distributed in the hope that it will be useful, but +! WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +! or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +! License for more details. +! +! You should have received a copy of the GNU Lesser General Public License +! along with the GNU MP Library; see the file COPYING.LIB. If not, +! see <http://www.gnu.org/licenses/>. + + +! INPUT PARAMETERS +! RES_PTR o0 +! S1_PTR o1 +! SIZE o2 +! S2_LIMB o3 + +! ADD CODE FOR SMALL MULTIPLIERS! +!1: ld +! st +! +!2: ld ,a +! addxcc a,a,x +! st x, +! +!3_unrolled: +! ld ,a +! addxcc a,a,x1 ! 2a + cy +! addx %g0,%g0,x2 +! addcc a,x1,x ! 3a + c +! st x, +! +! ld ,a +! addxcc a,a,y1 +! addx %g0,%g0,y2 +! addcc a,y1,x +! st x, +! +!4_unrolled: +! ld ,a +! srl a,2,x1 ! 4a +! addxcc y2,x1,x +! sll a,30,x2 +! st x, +! +! ld ,a +! srl a,2,y1 +! addxcc x2,y1,y +! sll a,30,y2 +! st x, +! +!5_unrolled: +! ld ,a +! srl a,2,x1 ! 4a +! addxcc a,x1,x ! 5a + c +! sll a,30,x2 +! addx %g0,x2,x2 +! st x, +! +! ld ,a +! srl a,2,y1 +! addxcc a,y1,x +! sll a,30,y2 +! addx %g0,y2,y2 +! st x, +! +!8_unrolled: +! ld ,a +! srl a,3,x1 ! 8a +! addxcc y2,x1,x +! sll a,29,x2 +! st x, +! +! ld ,a +! srl a,3,y1 +! addxcc x2,y1,y +! sll a,29,y2 +! st x, + +#include <sysdep.h> + +ENTRY(__mpn_mul_1) + ! Make S1_PTR and RES_PTR point at the end of their blocks + ! and put (- 4 x SIZE) in index/loop counter. + sll %o2,2,%o2 + add %o0,%o2,%o4 ! RES_PTR in o4 since o0 is retval + add %o1,%o2,%o1 + sub %g0,%o2,%o2 + + cmp %o3,0xfff + bgu LOC(large) + nop + + ld [%o1+%o2],%o5 + mov 0,%o0 + b LOC(0) + add %o4,-4,%o4 +LOC(loop0): + st %g1,[%o4+%o2] +LOC(0): wr %g0,%o3,%y + sra %o5,31,%g2 + and %o3,%g2,%g2 + andcc %g1,0,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,0,%g1 + sra %g1,20,%g4 + sll %g1,12,%g1 + rd %y,%g3 + srl %g3,20,%g3 + or %g1,%g3,%g1 + + addcc %g1,%o0,%g1 + addx %g2,%g4,%o0 ! add sign-compensation and cy to hi limb + addcc %o2,4,%o2 ! loop counter + bne,a LOC(loop0) + ld [%o1+%o2],%o5 + + retl + st %g1,[%o4+%o2] + + +LOC(large): + ld [%o1+%o2],%o5 + mov 0,%o0 + sra %o3,31,%g4 ! g4 = mask of ones iff S2_LIMB < 0 + b LOC(1) + add %o4,-4,%o4 +LOC(loop): + st %g3,[%o4+%o2] +LOC(1): wr %g0,%o5,%y + and %o5,%g4,%g2 ! g2 = S1_LIMB iff S2_LIMB < 0, else 0 + andcc %g0,%g0,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%g0,%g1 + rd %y,%g3 + addcc %g3,%o0,%g3 + addx %g2,%g1,%o0 ! add sign-compensation and cy to hi limb + addcc %o2,4,%o2 ! loop counter + bne,a LOC(loop) + ld [%o1+%o2],%o5 + + retl + st %g3,[%o4+%o2] + +END(__mpn_mul_1) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/pthread_barrier_wait.c b/REORG.TODO/sysdeps/sparc/sparc32/pthread_barrier_wait.c new file mode 100644 index 0000000000..e5ef911f62 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/pthread_barrier_wait.c @@ -0,0 +1 @@ +#error No support for pthread barriers on pre-v9 sparc. diff --git a/REORG.TODO/sysdeps/sparc/sparc32/pthread_spin_lock.S b/REORG.TODO/sysdeps/sparc/sparc32/pthread_spin_lock.S new file mode 100644 index 0000000000..7d57c525b1 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/pthread_spin_lock.S @@ -0,0 +1,32 @@ +/* Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .text +ENTRY(pthread_spin_lock) +1: ldstub [%o0], %g1 + orcc %g1, 0x0, %g0 + bne,a 2f + ldub [%o0], %g1 + retl + mov 0, %o0 +2: orcc %g1, 0x0, %g0 + bne,a 2b + ldub [%o0], %g1 + ba,a 1b +END(pthread_spin_lock) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/pthread_spin_trylock.S b/REORG.TODO/sysdeps/sparc/sparc32/pthread_spin_trylock.S new file mode 100644 index 0000000000..061b37a834 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/pthread_spin_trylock.S @@ -0,0 +1,29 @@ +/* Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <pthread-errnos.h> + + .text +ENTRY(pthread_spin_trylock) + ldstub [%o0], %o0 + cmp %o0, 0 + bne,a 1f + mov EBUSY, %o0 +1: retl + nop +END(pthread_spin_trylock) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/pthreaddef.h b/REORG.TODO/sysdeps/sparc/sparc32/pthreaddef.h new file mode 100644 index 0000000000..720e183fde --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/pthreaddef.h @@ -0,0 +1,33 @@ +/* Copyright (C) 2003-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +/* Default stack size. */ +#define ARCH_STACK_DEFAULT_SIZE (2 * 1024 * 1024) + +/* Required stack pointer alignment at beginning. */ +#define STACK_ALIGN 16 + +/* Minimal stack size after allocating thread descriptor and guard size. */ +#define MINIMAL_REST_STACK 2048 + +/* Alignment requirement for TCB. */ +#define TCB_ALIGNMENT 16 + + +/* Location of current stack frame. */ +#define CURRENT_STACK_FRAME (stack_pointer + (2 * 64)) +register char *stack_pointer __asm__("%sp"); diff --git a/REORG.TODO/sysdeps/sparc/sparc32/rem.S b/REORG.TODO/sysdeps/sparc/sparc32/rem.S new file mode 100644 index 0000000000..349d7c0115 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/rem.S @@ -0,0 +1,363 @@ + /* This file is generated from divrem.m4; DO NOT EDIT! */ +/* + * Division and remainder, from Appendix E of the Sparc Version 8 + * Architecture Manual, with fixes from Gordon Irlam. + */ + +/* + * Input: dividend and divisor in %o0 and %o1 respectively. + * + * m4 parameters: + * .rem name of function to generate + * rem rem=div => %o0 / %o1; rem=rem => %o0 % %o1 + * true true=true => signed; true=false => unsigned + * + * Algorithm parameters: + * N how many bits per iteration we try to get (4) + * WORDSIZE total number of bits (32) + * + * Derived constants: + * TOPBITS number of bits in the top decade of a number + * + * Important variables: + * Q the partial quotient under development (initially 0) + * R the remainder so far, initially the dividend + * ITER number of main division loop iterations required; + * equal to ceil(log2(quotient) / N). Note that this + * is the log base (2^N) of the quotient. + * V the current comparand, initially divisor*2^(ITER*N-1) + * + * Cost: + * Current estimate for non-large dividend is + * ceil(log2(quotient) / N) * (10 + 7N/2) + C + * A large dividend is one greater than 2^(31-TOPBITS) and takes a + * different path, as the upper bits of the quotient must be developed + * one bit at a time. + */ + + + +#include <sysdep.h> +#include <sys/trap.h> + +ENTRY(.rem) + ! compute sign of result; if neither is negative, no problem + orcc %o1, %o0, %g0 ! either negative? + bge 2f ! no, go do the divide + mov %o0, %g3 ! sign of remainder matches %o0 + tst %o1 + bge 1f + tst %o0 + ! %o1 is definitely negative; %o0 might also be negative + bge 2f ! if %o0 not negative... + sub %g0, %o1, %o1 ! in any case, make %o1 nonneg +1: ! %o0 is negative, %o1 is nonnegative + sub %g0, %o0, %o0 ! make %o0 nonnegative +2: + + ! Ready to divide. Compute size of quotient; scale comparand. + orcc %o1, %g0, %o5 + bne 1f + mov %o0, %o3 + + ! Divide by zero trap. If it returns, return 0 (about as + ! wrong as possible, but that is what SunOS does...). + ta ST_DIV0 + retl + clr %o0 + +1: + cmp %o3, %o5 ! if %o1 exceeds %o0, done + blu LOC(got_result) ! (and algorithm fails otherwise) + clr %o2 + sethi %hi(1 << (32 - 4 - 1)), %g1 + cmp %o3, %g1 + blu LOC(not_really_big) + clr %o4 + + ! Here the dividend is >= 2**(31-N) or so. We must be careful here, + ! as our usual N-at-a-shot divide step will cause overflow and havoc. + ! The number of bits in the result here is N*ITER+SC, where SC <= N. + ! Compute ITER in an unorthodox manner: know we need to shift V into + ! the top decade: so do not even bother to compare to R. + 1: + cmp %o5, %g1 + bgeu 3f + mov 1, %g2 + sll %o5, 4, %o5 + b 1b + add %o4, 1, %o4 + + ! Now compute %g2. + 2: addcc %o5, %o5, %o5 + bcc LOC(not_too_big) + add %g2, 1, %g2 + + ! We get here if the %o1 overflowed while shifting. + ! This means that %o3 has the high-order bit set. + ! Restore %o5 and subtract from %o3. + sll %g1, 4, %g1 ! high order bit + srl %o5, 1, %o5 ! rest of %o5 + add %o5, %g1, %o5 + b LOC(do_single_div) + sub %g2, 1, %g2 + + LOC(not_too_big): + 3: cmp %o5, %o3 + blu 2b + nop + be LOC(do_single_div) + nop + /* NB: these are commented out in the V8-Sparc manual as well */ + /* (I do not understand this) */ + ! %o5 > %o3: went too far: back up 1 step + ! srl %o5, 1, %o5 + ! dec %g2 + ! do single-bit divide steps + ! + ! We have to be careful here. We know that %o3 >= %o5, so we can do the + ! first divide step without thinking. BUT, the others are conditional, + ! and are only done if %o3 >= 0. Because both %o3 and %o5 may have the high- + ! order bit set in the first step, just falling into the regular + ! division loop will mess up the first time around. + ! So we unroll slightly... + LOC(do_single_div): + subcc %g2, 1, %g2 + bl LOC(end_regular_divide) + nop + sub %o3, %o5, %o3 + mov 1, %o2 + b LOC(end_single_divloop) + nop + LOC(single_divloop): + sll %o2, 1, %o2 + bl 1f + srl %o5, 1, %o5 + ! %o3 >= 0 + sub %o3, %o5, %o3 + b 2f + add %o2, 1, %o2 + 1: ! %o3 < 0 + add %o3, %o5, %o3 + sub %o2, 1, %o2 + 2: + LOC(end_single_divloop): + subcc %g2, 1, %g2 + bge LOC(single_divloop) + tst %o3 + b,a LOC(end_regular_divide) + +LOC(not_really_big): +1: + sll %o5, 4, %o5 + cmp %o5, %o3 + bleu 1b + addcc %o4, 1, %o4 + be LOC(got_result) + sub %o4, 1, %o4 + + tst %o3 ! set up for initial iteration +LOC(divloop): + sll %o2, 4, %o2 + ! depth 1, accumulated bits 0 + bl LOC(1.16) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 2, accumulated bits 1 + bl LOC(2.17) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 3, accumulated bits 3 + bl LOC(3.19) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits 7 + bl LOC(4.23) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (7*2+1), %o2 + +LOC(4.23): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (7*2-1), %o2 + + +LOC(3.19): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits 5 + bl LOC(4.21) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (5*2+1), %o2 + +LOC(4.21): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (5*2-1), %o2 + + + +LOC(2.17): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 3, accumulated bits 1 + bl LOC(3.17) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits 3 + bl LOC(4.19) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (3*2+1), %o2 + +LOC(4.19): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (3*2-1), %o2 + + +LOC(3.17): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits 1 + bl LOC(4.17) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (1*2+1), %o2 + +LOC(4.17): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (1*2-1), %o2 + + + + +LOC(1.16): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 2, accumulated bits -1 + bl LOC(2.15) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 3, accumulated bits -1 + bl LOC(3.15) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits -1 + bl LOC(4.15) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-1*2+1), %o2 + +LOC(4.15): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-1*2-1), %o2 + + +LOC(3.15): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits -3 + bl LOC(4.13) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-3*2+1), %o2 + +LOC(4.13): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-3*2-1), %o2 + + + +LOC(2.15): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 3, accumulated bits -3 + bl LOC(3.13) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits -5 + bl LOC(4.11) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-5*2+1), %o2 + +LOC(4.11): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-5*2-1), %o2 + + +LOC(3.13): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits -7 + bl LOC(4.9) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-7*2+1), %o2 + +LOC(4.9): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-7*2-1), %o2 + + + + + 9: +LOC(end_regular_divide): + subcc %o4, 1, %o4 + bge LOC(divloop) + tst %o3 + bl,a LOC(got_result) + ! non-restoring fixup here (one instruction only!) + add %o3, %o1, %o3 + + +LOC(got_result): + ! check to see if answer should be < 0 + tst %g3 + bl,a 1f + sub %g0, %o3, %o3 +1: + retl + mov %o3, %o0 + +END(.rem) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/rshift.S b/REORG.TODO/sysdeps/sparc/sparc32/rshift.S new file mode 100644 index 0000000000..4185044168 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/rshift.S @@ -0,0 +1,93 @@ +! sparc __mpn_rshift -- +! +! Copyright (C) 1995-2017 Free Software Foundation, Inc. +! +! This file is part of the GNU MP Library. +! +! The GNU MP Library is free software; you can redistribute it and/or modify +! it under the terms of the GNU Lesser General Public License as published by +! the Free Software Foundation; either version 2.1 of the License, or (at your +! option) any later version. +! +! The GNU MP Library is distributed in the hope that it will be useful, but +! WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +! or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +! License for more details. +! +! You should have received a copy of the GNU Lesser General Public License +! along with the GNU MP Library; see the file COPYING.LIB. If not, +! see <http://www.gnu.org/licenses/>. + + +! INPUT PARAMETERS +! RES_PTR %o0 +! SRC_PTR %o1 +! SIZE %o2 +! CNT %o3 + +#include <sysdep.h> + +ENTRY(__mpn_rshift) + ld [%o1],%g2 ! load first limb + sub %g0,%o3,%o5 ! negate shift count + add %o2,-1,%o2 + andcc %o2,4-1,%g4 ! number of limbs in first loop + sll %g2,%o5,%g1 ! compute function result + be LOC(0) ! if multiple of 4 limbs, skip first loop + st %g1,[%sp+80] + + sub %o2,%g4,%o2 ! adjust count for main loop + +LOC(loop0): + ld [%o1+4],%g3 + add %o0,4,%o0 + add %o1,4,%o1 + addcc %g4,-1,%g4 + srl %g2,%o3,%o4 + sll %g3,%o5,%g1 + mov %g3,%g2 + or %o4,%g1,%o4 + bne LOC(loop0) + st %o4,[%o0-4] + +LOC(0): tst %o2 + be LOC(end) + nop + +LOC(loop): + ld [%o1+4],%g3 + add %o0,16,%o0 + addcc %o2,-4,%o2 + srl %g2,%o3,%o4 + sll %g3,%o5,%g1 + + ld [%o1+8],%g2 + srl %g3,%o3,%g4 + or %o4,%g1,%o4 + st %o4,[%o0-16] + sll %g2,%o5,%g1 + + ld [%o1+12],%g3 + srl %g2,%o3,%o4 + or %g4,%g1,%g4 + st %g4,[%o0-12] + sll %g3,%o5,%g1 + + ld [%o1+16],%g2 + srl %g3,%o3,%g4 + or %o4,%g1,%o4 + st %o4,[%o0-8] + sll %g2,%o5,%g1 + + add %o1,16,%o1 + or %g4,%g1,%g4 + bne LOC(loop) + st %g4,[%o0-4] + +LOC(end): + srl %g2,%o3,%g2 + st %g2,[%o0-0] + retl + ld [%sp+80],%o0 + +END(__mpn_rshift) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sdiv.S b/REORG.TODO/sysdeps/sparc/sparc32/sdiv.S new file mode 100644 index 0000000000..d1d4ee31f8 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sdiv.S @@ -0,0 +1,363 @@ + /* This file is generated from divrem.m4; DO NOT EDIT! */ +/* + * Division and remainder, from Appendix E of the Sparc Version 8 + * Architecture Manual, with fixes from Gordon Irlam. + */ + +/* + * Input: dividend and divisor in %o0 and %o1 respectively. + * + * m4 parameters: + * .div name of function to generate + * div div=div => %o0 / %o1; div=rem => %o0 % %o1 + * true true=true => signed; true=false => unsigned + * + * Algorithm parameters: + * N how many bits per iteration we try to get (4) + * WORDSIZE total number of bits (32) + * + * Derived constants: + * TOPBITS number of bits in the top decade of a number + * + * Important variables: + * Q the partial quotient under development (initially 0) + * R the remainder so far, initially the dividend + * ITER number of main division loop iterations required; + * equal to ceil(log2(quotient) / N). Note that this + * is the log base (2^N) of the quotient. + * V the current comparand, initially divisor*2^(ITER*N-1) + * + * Cost: + * Current estimate for non-large dividend is + * ceil(log2(quotient) / N) * (10 + 7N/2) + C + * A large dividend is one greater than 2^(31-TOPBITS) and takes a + * different path, as the upper bits of the quotient must be developed + * one bit at a time. + */ + + + +#include <sysdep.h> +#include <sys/trap.h> + +ENTRY(.div) + ! compute sign of result; if neither is negative, no problem + orcc %o1, %o0, %g0 ! either negative? + bge 2f ! no, go do the divide + xor %o1, %o0, %g3 ! compute sign in any case + tst %o1 + bge 1f + tst %o0 + ! %o1 is definitely negative; %o0 might also be negative + bge 2f ! if %o0 not negative... + sub %g0, %o1, %o1 ! in any case, make %o1 nonneg +1: ! %o0 is negative, %o1 is nonnegative + sub %g0, %o0, %o0 ! make %o0 nonnegative +2: + + ! Ready to divide. Compute size of quotient; scale comparand. + orcc %o1, %g0, %o5 + bne 1f + mov %o0, %o3 + + ! Divide by zero trap. If it returns, return 0 (about as + ! wrong as possible, but that is what SunOS does...). + ta ST_DIV0 + retl + clr %o0 + +1: + cmp %o3, %o5 ! if %o1 exceeds %o0, done + blu LOC(got_result) ! (and algorithm fails otherwise) + clr %o2 + sethi %hi(1 << (32 - 4 - 1)), %g1 + cmp %o3, %g1 + blu LOC(not_really_big) + clr %o4 + + ! Here the dividend is >= 2**(31-N) or so. We must be careful here, + ! as our usual N-at-a-shot divide step will cause overflow and havoc. + ! The number of bits in the result here is N*ITER+SC, where SC <= N. + ! Compute ITER in an unorthodox manner: know we need to shift V into + ! the top decade: so do not even bother to compare to R. + 1: + cmp %o5, %g1 + bgeu 3f + mov 1, %g2 + sll %o5, 4, %o5 + b 1b + add %o4, 1, %o4 + + ! Now compute %g2. + 2: addcc %o5, %o5, %o5 + bcc LOC(not_too_big) + add %g2, 1, %g2 + + ! We get here if the %o1 overflowed while shifting. + ! This means that %o3 has the high-order bit set. + ! Restore %o5 and subtract from %o3. + sll %g1, 4, %g1 ! high order bit + srl %o5, 1, %o5 ! rest of %o5 + add %o5, %g1, %o5 + b LOC(do_single_div) + sub %g2, 1, %g2 + + LOC(not_too_big): + 3: cmp %o5, %o3 + blu 2b + nop + be LOC(do_single_div) + nop + /* NB: these are commented out in the V8-Sparc manual as well */ + /* (I do not understand this) */ + ! %o5 > %o3: went too far: back up 1 step + ! srl %o5, 1, %o5 + ! dec %g2 + ! do single-bit divide steps + ! + ! We have to be careful here. We know that %o3 >= %o5, so we can do the + ! first divide step without thinking. BUT, the others are conditional, + ! and are only done if %o3 >= 0. Because both %o3 and %o5 may have the high- + ! order bit set in the first step, just falling into the regular + ! division loop will mess up the first time around. + ! So we unroll slightly... + LOC(do_single_div): + subcc %g2, 1, %g2 + bl LOC(end_regular_divide) + nop + sub %o3, %o5, %o3 + mov 1, %o2 + b LOC(end_single_divloop) + nop + LOC(single_divloop): + sll %o2, 1, %o2 + bl 1f + srl %o5, 1, %o5 + ! %o3 >= 0 + sub %o3, %o5, %o3 + b 2f + add %o2, 1, %o2 + 1: ! %o3 < 0 + add %o3, %o5, %o3 + sub %o2, 1, %o2 + 2: + LOC(end_single_divloop): + subcc %g2, 1, %g2 + bge LOC(single_divloop) + tst %o3 + b,a LOC(end_regular_divide) + +LOC(not_really_big): +1: + sll %o5, 4, %o5 + cmp %o5, %o3 + bleu 1b + addcc %o4, 1, %o4 + be LOC(got_result) + sub %o4, 1, %o4 + + tst %o3 ! set up for initial iteration +LOC(divloop): + sll %o2, 4, %o2 + ! depth 1, accumulated bits 0 + bl LOC(1.16) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 2, accumulated bits 1 + bl LOC(2.17) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 3, accumulated bits 3 + bl LOC(3.19) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits 7 + bl LOC(4.23) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (7*2+1), %o2 + +LOC(4.23): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (7*2-1), %o2 + + +LOC(3.19): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits 5 + bl LOC(4.21) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (5*2+1), %o2 + +LOC(4.21): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (5*2-1), %o2 + + + +LOC(2.17): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 3, accumulated bits 1 + bl LOC(3.17) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits 3 + bl LOC(4.19) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (3*2+1), %o2 + +LOC(4.19): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (3*2-1), %o2 + + +LOC(3.17): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits 1 + bl LOC(4.17) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (1*2+1), %o2 + +LOC(4.17): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (1*2-1), %o2 + + + + +LOC(1.16): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 2, accumulated bits -1 + bl LOC(2.15) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 3, accumulated bits -1 + bl LOC(3.15) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits -1 + bl LOC(4.15) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-1*2+1), %o2 + +LOC(4.15): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-1*2-1), %o2 + + +LOC(3.15): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits -3 + bl LOC(4.13) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-3*2+1), %o2 + +LOC(4.13): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-3*2-1), %o2 + + + +LOC(2.15): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 3, accumulated bits -3 + bl LOC(3.13) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits -5 + bl LOC(4.11) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-5*2+1), %o2 + +LOC(4.11): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-5*2-1), %o2 + + +LOC(3.13): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits -7 + bl LOC(4.9) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-7*2+1), %o2 + +LOC(4.9): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-7*2-1), %o2 + + + + + 9: +LOC(end_regular_divide): + subcc %o4, 1, %o4 + bge LOC(divloop) + tst %o3 + bl,a LOC(got_result) + ! non-restoring fixup here (one instruction only!) + sub %o2, 1, %o2 + + +LOC(got_result): + ! check to see if answer should be < 0 + tst %g3 + bl,a 1f + sub %g0, %o2, %o2 +1: + retl + mov %o2, %o0 + +END(.div) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sem_post.c b/REORG.TODO/sysdeps/sparc/sparc32/sem_post.c new file mode 100644 index 0000000000..ae8358dc11 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sem_post.c @@ -0,0 +1,82 @@ +/* sem_post -- post to a POSIX semaphore. Generic futex-using version. + Copyright (C) 2003-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jakub@redhat.com>, 2003. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <atomic.h> +#include <errno.h> +#include <sysdep.h> +#include <lowlevellock.h> +#include <internaltypes.h> +#include <semaphore.h> +#include <futex-internal.h> + +#include <shlib-compat.h> + + +/* See sem_wait for an explanation of the algorithm. */ +int +__new_sem_post (sem_t *sem) +{ + struct new_sem *isem = (struct new_sem *) sem; + int private = isem->private; + unsigned int v; + + __sparc32_atomic_do_lock24 (&isem->pad); + + v = isem->value; + if ((v >> SEM_VALUE_SHIFT) == SEM_VALUE_MAX) + { + __sparc32_atomic_do_unlock24 (&isem->pad); + + __set_errno (EOVERFLOW); + return -1; + } + isem->value = v + (1 << SEM_VALUE_SHIFT); + + __sparc32_atomic_do_unlock24 (&isem->pad); + + if ((v & SEM_NWAITERS_MASK) != 0) + futex_wake (&isem->value, 1, private); + + return 0; +} +versioned_symbol (libpthread, __new_sem_post, sem_post, GLIBC_2_1); + + +#if SHLIB_COMPAT (libpthread, GLIBC_2_0, GLIBC_2_1) +int +attribute_compat_text_section +__old_sem_post (sem_t *sem) +{ + int *futex = (int *) sem; + + /* We must need to synchronize with consumers of this token, so the atomic + increment must have release MO semantics. */ + atomic_write_barrier (); + (void) atomic_increment_val (futex); + /* We always have to assume it is a shared semaphore. */ + int err = lll_futex_wake (futex, 1, LLL_SHARED); + if (__builtin_expect (err, 0) < 0) + { + __set_errno (-err); + return -1; + } + return 0; +} +compat_symbol (libpthread, __old_sem_post, sem_post, GLIBC_2_0); +#endif diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sem_waitcommon.c b/REORG.TODO/sysdeps/sparc/sparc32/sem_waitcommon.c new file mode 100644 index 0000000000..08fd12ce50 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sem_waitcommon.c @@ -0,0 +1,146 @@ +/* sem_waitcommon -- wait on a semaphore, shared code. + Copyright (C) 2003-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <errno.h> +#include <sysdep.h> +#include <futex-internal.h> +#include <internaltypes.h> +#include <semaphore.h> +#include <sys/time.h> + +#include <pthreadP.h> +#include <shlib-compat.h> +#include <atomic.h> + + +static void +__sem_wait_32_finish (struct new_sem *sem); + +static void +__sem_wait_cleanup (void *arg) +{ + struct new_sem *sem = (struct new_sem *) arg; + + __sem_wait_32_finish (sem); +} + +/* Wait until at least one token is available, possibly with a timeout. + This is in a separate function in order to make sure gcc + puts the call site into an exception region, and thus the + cleanups get properly run. TODO still necessary? Other futex_wait + users don't seem to need it. */ +static int +__attribute__ ((noinline)) +do_futex_wait (struct new_sem *sem, const struct timespec *abstime) +{ + int err; + + err = futex_abstimed_wait_cancelable (&sem->value, SEM_NWAITERS_MASK, + abstime, sem->private); + + return err; +} + +/* Fast path: Try to grab a token without blocking. */ +static int +__new_sem_wait_fast (struct new_sem *sem, int definitive_result) +{ + unsigned int v; + int ret = 0; + + __sparc32_atomic_do_lock24(&sem->pad); + + v = sem->value; + if ((v >> SEM_VALUE_SHIFT) == 0) + ret = -1; + else + sem->value = v - (1 << SEM_VALUE_SHIFT); + + __sparc32_atomic_do_unlock24(&sem->pad); + + return ret; +} + +/* Slow path that blocks. */ +static int +__attribute__ ((noinline)) +__new_sem_wait_slow (struct new_sem *sem, const struct timespec *abstime) +{ + unsigned int v; + int err = 0; + + __sparc32_atomic_do_lock24(&sem->pad); + + sem->nwaiters++; + + pthread_cleanup_push (__sem_wait_cleanup, sem); + + /* Wait for a token to be available. Retry until we can grab one. */ + v = sem->value; + do + { + if (!(v & SEM_NWAITERS_MASK)) + sem->value = v | SEM_NWAITERS_MASK; + + /* If there is no token, wait. */ + if ((v >> SEM_VALUE_SHIFT) == 0) + { + __sparc32_atomic_do_unlock24(&sem->pad); + + err = do_futex_wait(sem, abstime); + if (err == ETIMEDOUT || err == EINTR) + { + __set_errno (err); + err = -1; + goto error; + } + err = 0; + + __sparc32_atomic_do_lock24(&sem->pad); + + /* We blocked, so there might be a token now. */ + v = sem->value; + } + } + /* If there is no token, we must not try to grab one. */ + while ((v >> SEM_VALUE_SHIFT) == 0); + + sem->value = v - (1 << SEM_VALUE_SHIFT); + + __sparc32_atomic_do_unlock24(&sem->pad); + +error: + pthread_cleanup_pop (0); + + __sem_wait_32_finish (sem); + + return err; +} + +/* Stop being a registered waiter (non-64b-atomics code only). */ +static void +__sem_wait_32_finish (struct new_sem *sem) +{ + __sparc32_atomic_do_lock24(&sem->pad); + + if (--sem->nwaiters == 0) + sem->value &= ~SEM_NWAITERS_MASK; + + __sparc32_atomic_do_unlock24(&sem->pad); +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/setjmp.S b/REORG.TODO/sysdeps/sparc/sparc32/setjmp.S new file mode 100644 index 0000000000..02cf17343b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/setjmp.S @@ -0,0 +1,59 @@ +/* Copyright (C) 1991-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <sys/trap.h> + +#include <jmpbuf-offsets.h> + +ENTRY(_setjmp) + b 1f + set 0, %o1 +END(_setjmp) +libc_hidden_def (_setjmp) + +ENTRY(setjmp) + set 1, %o1 +END(setjmp) + +ENTRY (__sigsetjmp) +1: + /* Save our PC, SP and FP. Save the signal mask if requested with + a tail-call for simplicity; it always returns zero. */ + ta ST_FLUSH_WINDOWS + +#ifdef PTR_MANGLE + PTR_MANGLE (%g1, %o7, %g4) + PTR_MANGLE2 (%g2, %sp, %g4) + PTR_MANGLE2 (%g3, %fp, %g4) + st %g1, [%o0 + (JB_PC * 4)] + st %g2, [%o0 + (JB_SP * 4)] + st %g3, [%o0 + (JB_FP * 4)] +#else + st %o7, [%o0 + (JB_PC * 4)] + st %sp, [%o0 + (JB_SP * 4)] + st %fp, [%o0 + (JB_FP * 4)] +#endif + + mov %o7, %g1 + call __sigjmp_save + mov %g1, %o7 +END(__sigsetjmp) +hidden_def (__sigsetjmp) + +weak_extern(_setjmp) +weak_extern(setjmp) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/Makefile b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/Makefile new file mode 100644 index 0000000000..137e26bee9 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/Makefile @@ -0,0 +1,29 @@ +# Software floating-point emulation. +# Makefile for SPARC v8 long double utility functions (_Q_*). +# Copyright (C) 1999-2017 Free Software Foundation, Inc. +# This file is part of the GNU C Library. +# Contributed by Jakub Jelinek (jj@ultra.linux.cz). +# + +# The GNU C Library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. + +# The GNU C Library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. + +# You should have received a copy of the GNU Lesser General Public +# License along with the GNU C Library; if not, see +# <http://www.gnu.org/licenses/>. + +ifeq ($(subdir),soft-fp) +sparc32-quad-routines := q_add q_cmp q_cmpe q_div q_dtoq q_feq q_fge \ + q_fgt q_fle q_flt q_fne q_itoq q_mul q_neg q_qtod q_qtoi \ + q_qtos q_qtou q_qtoull q_qtoll q_sqrt q_stoq q_sub q_utoq \ + q_ulltoq q_lltoq q_util +sysdep_routines += $(sparc32-quad-routines) + +endif diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/Versions b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/Versions new file mode 100644 index 0000000000..6a09249c46 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/Versions @@ -0,0 +1,8 @@ +libc { + GLIBC_2.4 { + _Q_add; _Q_cmp; _Q_cmpe; _Q_div; _Q_dtoq; _Q_feq; _Q_fge; _Q_fgt; + _Q_fle; _Q_flt; _Q_fne; _Q_itoq; _Q_mul; _Q_neg; _Q_qtod; _Q_qtoi; + _Q_qtos; _Q_qtou; _Q_qtoull; _Q_qtoll; _Q_sqrt; _Q_stoq; _Q_sub; + _Q_utoq; _Q_ulltoq; _Q_lltoq; + } +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_add.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_add.c new file mode 100644 index 0000000000..2a250dee37 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_add.c @@ -0,0 +1,38 @@ +/* Software floating-point emulation. + Return a + b + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +long double _Q_add(const long double a, const long double b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); FP_DECL_Q(C); + long double c; + + FP_INIT_ROUNDMODE; + FP_UNPACK_SEMIRAW_Q(A, a); + FP_UNPACK_SEMIRAW_Q(B, b); + FP_ADD_Q(C, A, B); + FP_PACK_SEMIRAW_Q(c, C); + FP_HANDLE_EXCEPTIONS; + return c; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_cmp.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_cmp.c new file mode 100644 index 0000000000..9269cf72ae --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_cmp.c @@ -0,0 +1,38 @@ +/* Software floating-point emulation. + Compare a and b, return float condition code. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +int _Q_cmp(const long double a, const long double b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); + int r; + + FP_UNPACK_RAW_Q(A, a); + FP_UNPACK_RAW_Q(B, b); + FP_CMP_Q(r, B, A, 3, 1); + if (r == -1) r = 2; + FP_HANDLE_EXCEPTIONS; + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_cmpe.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_cmpe.c new file mode 100644 index 0000000000..6a46441e8f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_cmpe.c @@ -0,0 +1,39 @@ +/* Software floating-point emulation. + Compare a and b, return float condition code. + Signal exception (unless masked) if unordered. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +int _Q_cmpe(const long double a, const long double b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); + int r; + + FP_UNPACK_RAW_Q(A, a); + FP_UNPACK_RAW_Q(B, b); + FP_CMP_Q(r, B, A, 3, 2); + if (r == -1) r = 2; + FP_HANDLE_EXCEPTIONS; + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_div.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_div.c new file mode 100644 index 0000000000..4920219a4d --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_div.c @@ -0,0 +1,38 @@ +/* Software floating-point emulation. + Return a / b + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +long double _Q_div(const long double a, const long double b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); FP_DECL_Q(C); + long double c; + + FP_INIT_ROUNDMODE; + FP_UNPACK_Q(A, a); + FP_UNPACK_Q(B, b); + FP_DIV_Q(C, A, B); + FP_PACK_Q(c, C); + FP_HANDLE_EXCEPTIONS; + return c; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_dtoq.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_dtoq.c new file mode 100644 index 0000000000..1d5426dfe9 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_dtoq.c @@ -0,0 +1,43 @@ +/* Software floating-point emulation. + Return (long double)(a) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "double.h" +#include "quad.h" + +long double _Q_dtoq(const double a) +{ + FP_DECL_EX; + FP_DECL_D(A); + FP_DECL_Q(C); + long double c; + + FP_INIT_ROUNDMODE; + FP_UNPACK_RAW_D(A, a); +#if (2 * _FP_W_TYPE_SIZE) < _FP_FRACBITS_Q + FP_EXTEND(Q,D,4,2,C,A); +#else + FP_EXTEND(Q,D,2,1,C,A); +#endif + FP_PACK_RAW_Q(c, C); + FP_HANDLE_EXCEPTIONS; + return c; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_feq.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_feq.c new file mode 100644 index 0000000000..94ba005e61 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_feq.c @@ -0,0 +1,37 @@ +/* Software floating-point emulation. + Return 1 if a == b + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +int _Q_feq(const long double a, const long double b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); + int r; + + FP_UNPACK_RAW_Q(A, a); + FP_UNPACK_RAW_Q(B, b); + FP_CMP_EQ_Q(r, A, B, 1); + FP_HANDLE_EXCEPTIONS; + + return !r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_fge.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_fge.c new file mode 100644 index 0000000000..09c45d7ef9 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_fge.c @@ -0,0 +1,37 @@ +/* Software floating-point emulation. + Return 1 if a >= b + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +int _Q_fge(const long double a, const long double b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); + int r; + + FP_UNPACK_RAW_Q(A, a); + FP_UNPACK_RAW_Q(B, b); + FP_CMP_Q(r, B, A, 3, 2); + FP_HANDLE_EXCEPTIONS; + + return (r <= 0); +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_fgt.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_fgt.c new file mode 100644 index 0000000000..1386b14434 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_fgt.c @@ -0,0 +1,37 @@ +/* Software floating-point emulation. + Return 1 if a > b + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +int _Q_fgt(const long double a, const long double b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); + int r; + + FP_UNPACK_RAW_Q(A, a); + FP_UNPACK_RAW_Q(B, b); + FP_CMP_Q(r, B, A, 3, 2); + FP_HANDLE_EXCEPTIONS; + + return (r == -1); +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_fle.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_fle.c new file mode 100644 index 0000000000..83b676ee44 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_fle.c @@ -0,0 +1,37 @@ +/* Software floating-point emulation. + Return 1 if a <= b + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +int _Q_fle(const long double a, const long double b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); + int r; + + FP_UNPACK_RAW_Q(A, a); + FP_UNPACK_RAW_Q(B, b); + FP_CMP_Q(r, B, A, -2, 2); + FP_HANDLE_EXCEPTIONS; + + return (r >= 0); +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_flt.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_flt.c new file mode 100644 index 0000000000..f196393b44 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_flt.c @@ -0,0 +1,37 @@ +/* Software floating-point emulation. + Return 1 if a < b + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +int _Q_flt(const long double a, const long double b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); + int r; + + FP_UNPACK_RAW_Q(A, a); + FP_UNPACK_RAW_Q(B, b); + FP_CMP_Q(r, B, A, 3, 2); + FP_HANDLE_EXCEPTIONS; + + return (r == 1); +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_fne.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_fne.c new file mode 100644 index 0000000000..b017d892c9 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_fne.c @@ -0,0 +1,37 @@ +/* Software floating-point emulation. + Return 1 if a != b + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +int _Q_fne(const long double a, const long double b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); + int r; + + FP_UNPACK_RAW_Q(A, a); + FP_UNPACK_RAW_Q(B, b); + FP_CMP_EQ_Q(r, A, B, 1); + FP_HANDLE_EXCEPTIONS; + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_itoq.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_itoq.c new file mode 100644 index 0000000000..e11938cc43 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_itoq.c @@ -0,0 +1,35 @@ +/* Software floating-point emulation. + Return (long double)(a) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#define FP_NO_EXCEPTIONS +#include "soft-fp.h" +#include "quad.h" + +long double _Q_itoq(const int a) +{ + FP_DECL_Q(C); + int b = a; + long double c; + + FP_FROM_INT_Q(C, b, 32, unsigned int); + FP_PACK_RAW_Q(c, C); + return c; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_lltoq.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_lltoq.c new file mode 100644 index 0000000000..b94443dd65 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_lltoq.c @@ -0,0 +1,35 @@ +/* Software floating-point emulation. + Return (long double)a + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#define FP_NO_EXCEPTIONS +#include "soft-fp.h" +#include "quad.h" + +long double _Q_lltoq(const long long a) +{ + FP_DECL_Q(C); + long double c; + long long b = a; + + FP_FROM_INT_Q(C, b, 64, unsigned long long); + FP_PACK_RAW_Q(c, C); + return c; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_mul.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_mul.c new file mode 100644 index 0000000000..8892f0ef93 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_mul.c @@ -0,0 +1,38 @@ +/* Software floating-point emulation. + Return a * b + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +long double _Q_mul(const long double a, const long double b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); FP_DECL_Q(C); + long double c; + + FP_INIT_ROUNDMODE; + FP_UNPACK_Q(A, a); + FP_UNPACK_Q(B, b); + FP_MUL_Q(C, A, B); + FP_PACK_Q(c, C); + FP_HANDLE_EXCEPTIONS; + return c; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_neg.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_neg.c new file mode 100644 index 0000000000..9660d17eac --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_neg.c @@ -0,0 +1,48 @@ +/* Software floating-point emulation. + Return !a + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +long double _Q_neg(const long double a) +{ + union { + long double ldbl; + UWtype words[4]; + } c; + + c.ldbl = a; + +#if (__BYTE_ORDER == __BIG_ENDIAN) + c.words[0] ^= (((UWtype)1) << (W_TYPE_SIZE - 1)); +#elif (__BYTE_ORDER == __LITTLE_ENDIAN) && (W_TYPE_SIZE == 64) + c.words[1] ^= (((UWtype)1) << (W_TYPE_SIZE - 1)); +#elif (__BYTE_ORDER == __LITTLE_ENDIAN) && (W_TYPE_SIZE == 32) + c.words[3] ^= (((UWtype)1) << (W_TYPE_SIZE - 1)); +#else + FP_DECL_Q(A); FP_DECL_Q(C); + + FP_UNPACK_RAW_Q(A, a); + FP_NEG_Q(C, A); + FP_PACK_RAW_Q(c.ldbl, C); +#endif + return c.ldbl; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_qtod.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_qtod.c new file mode 100644 index 0000000000..9d7b80ef3e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_qtod.c @@ -0,0 +1,44 @@ +/* Software floating-point emulation. + Return (double)a + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "double.h" +#include "quad.h" + +double _Q_qtod(const long double a) +{ + FP_DECL_EX; + FP_DECL_Q(A); + FP_DECL_D(R); + double r; + + FP_INIT_ROUNDMODE; + FP_UNPACK_SEMIRAW_Q(A, a); +#if (2 * _FP_W_TYPE_SIZE) < _FP_FRACBITS_Q + FP_TRUNC(D,Q,2,4,R,A); +#else + FP_TRUNC(D,Q,1,2,R,A); +#endif + FP_PACK_SEMIRAW_D(r, R); + FP_HANDLE_EXCEPTIONS; + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_qtoi.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_qtoi.c new file mode 100644 index 0000000000..5d362b70e4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_qtoi.c @@ -0,0 +1,37 @@ +/* Software floating-point emulation. + Return (int)a + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#define FP_ROUNDMODE FP_RND_ZERO +#include "soft-fp.h" +#include "quad.h" + +int _Q_qtoi(const long double a) +{ + FP_DECL_EX; + FP_DECL_Q(A); + unsigned int r; + + FP_UNPACK_RAW_Q(A, a); + FP_TO_INT_Q(r, A, 32, 1); + FP_HANDLE_EXCEPTIONS; + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_qtoll.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_qtoll.c new file mode 100644 index 0000000000..bfaa64ac11 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_qtoll.c @@ -0,0 +1,37 @@ +/* Software floating-point emulation. + Return (long long)a + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#define FP_ROUNDMODE FP_RND_ZERO +#include "soft-fp.h" +#include "quad.h" + +long long _Q_qtoll(const long double a) +{ + FP_DECL_EX; + FP_DECL_Q(A); + unsigned long long r; + + FP_UNPACK_RAW_Q(A, a); + FP_TO_INT_Q(r, A, 64, 1); + FP_HANDLE_EXCEPTIONS; + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_qtos.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_qtos.c new file mode 100644 index 0000000000..b2642def3b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_qtos.c @@ -0,0 +1,44 @@ +/* Software floating-point emulation. + Return (float)a + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "single.h" +#include "quad.h" + +float _Q_qtos(const long double a) +{ + FP_DECL_EX; + FP_DECL_Q(A); + FP_DECL_S(R); + float r; + + FP_INIT_ROUNDMODE; + FP_UNPACK_SEMIRAW_Q(A, a); +#if (2 * _FP_W_TYPE_SIZE) < _FP_FRACBITS_Q + FP_TRUNC(S,Q,1,4,R,A); +#else + FP_TRUNC(S,Q,1,2,R,A); +#endif + FP_PACK_SEMIRAW_S(r, R); + FP_HANDLE_EXCEPTIONS; + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_qtou.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_qtou.c new file mode 100644 index 0000000000..3940a2f5b6 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_qtou.c @@ -0,0 +1,37 @@ +/* Software floating-point emulation. + Return (unsigned int)a + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#define FP_ROUNDMODE FP_RND_ZERO +#include "soft-fp.h" +#include "quad.h" + +unsigned int _Q_qtou(const long double a) +{ + FP_DECL_EX; + FP_DECL_Q(A); + unsigned int r; + + FP_UNPACK_RAW_Q(A, a); + FP_TO_INT_Q(r, A, 32, -1); + FP_HANDLE_EXCEPTIONS; + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_qtoull.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_qtoull.c new file mode 100644 index 0000000000..83fabef05c --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_qtoull.c @@ -0,0 +1,37 @@ +/* Software floating-point emulation. + Return (unsigned long long)a + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#define FP_ROUNDMODE FP_RND_ZERO +#include "soft-fp.h" +#include "quad.h" + +unsigned long long _Q_qtoull(const long double a) +{ + FP_DECL_EX; + FP_DECL_Q(A); + unsigned long long r; + + FP_UNPACK_RAW_Q(A, a); + FP_TO_INT_Q(r, A, 64, -1); + FP_HANDLE_EXCEPTIONS; + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_sqrt.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_sqrt.c new file mode 100644 index 0000000000..c3939446fe --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_sqrt.c @@ -0,0 +1,37 @@ +/* Software floating-point emulation. + Return sqrtl(a) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +long double _Q_sqrt(const long double a) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(C); + long double c; + + FP_INIT_ROUNDMODE; + FP_UNPACK_Q(A, a); + FP_SQRT_Q(C, A); + FP_PACK_Q(c, C); + FP_HANDLE_EXCEPTIONS; + return c; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_stoq.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_stoq.c new file mode 100644 index 0000000000..b011d801b4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_stoq.c @@ -0,0 +1,42 @@ +/* Software floating-point emulation. + c = (long double)(a) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "single.h" +#include "quad.h" + +long double _Q_stoq(const float a) +{ + FP_DECL_EX; + FP_DECL_S(A); + FP_DECL_Q(C); + long double c; + + FP_UNPACK_RAW_S(A, a); +#if (2 * _FP_W_TYPE_SIZE) < _FP_FRACBITS_Q + FP_EXTEND(Q,S,4,1,C,A); +#else + FP_EXTEND(Q,S,2,1,C,A); +#endif + FP_PACK_RAW_Q(c, C); + FP_HANDLE_EXCEPTIONS; + return c; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_sub.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_sub.c new file mode 100644 index 0000000000..69d78cd85a --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_sub.c @@ -0,0 +1,38 @@ +/* Software floating-point emulation. + c = a - b + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +long double _Q_sub(const long double a, const long double b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); FP_DECL_Q(C); + long double c; + + FP_INIT_ROUNDMODE; + FP_UNPACK_SEMIRAW_Q(A, a); + FP_UNPACK_SEMIRAW_Q(B, b); + FP_SUB_Q(C, A, B); + FP_PACK_SEMIRAW_Q(c, C); + FP_HANDLE_EXCEPTIONS; + return c; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_ulltoq.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_ulltoq.c new file mode 100644 index 0000000000..97586cb588 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_ulltoq.c @@ -0,0 +1,35 @@ +/* Software floating-point emulation. + Return (long double)(a) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#define FP_NO_EXCEPTIONS +#include "soft-fp.h" +#include "quad.h" + +long double _Q_ulltoq(const unsigned long long a) +{ + FP_DECL_Q(C); + long double c; + unsigned long long b = a; + + FP_FROM_INT_Q(C, b, 64, unsigned long long); + FP_PACK_RAW_Q(c, C); + return c; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_util.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_util.c new file mode 100644 index 0000000000..35de7ee791 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_util.c @@ -0,0 +1,62 @@ +/* Software floating-point emulation. + Helper routine for _Q_* routines. + Simulate exceptions using double arithmetics. + Copyright (C) 1999-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <float.h> +#include <math.h> +#include <assert.h> +#include "soft-fp.h" + +unsigned long long ___Q_zero = 0x0000000000000000ULL; + +void ___Q_simulate_exceptions(int exceptions) +{ + if (exceptions & FP_EX_INVALID) + { + float f = 0.0; + __asm__ __volatile__ ("fdivs %0, %0, %0" : "+f" (f)); + } + if (exceptions & FP_EX_DIVZERO) + { + float f = 1.0, g = 0.0; + __asm__ __volatile__ ("fdivs %0, %1, %0" + : "+f" (f) + : "f" (g)); + } + if (exceptions & FP_EX_OVERFLOW) + { + float f = FLT_MAX; + __asm__ __volatile__("fmuls %0, %0, %0" : "+f" (f)); + exceptions &= ~FP_EX_INEXACT; + } + if (exceptions & FP_EX_UNDERFLOW) + { + float f = FLT_MIN; + __asm__ __volatile__("fmuls %0, %0, %0" : "+f" (f)); + exceptions &= ~FP_EX_INEXACT; + } + if (exceptions & FP_EX_INEXACT) + { + double d = 1.0, e = M_PI; + __asm__ __volatile__ ("fdivd %0, %1, %0" + : "+f" (d) + : "f" (e)); + } +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_utoq.c b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_utoq.c new file mode 100644 index 0000000000..48337ccb0e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/q_utoq.c @@ -0,0 +1,35 @@ +/* Software floating-point emulation. + c = (long double)(a) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#define FP_NO_EXCEPTIONS +#include "soft-fp.h" +#include "quad.h" + +long double _Q_utoq(const unsigned int a) +{ + FP_DECL_Q(C); + long double c; + unsigned int b = a; + + FP_FROM_INT_Q(C, b, 32, unsigned int); + FP_PACK_RAW_Q(c, C); + return c; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/sfp-machine.h b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/sfp-machine.h new file mode 100644 index 0000000000..de9d56ec46 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/soft-fp/sfp-machine.h @@ -0,0 +1,218 @@ +/* Machine-dependent software floating-point definitions. + Sparc userland (_Q_*) version. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com), + Jakub Jelinek (jj@ultra.linux.cz) and + David S. Miller (davem@redhat.com). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fpu_control.h> +#include <stdlib.h> + +#define _FP_W_TYPE_SIZE 32 +#define _FP_W_TYPE unsigned long +#define _FP_WS_TYPE signed long +#define _FP_I_TYPE long + +#define _FP_MUL_MEAT_S(R,X,Y) \ + _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm) +#define _FP_MUL_MEAT_D(R,X,Y) \ + _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm) +#define _FP_MUL_MEAT_Q(R,X,Y) \ + _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm) + +#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv(S,R,X,Y) +#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y) +#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y) + +#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) +#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1 +#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1 +#define _FP_NANSIGN_S 0 +#define _FP_NANSIGN_D 0 +#define _FP_NANSIGN_Q 0 + +#define _FP_KEEPNANFRACP 1 +#define _FP_QNANNEGATEDP 0 + +/* If one NaN is signaling and the other is not, + * we choose that one, otherwise we choose X. + */ +/* For _Qp_* and _Q_*, this should prefer X, for + * CPU instruction emulation this should prefer Y. + * (see SPAMv9 B.2.2 section). + */ +#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \ + do { \ + if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \ + && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) \ + { \ + R##_s = Y##_s; \ + _FP_FRAC_COPY_##wc(R,Y); \ + } \ + else \ + { \ + R##_s = X##_s; \ + _FP_FRAC_COPY_##wc(R,X); \ + } \ + R##_c = FP_CLS_NAN; \ + } while (0) + +/* Some assembly to speed things up. */ +#define __FP_FRAC_ADD_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \ + __asm__ ("addcc %r7,%8,%2\n\ + addxcc %r5,%6,%1\n\ + addx %r3,%4,%0" \ + : "=r" ((USItype)(r2)), \ + "=&r" ((USItype)(r1)), \ + "=&r" ((USItype)(r0)) \ + : "%rJ" ((USItype)(x2)), \ + "rI" ((USItype)(y2)), \ + "%rJ" ((USItype)(x1)), \ + "rI" ((USItype)(y1)), \ + "%rJ" ((USItype)(x0)), \ + "rI" ((USItype)(y0)) \ + : "cc") + +#define __FP_FRAC_SUB_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \ + __asm__ ("subcc %r7,%8,%2\n\ + subxcc %r5,%6,%1\n\ + subx %r3,%4,%0" \ + : "=r" ((USItype)(r2)), \ + "=&r" ((USItype)(r1)), \ + "=&r" ((USItype)(r0)) \ + : "%rJ" ((USItype)(x2)), \ + "rI" ((USItype)(y2)), \ + "%rJ" ((USItype)(x1)), \ + "rI" ((USItype)(y1)), \ + "%rJ" ((USItype)(x0)), \ + "rI" ((USItype)(y0)) \ + : "cc") + +#define __FP_FRAC_ADD_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \ + do { \ + /* We need to fool gcc, as we need to pass more than 10 \ + input/outputs. */ \ + register USItype _t1 __asm__ ("g1"), _t2 __asm__ ("g2"); \ + __asm__ __volatile__ ("\ + addcc %r8,%9,%1\n\ + addxcc %r6,%7,%0\n\ + addxcc %r4,%5,%%g2\n\ + addx %r2,%3,%%g1" \ + : "=&r" ((USItype)(r1)), \ + "=&r" ((USItype)(r0)) \ + : "%rJ" ((USItype)(x3)), \ + "rI" ((USItype)(y3)), \ + "%rJ" ((USItype)(x2)), \ + "rI" ((USItype)(y2)), \ + "%rJ" ((USItype)(x1)), \ + "rI" ((USItype)(y1)), \ + "%rJ" ((USItype)(x0)), \ + "rI" ((USItype)(y0)) \ + : "cc", "g1", "g2"); \ + __asm__ __volatile__ ("" : "=r" (_t1), "=r" (_t2)); \ + r3 = _t1; r2 = _t2; \ + } while (0) + +#define __FP_FRAC_SUB_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \ + do { \ + /* We need to fool gcc, as we need to pass more than 10 \ + input/outputs. */ \ + register USItype _t1 __asm__ ("g1"), _t2 __asm__ ("g2"); \ + __asm__ __volatile__ ("\ + subcc %r8,%9,%1\n\ + subxcc %r6,%7,%0\n\ + subxcc %r4,%5,%%g2\n\ + subx %r2,%3,%%g1" \ + : "=&r" ((USItype)(r1)), \ + "=&r" ((USItype)(r0)) \ + : "%rJ" ((USItype)(x3)), \ + "rI" ((USItype)(y3)), \ + "%rJ" ((USItype)(x2)), \ + "rI" ((USItype)(y2)), \ + "%rJ" ((USItype)(x1)), \ + "rI" ((USItype)(y1)), \ + "%rJ" ((USItype)(x0)), \ + "rI" ((USItype)(y0)) \ + : "cc", "g1", "g2"); \ + __asm__ __volatile__ ("" : "=r" (_t1), "=r" (_t2)); \ + r3 = _t1; r2 = _t2; \ + } while (0) + +#define __FP_FRAC_DEC_3(x2,x1,x0,y2,y1,y0) __FP_FRAC_SUB_3(x2,x1,x0,x2,x1,x0,y2,y1,y0) + +#define __FP_FRAC_DEC_4(x3,x2,x1,x0,y3,y2,y1,y0) __FP_FRAC_SUB_4(x3,x2,x1,x0,x3,x2,x1,x0,y3,y2,y1,y0) + +#define __FP_FRAC_ADDI_4(x3,x2,x1,x0,i) \ + __asm__ ("addcc %3,%4,%3\n\ + addxcc %2,%%g0,%2\n\ + addxcc %1,%%g0,%1\n\ + addx %0,%%g0,%0" \ + : "=&r" ((USItype)(x3)), \ + "=&r" ((USItype)(x2)), \ + "=&r" ((USItype)(x1)), \ + "=&r" ((USItype)(x0)) \ + : "rI" ((USItype)(i)), \ + "0" ((USItype)(x3)), \ + "1" ((USItype)(x2)), \ + "2" ((USItype)(x1)), \ + "3" ((USItype)(x0)) \ + : "cc") + +/* Obtain the current rounding mode. */ +#ifndef FP_ROUNDMODE +#define FP_ROUNDMODE ((_fcw >> 30) & 0x3) +#endif + +/* Exception flags. */ +#define FP_EX_INVALID (1 << 4) +#define FP_EX_OVERFLOW (1 << 3) +#define FP_EX_UNDERFLOW (1 << 2) +#define FP_EX_DIVZERO (1 << 1) +#define FP_EX_INEXACT (1 << 0) + +#define _FP_TININESS_AFTER_ROUNDING 0 + +#define _FP_DECL_EX \ + fpu_control_t _fcw __attribute__ ((unused)) = (FP_RND_NEAREST << 30) + +#define FP_INIT_ROUNDMODE \ +do { \ + _FPU_GETCW(_fcw); \ +} while (0) + +#define FP_TRAPPING_EXCEPTIONS ((_fcw >> 23) & 0x1f) +#define FP_INHIBIT_RESULTS ((_fcw >> 23) & _fex) + +/* Simulate exceptions using double arithmetics. */ +extern void ___Q_simulate_exceptions(int exc); + +#define FP_HANDLE_EXCEPTIONS \ +do { \ + if (!_fex) \ + { \ + /* This is the common case, so we do it inline. \ + * We need to clear cexc bits if any. \ + */ \ + extern unsigned long long ___Q_zero; \ + __asm__ __volatile__("ldd [%0], %%f30\n\t" \ + "faddd %%f30, %%f30, %%f30" \ + : : "r" (&___Q_zero) : "f30"); \ + } \ + else \ + ___Q_simulate_exceptions (_fex); \ +} while (0) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/Makefile b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/Makefile new file mode 100644 index 0000000000..2ff9853458 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/Makefile @@ -0,0 +1 @@ +sysdep-CFLAGS += -mcpu=v8 diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/addmul_1.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/addmul_1.S new file mode 100644 index 0000000000..20e37c2d0b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/addmul_1.S @@ -0,0 +1,118 @@ +! SPARC v8 __mpn_addmul_1 -- Multiply a limb vector with a limb and +! add the result to a second limb vector. + +! Copyright (C) 1992-2017 Free Software Foundation, Inc. + +! This file is part of the GNU MP Library. + +! The GNU MP Library is free software; you can redistribute it and/or modify +! it under the terms of the GNU Lesser General Public License as published by +! the Free Software Foundation; either version 2.1 of the License, or (at your +! option) any later version. + +! The GNU MP Library is distributed in the hope that it will be useful, but +! WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +! or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +! License for more details. + +! You should have received a copy of the GNU Lesser General Public License +! along with the GNU MP Library; see the file COPYING.LIB. If not, +! see <http://www.gnu.org/licenses/>. + + +! INPUT PARAMETERS +! res_ptr o0 +! s1_ptr o1 +! size o2 +! s2_limb o3 + +#include <sysdep.h> + +ENTRY(__mpn_addmul_1) + ld [%o1+0],%o4 ! 1 + sll %o2,4,%g1 + orcc %g0,%g0,%g2 + mov %o7,%g4 ! Save return address register + and %g1,(4-1)<<4,%g1 +1: call 2f + add %o7,3f-1b,%g3 +2: jmp %g3+%g1 + mov %g4,%o7 ! Restore return address register + + .align 4 +3: +LOC(00): + add %o0,-4,%o0 + b LOC(loop00) /* 4, 8, 12, ... */ + add %o1,-4,%o1 + nop +LOC(01): + b LOC(loop01) /* 1, 5, 9, ... */ + nop + nop + nop +LOC(10): + add %o0,-12,%o0 /* 2, 6, 10, ... */ + b LOC(loop10) + add %o1,4,%o1 + nop +LOC(11): + add %o0,-8,%o0 /* 3, 7, 11, ... */ + b LOC(loop11) + add %o1,-8,%o1 + nop + +LOC(loop): + addcc %g3,%g2,%g3 ! 1 + ld [%o1+4],%o4 ! 2 + rd %y,%g2 ! 1 + addx %g0,%g2,%g2 + ld [%o0+0],%g1 ! 2 + addcc %g1,%g3,%g3 + st %g3,[%o0+0] ! 1 +LOC(loop00): + umul %o4,%o3,%g3 ! 2 + ld [%o0+4],%g1 ! 2 + addxcc %g3,%g2,%g3 ! 2 + ld [%o1+8],%o4 ! 3 + rd %y,%g2 ! 2 + addx %g0,%g2,%g2 + nop + addcc %g1,%g3,%g3 + st %g3,[%o0+4] ! 2 +LOC(loop11): + umul %o4,%o3,%g3 ! 3 + addxcc %g3,%g2,%g3 ! 3 + ld [%o1+12],%o4 ! 4 + rd %y,%g2 ! 3 + add %o1,16,%o1 + addx %g0,%g2,%g2 + ld [%o0+8],%g1 ! 2 + addcc %g1,%g3,%g3 + st %g3,[%o0+8] ! 3 +LOC(loop10): + umul %o4,%o3,%g3 ! 4 + addxcc %g3,%g2,%g3 ! 4 + ld [%o1+0],%o4 ! 1 + rd %y,%g2 ! 4 + addx %g0,%g2,%g2 + ld [%o0+12],%g1 ! 2 + addcc %g1,%g3,%g3 + st %g3,[%o0+12] ! 4 + add %o0,16,%o0 + addx %g0,%g2,%g2 +LOC(loop01): + addcc %o2,-4,%o2 + bg LOC(loop) + umul %o4,%o3,%g3 ! 1 + + addcc %g3,%g2,%g3 ! 4 + rd %y,%g2 ! 4 + addx %g0,%g2,%g2 + ld [%o0+0],%g1 ! 2 + addcc %g1,%g3,%g3 + st %g3,[%o0+0] ! 4 + retl + addx %g0,%g2,%o0 + +END(__mpn_addmul_1) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/dotmul.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/dotmul.S new file mode 100644 index 0000000000..9b20cc3684 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/dotmul.S @@ -0,0 +1,13 @@ +/* + * Sparc v8 has multiply. + */ + +#include <sysdep.h> + +ENTRY(.mul) + + smul %o0, %o1, %o0 + retl + rd %y, %o1 + +END(.mul) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/mul_1.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/mul_1.S new file mode 100644 index 0000000000..49a2213c0f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/mul_1.S @@ -0,0 +1,102 @@ +! SPARC v8 __mpn_mul_1 -- Multiply a limb vector with a single limb and +! store the product in a second limb vector. + +! Copyright (C) 1992-2017 Free Software Foundation, Inc. + +! This file is part of the GNU MP Library. + +! The GNU MP Library is free software; you can redistribute it and/or modify +! it under the terms of the GNU Lesser General Public License as published by +! the Free Software Foundation; either version 2.1 of the License, or (at your +! option) any later version. + +! The GNU MP Library is distributed in the hope that it will be useful, but +! WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +! or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +! License for more details. + +! You should have received a copy of the GNU Lesser General Public License +! along with the GNU MP Library; see the file COPYING.LIB. If not, +! see <http://www.gnu.org/licenses/>. + + +! INPUT PARAMETERS +! res_ptr o0 +! s1_ptr o1 +! size o2 +! s2_limb o3 + +#include <sysdep.h> + +ENTRY(__mpn_mul_1) + sll %o2,4,%g1 + mov %o7,%g4 ! Save return address register + and %g1,(4-1)<<4,%g1 +1: call 2f + add %o7,3f-1b,%g3 +2: mov %g4,%o7 ! Restore return address register + jmp %g3+%g1 + ld [%o1+0],%o4 ! 1 + + .align 4 +3: +LOC(00): + add %o0,-4,%o0 + add %o1,-4,%o1 + b LOC(loop00) /* 4, 8, 12, ... */ + orcc %g0,%g0,%g2 +LOC(01): + b LOC(loop01) /* 1, 5, 9, ... */ + orcc %g0,%g0,%g2 + nop + nop +LOC(10): + add %o0,-12,%o0 /* 2, 6, 10, ... */ + add %o1,4,%o1 + b LOC(loop10) + orcc %g0,%g0,%g2 + nop +LOC(11): + add %o0,-8,%o0 /* 3, 7, 11, ... */ + add %o1,-8,%o1 + b LOC(loop11) + orcc %g0,%g0,%g2 + +LOC(loop): + addcc %g3,%g2,%g3 ! 1 + ld [%o1+4],%o4 ! 2 + st %g3,[%o0+0] ! 1 + rd %y,%g2 ! 1 +LOC(loop00): + umul %o4,%o3,%g3 ! 2 + addxcc %g3,%g2,%g3 ! 2 + ld [%o1+8],%o4 ! 3 + st %g3,[%o0+4] ! 2 + rd %y,%g2 ! 2 +LOC(loop11): + umul %o4,%o3,%g3 ! 3 + addxcc %g3,%g2,%g3 ! 3 + ld [%o1+12],%o4 ! 4 + add %o1,16,%o1 + st %g3,[%o0+8] ! 3 + rd %y,%g2 ! 3 +LOC(loop10): + umul %o4,%o3,%g3 ! 4 + addxcc %g3,%g2,%g3 ! 4 + ld [%o1+0],%o4 ! 1 + st %g3,[%o0+12] ! 4 + add %o0,16,%o0 + rd %y,%g2 ! 4 + addx %g0,%g2,%g2 +LOC(loop01): + addcc %o2,-4,%o2 + bg LOC(loop) + umul %o4,%o3,%g3 ! 1 + + addcc %g3,%g2,%g3 ! 4 + st %g3,[%o0+0] ! 4 + rd %y,%g2 ! 4 + retl + addx %g0,%g2,%o0 + +END(__mpn_mul_1) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/rem.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/rem.S new file mode 100644 index 0000000000..a2694e699e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/rem.S @@ -0,0 +1,21 @@ +/* + * Sparc v8 has divide. + */ + +#include <sysdep.h> + +ENTRY(.rem) + + sra %o0, 31, %o2 + wr %o2, 0, %y + nop + nop + nop + sdivcc %o0, %o1, %o2 + bvs,a 1f + xnor %o2, %g0, %o2 +1: smul %o2, %o1, %o2 + retl + sub %o0, %o2, %o0 + +END(.rem) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/sdiv.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/sdiv.S new file mode 100644 index 0000000000..bfc4acf2fa --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/sdiv.S @@ -0,0 +1,20 @@ +/* + * Sparc v8 has divide. + */ + +#include <sysdep.h> + +ENTRY(.div) + + sra %o0, 31, %o2 + wr %o2, 0, %y + nop + nop + nop + sdivcc %o0, %o1, %o0 + bvs,a 1f + xnor %o0, %g0, %o0 +1: retl + nop + +END(.div) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/submul_1.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/submul_1.S new file mode 100644 index 0000000000..b9cb561ef4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/submul_1.S @@ -0,0 +1,57 @@ +! SPARC v8 __mpn_submul_1 -- Multiply a limb vector with a limb and +! subtract the result from a second limb vector. + +! Copyright (C) 1992-2017 Free Software Foundation, Inc. + +! This file is part of the GNU MP Library. + +! The GNU MP Library is free software; you can redistribute it and/or modify +! it under the terms of the GNU Lesser General Public License as published by +! the Free Software Foundation; either version 2.1 of the License, or (at your +! option) any later version. + +! The GNU MP Library is distributed in the hope that it will be useful, but +! WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +! or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +! License for more details. + +! You should have received a copy of the GNU Lesser General Public License +! along with the GNU MP Library; see the file COPYING.LIB. If not, +! see <http://www.gnu.org/licenses/>. + + +! INPUT PARAMETERS +! res_ptr o0 +! s1_ptr o1 +! size o2 +! s2_limb o3 + +#include <sysdep.h> + +ENTRY(__mpn_submul_1) + sub %g0,%o2,%o2 ! negate ... + sll %o2,2,%o2 ! ... and scale size + sub %o1,%o2,%o1 ! o1 is offset s1_ptr + sub %o0,%o2,%g1 ! g1 is offset res_ptr + + mov 0,%o0 ! clear cy_limb + +LOC(loop): + ld [%o1+%o2],%o4 + ld [%g1+%o2],%g2 + umul %o4,%o3,%o5 + rd %y,%g3 + addcc %o5,%o0,%o5 + addx %g3,0,%o0 + subcc %g2,%o5,%g2 + addx %o0,0,%o0 + st %g2,[%g1+%o2] + + addcc %o2,4,%o2 + bne LOC(loop) + nop + + retl + nop + +END(__mpn_submul_1) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/udiv.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/udiv.S new file mode 100644 index 0000000000..e9cab4e4ef --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/udiv.S @@ -0,0 +1,16 @@ +/* + * Sparc v8 has divide. + */ + +#include <sysdep.h> + +ENTRY(.udiv) + + wr %g0, 0, %y + nop + nop + retl + udiv %o0, %o1, %o0 + +END(.udiv) +strong_alias (.udiv, __wrap_.udiv) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/umul.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/umul.S new file mode 100644 index 0000000000..cec454a7dd --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/umul.S @@ -0,0 +1,13 @@ +/* + * Sparc v8 has multiply. + */ + +#include <sysdep.h> + +ENTRY(.umul) + + umul %o0, %o1, %o0 + retl + rd %y, %o1 + +END(.umul) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/urem.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/urem.S new file mode 100644 index 0000000000..cc2689d514 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv8/urem.S @@ -0,0 +1,18 @@ +/* + * Sparc v8 has divide. + */ + +#include <sysdep.h> + +ENTRY(.urem) + + wr %g0, 0, %y + nop + nop + nop + udiv %o0, %o1, %o2 + umul %o2, %o1, %o2 + retl + sub %o0, %o2, %o0 + +END(.urem) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/Makefile b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/Makefile new file mode 100644 index 0000000000..526673e7b4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/Makefile @@ -0,0 +1,22 @@ +sysdep-CFLAGS += -mcpu=ultrasparc -Wa,-Av9a -mvis + +ifeq ($(have-as-vis3),yes) +ASFLAGS-.o += -Wa,-Av9d +ASFLAGS-.os += -Wa,-Av9d +ASFLAGS-.op += -Wa,-Av9d +ASFLAGS-.oS += -Wa,-Av9d +else +ASFLAGS-.o += -Wa,-Av9a +ASFLAGS-.os += -Wa,-Av9a +ASFLAGS-.op += -Wa,-Av9a +ASFLAGS-.oS += -Wa,-Av9a +endif + +# nscd uses atomic_spin_nop which in turn requires cpu_relax +ifeq ($(subdir),nscd) +routines += cpu_relax +endif + +ifeq ($(subdir), nptl) +libpthread-routines += cpu_relax +endif diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/addmul_1.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/addmul_1.S new file mode 100644 index 0000000000..7d3114a846 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/addmul_1.S @@ -0,0 +1,81 @@ +! SPARC v9 32-bit __mpn_addmul_1 -- Multiply a limb vector with a limb +! and add the result to a second limb vector. +! +! Copyright (C) 2013-2017 Free Software Foundation, Inc. +! This file is part of the GNU C Library. +! Contributed by David S. Miller <davem@davemloft.net> +! +! The GNU C Library is free software; you can redistribute it and/or +! modify it under the terms of the GNU Lesser General Public +! License as published by the Free Software Foundation; either +! version 2.1 of the License, or (at your option) any later version. +! +! The GNU C Library is distributed in the hope that it will be useful, +! but WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! Lesser General Public License for more details. +! +! You should have received a copy of the GNU Lesser General Public +! License along with the GNU C Library; if not, see +! <http://www.gnu.org/licenses/>. + +#include <sysdep.h> + +#define res_ptr %i0 +#define s1_ptr %i1 +#define sz_arg %i2 +#define s2l_arg %i3 +#define sz %o4 +#define carry %o5 +#define s2_limb %g1 +#define tmp1 %l0 +#define tmp2 %l1 +#define tmp3 %l2 +#define tmp4 %l3 +#define tmp64_1 %g3 +#define tmp64_2 %o3 + +ENTRY(__mpn_addmul_1) + save %sp, -96, %sp + srl sz_arg, 0, sz + srl s2l_arg, 0, s2_limb + subcc sz, 1, sz + be,pn %icc, .Lfinal_limb + clr carry + +.Lloop: + lduw [s1_ptr + 0x00], tmp1 + lduw [res_ptr + 0x00], tmp3 + lduw [s1_ptr + 0x04], tmp2 + lduw [res_ptr + 0x04], tmp4 + mulx tmp1, s2_limb, tmp64_1 + add s1_ptr, 8, s1_ptr + mulx tmp2, s2_limb, tmp64_2 + sub sz, 2, sz + add res_ptr, 8, res_ptr + add tmp3, tmp64_1, tmp64_1 + add carry, tmp64_1, tmp64_1 + stw tmp64_1, [res_ptr - 0x08] + srlx tmp64_1, 32, carry + add tmp4, tmp64_2, tmp64_2 + add carry, tmp64_2, tmp64_2 + stw tmp64_2, [res_ptr - 0x04] + brgz sz, .Lloop + srlx tmp64_2, 32, carry + + brlz,pt sz, .Lfinish + nop + +.Lfinal_limb: + lduw [s1_ptr + 0x00], tmp1 + lduw [res_ptr + 0x00], tmp3 + mulx tmp1, s2_limb, tmp64_1 + add tmp3, tmp64_1, tmp64_1 + add carry, tmp64_1, tmp64_1 + stw tmp64_1, [res_ptr + 0x00] + srlx tmp64_1, 32, carry + +.Lfinish: + jmpl %i7 + 0x8, %g0 + restore carry, 0, %o0 +END(__mpn_addmul_1) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/atomic-machine.h b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/atomic-machine.h new file mode 100644 index 0000000000..2b36dfc94d --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/atomic-machine.h @@ -0,0 +1,108 @@ +/* Atomic operations. sparcv9 version. + Copyright (C) 2003-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jakub@redhat.com>, 2003. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <stdint.h> + +typedef int8_t atomic8_t; +typedef uint8_t uatomic8_t; +typedef int_fast8_t atomic_fast8_t; +typedef uint_fast8_t uatomic_fast8_t; + +typedef int16_t atomic16_t; +typedef uint16_t uatomic16_t; +typedef int_fast16_t atomic_fast16_t; +typedef uint_fast16_t uatomic_fast16_t; + +typedef int32_t atomic32_t; +typedef uint32_t uatomic32_t; +typedef int_fast32_t atomic_fast32_t; +typedef uint_fast32_t uatomic_fast32_t; + +typedef int64_t atomic64_t; +typedef uint64_t uatomic64_t; +typedef int_fast64_t atomic_fast64_t; +typedef uint_fast64_t uatomic_fast64_t; + +typedef intptr_t atomicptr_t; +typedef uintptr_t uatomicptr_t; +typedef intmax_t atomic_max_t; +typedef uintmax_t uatomic_max_t; + +#define __HAVE_64B_ATOMICS 0 +#define USE_ATOMIC_COMPILER_BUILTINS 0 + +/* XXX Is this actually correct? */ +#define ATOMIC_EXCHANGE_USES_CAS 0 + + +#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \ + (abort (), (__typeof (*mem)) 0) + +#define __arch_compare_and_exchange_val_16_acq(mem, newval, oldval) \ + (abort (), (__typeof (*mem)) 0) + +#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \ +({ \ + __typeof (*(mem)) __acev_tmp; \ + __typeof (mem) __acev_mem = (mem); \ + if (__builtin_constant_p (oldval) && (oldval) == 0) \ + __asm __volatile ("cas [%3], %%g0, %0" \ + : "=r" (__acev_tmp), "=m" (*__acev_mem) \ + : "m" (*__acev_mem), "r" (__acev_mem), \ + "0" (newval) : "memory"); \ + else \ + __asm __volatile ("cas [%4], %2, %0" \ + : "=r" (__acev_tmp), "=m" (*__acev_mem) \ + : "r" (oldval), "m" (*__acev_mem), "r" (__acev_mem), \ + "0" (newval) : "memory"); \ + __acev_tmp; }) + +/* This can be implemented if needed. */ +#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \ + (abort (), (__typeof (*mem)) 0) + +#define atomic_exchange_acq(mem, newvalue) \ + ({ __typeof (*(mem)) __oldval; \ + __typeof (mem) __memp = (mem); \ + __typeof (*(mem)) __value = (newvalue); \ + \ + if (sizeof (*(mem)) == 4) \ + __asm ("swap %0, %1" \ + : "=m" (*__memp), "=r" (__oldval) \ + : "m" (*__memp), "1" (__value) : "memory"); \ + else \ + abort (); \ + __oldval; }) + +#define atomic_compare_and_exchange_val_24_acq(mem, newval, oldval) \ + atomic_compare_and_exchange_val_acq (mem, newval, oldval) + +#define atomic_exchange_24_rel(mem, newval) \ + atomic_exchange_rel (mem, newval) + +#define atomic_full_barrier() \ + __asm __volatile ("membar #LoadLoad | #LoadStore" \ + " | #StoreLoad | #StoreStore" : : : "memory") +#define atomic_read_barrier() \ + __asm __volatile ("membar #LoadLoad | #LoadStore" : : : "memory") +#define atomic_write_barrier() \ + __asm __volatile ("membar #LoadStore | #StoreStore" : : : "memory") + +extern void __cpu_relax (void); +#define atomic_spin_nop() __cpu_relax () diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/backtrace.h b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/backtrace.h new file mode 100644 index 0000000000..8d6c756717 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/backtrace.h @@ -0,0 +1,7 @@ +/* Private macros for guiding the backtrace implementation, sparc32 v9 + version. */ + +#define backtrace_flush_register_windows() \ + asm volatile ("flushw") + +#define BACKTRACE_STACK_BIAS 0 diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/bzero.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/bzero.c new file mode 100644 index 0000000000..37f0f6f993 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/bzero.c @@ -0,0 +1 @@ +/* bzero is in memset.S */ diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/cpu_relax.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/cpu_relax.S new file mode 100644 index 0000000000..41a5e72b25 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/cpu_relax.S @@ -0,0 +1 @@ +#include <sysdeps/sparc/sparc64/cpu_relax.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/dotmul.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/dotmul.S new file mode 100644 index 0000000000..811cf1e89e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/dotmul.S @@ -0,0 +1,17 @@ +/* + * Sparc v9 has multiply. + */ + +#include <sysdep.h> + + .text + .align 32 +ENTRY(.mul) + + sra %o0, 0, %o0 + sra %o1, 0, %o1 + mulx %o0, %o1, %o0 + retl + srax %o0, 32, %o1 + +END(.mul) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile new file mode 100644 index 0000000000..322e300097 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile @@ -0,0 +1,14 @@ +ifeq ($(subdir),math) +ifeq ($(have-as-vis3),yes) +libm-sysdep_routines += m_copysignf-vis3 m_copysign-vis3 s_fabs-vis3 \ + s_fabsf-vis3 s_llrintf-vis3 s_llrint-vis3 \ + s_rintf-vis3 s_rint-vis3 \ + w_sqrt_compat-vis3 w_sqrtf_compat-vis3 \ + s_fmaf-vis3 s_fma-vis3 s_nearbyint-vis3 \ + s_nearbyintf-vis3 s_fdimf-vis3 s_fdim-vis3 +sysdep_routines += s_copysignf-vis3 s_copysign-vis3 + +CFLAGS-s_fdimf-vis3.c += -Wa,-Av9d -mvis3 +CFLAGS-s_fdim-vis3.c += -Wa,-Av9d -mvis3 +endif +endif diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign-vis3.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign-vis3.S new file mode 100644 index 0000000000..aa8b6169a1 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign-vis3.S @@ -0,0 +1,30 @@ +/* copysign function, sparc32 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__copysign_vis3) + sethi %hi(0x80000000), %g1 + and %o2, %g1, %o4 + andn %o0, %g1, %o0 + or %o0, %o4, %o0 + movwtos %o0, %f0 + retl + movwtos %o1, %f1 +END (__copysign_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign.S new file mode 100644 index 0000000000..cdd98c00f4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysign.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(copysign) + +weak_alias (__copysign, copysign) + +# undef weak_alias +# define weak_alias(a, b) + +#define __copysign __copysign_generic + +#include "../../../fpu/s_copysign.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf-vis3.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf-vis3.S new file mode 100644 index 0000000000..0f702b32aa --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf-vis3.S @@ -0,0 +1,29 @@ +/* float copysign function, sparc32 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__copysignf_vis3) + sethi %hi(0x80000000), %g1 + and %o1, %g1, %o4 + andn %o0, %g1, %o0 + or %o0, %o4, %o0 + retl + movwtos %o0, %f0 +END (__copysignf_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf.S new file mode 100644 index 0000000000..cd409550de --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_copysignf.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(copysignf) + +weak_alias (__copysignf, copysignf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __copysignf __copysignf_generic + +#include "../../../fpu/s_copysignf.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S new file mode 100644 index 0000000000..21078eb00f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S @@ -0,0 +1,26 @@ +/* Float absolute value, sparc32+v9 vis3 version. + Copyright (C) 2011-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__fabs_vis3) + movwtos %o0, %f0 + movwtos %o1, %f1 + retl + fabsd %f0, %f0 +END (__fabs_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S new file mode 100644 index 0000000000..86c63989a4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(fabs) + +weak_alias (__fabs, fabs) + +# undef weak_alias +# define weak_alias(a, b) + +#define __fabs __fabs_generic + +#include "../s_fabs.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S new file mode 100644 index 0000000000..82816a185e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S @@ -0,0 +1,26 @@ +/* Float absolute value, sparc32 vis3 version. + Copyright (C) 2006-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jakub@redhat.com>, 2006. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__fabsf_vis3) + movwtos %o0, %f0 + retl + fabss %f0, %f0 +END (__fabsf_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S new file mode 100644 index 0000000000..0f2e11e01f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(fabsf) + +weak_alias (__fabsf, fabsf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __fabsf __fabsf_generic + +#include "../../../fpu/s_fabsf.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim-vis3.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim-vis3.c new file mode 100644 index 0000000000..8c3666da7a --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim-vis3.c @@ -0,0 +1,25 @@ +/* Compute positive difference, sparc 32-bit+v9+vis3. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math.h> + +#define __fdim __fdim_vis3 +#define declare_mgen_alias(t, f) +#define M_LIBM_NEED_COMPAT(f) 0 + +#include <math/s_fdim.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim.c new file mode 100644 index 0000000000..417b8690d6 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim.c @@ -0,0 +1,33 @@ +/* Compute positive difference, sparc 32-bit. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifdef HAVE_AS_VIS3_SUPPORT +# include <sparc-ifunc.h> +# include <math.h> + +extern double __fdim_vis3 (double, double); +extern double __fdim_generic (double, double); + +sparc_libm_ifunc(__fdim, hwcap & HWCAP_SPARC_VIS3 ? __fdim_vis3 : __fdim_generic); +weak_alias (__fdim, fdim) + +# define __fdim __fdim_generic +# define declare_mgen_alias(t, f) +#endif + +#include <math/s_fdim.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf-vis3.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf-vis3.c new file mode 100644 index 0000000000..a8ae7fa3d9 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf-vis3.c @@ -0,0 +1,24 @@ +/* Float compute positive difference, sparc 32-bit+v9+vis3. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math.h> + +#define __fdimf __fdimf_vis3 +#define declare_mgen_alias(t, f) + +#include <math/s_fdimf.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf.c new file mode 100644 index 0000000000..cf1dc9ec6c --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf.c @@ -0,0 +1,34 @@ +/* Float compute positive difference, sparc 32-bit. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifdef HAVE_AS_VIS3_SUPPORT +# include <sparc-ifunc.h> +# include <math.h> + +extern float __fdimf_vis3 (float, float); +extern float __fdimf_generic (float, float); + +sparc_libm_ifunc(__fdimf, hwcap & HWCAP_SPARC_VIS3 ? __fdimf_vis3 : __fdimf_generic); +weak_alias (__fdimf, fdimf) + +# define __fdimf __fdimf_generic +# define declare_mgen_alias(t, f) + +#endif + +#include <math/s_fdimf.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fma-vis3.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fma-vis3.S new file mode 100644 index 0000000000..2e7d2111a3 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fma-vis3.S @@ -0,0 +1,31 @@ +/* fma function, sparc32 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__fma_vis3) + movwtos %o0, %f0 + movwtos %o1, %f1 + movwtos %o2, %f2 + movwtos %o3, %f3 + movwtos %o4, %f4 + movwtos %o5, %f5 + retl + fmaddd %f0, %f2, %f4, %f0 +END (__fma_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fma.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fma.c new file mode 100644 index 0000000000..3f2f1622c8 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fma.c @@ -0,0 +1,14 @@ +#ifdef HAVE_AS_VIS3_SUPPORT +# include <sparc-ifunc.h> +# include <math.h> + +extern double __fma_vis3 (double, double, double); +extern double __fma_generic (double, double, double); + +sparc_libm_ifunc(__fma, hwcap & HWCAP_SPARC_FMAF ? __fma_vis3 : __fma_generic); +weak_alias (__fma, fma) + +# define __fma __fma_generic +#endif + +#include <sysdeps/ieee754/dbl-64/s_fma.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fmaf-vis3.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fmaf-vis3.S new file mode 100644 index 0000000000..0bd443a094 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fmaf-vis3.S @@ -0,0 +1,28 @@ +/* fmaf function, sparc32 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__fmaf_vis3) + movwtos %o0, %f1 + movwtos %o1, %f3 + movwtos %o2, %f5 + retl + fmadds %f1, %f3, %f5, %f0 +END (__fmaf_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fmaf.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fmaf.c new file mode 100644 index 0000000000..7a273a3b13 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fmaf.c @@ -0,0 +1,14 @@ +#ifdef HAVE_AS_VIS3_SUPPORT +# include <sparc-ifunc.h> +# include <math.h> + +extern float __fmaf_vis3 (float, float, float); +extern float __fmaf_generic (float, float, float); + +sparc_libm_ifunc(__fmaf, hwcap & HWCAP_SPARC_FMAF ? __fmaf_vis3 : __fmaf_generic); +weak_alias (__fmaf, fmaf) + +# define __fmaf __fmaf_generic +#endif + +#include <sysdeps/ieee754/dbl-64/s_fmaf.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S new file mode 100644 index 0000000000..7b8616c97f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S @@ -0,0 +1,58 @@ +/* llrint(), sparc32 v9 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__llrint_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + + or %o0, %o1, %o0 + fzero ZERO + + movxtod %o0, %f0 + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + for %f0, SIGN_BIT, %f0 + fdtox %f0, %f4 + movstouw %f4, %o0 + retl + movstouw %f5, %o1 +END (__llrint_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S new file mode 100644 index 0000000000..fd23041404 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S @@ -0,0 +1,24 @@ +#include <sparc-ifunc.h> +#include <math_ldbl_opt.h> + +SPARC_ASM_VIS3_IFUNC(llrint) + +weak_alias (__llrint, llrint) + +strong_alias (__llrint, __lllrint) +weak_alias (__lllrint, lllrint) + +#if LONG_DOUBLE_COMPAT(libm, GLIBC_2_1) +compat_symbol (libm, __llrint, llrintl, GLIBC_2_1) +#endif + +# undef weak_alias +# define weak_alias(a, b) +# undef strong_alias +# define strong_alias(a, b) +# undef compat_symbol +# define compat_symbol(a, b, c, d) + +#define __llrint __llrint_generic + +#include "../s_llrint.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S new file mode 100644 index 0000000000..a3801893c5 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S @@ -0,0 +1,54 @@ +/* llrintf(), sparc32 v9 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__llrintf_vis3) + movwtos %o0, %f1 + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + + movwtos %o2, %f16 + fabss %f1, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + fstox %f0, %f4 + movstouw %f4, %o0 + retl + movstouw %f5, %o1 +END (__llrintf_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S new file mode 100644 index 0000000000..8af5244e7e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S @@ -0,0 +1,17 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(llrintf) + +weak_alias (__llrintf, llrintf) + +strong_alias (__llrintf, __lllrintf) +weak_alias (__lllrintf, lllrintf) + +# undef weak_alias +# define weak_alias(a, b) +# undef strong_alias +# define strong_alias(a, b) + +#define __llrintf __llrintf_generic + +#include "../s_llrintf.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S new file mode 100644 index 0000000000..612446b4ae --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S @@ -0,0 +1,66 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc32 v9 vis3 version. + + Copyright (C) 2013-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <math_ldbl_opt.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyint_vis3) + sllx %o0, 32, %o0 + or %o0, %o1, %o0 + movxtod %o0, %f0 + fcmpd %fcc3, %f0, %f0 /* Check for sNaN */ + st %fsr, [%sp + 88] + sethi %hi(TWO_FIFTYTWO), %o2 + sethi %hi(0xf8003e0), %o5 + ld [%sp + 88], %o4 + or %o5, %lo(0xf8003e0), %o5 + andn %o4, %o5, %o4 + fzero ZERO + st %o4, [%sp + 80] + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + ld [%sp + 80], %fsr + movxtod %o2, %f16 + fabsd %f0, %f14 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + for %f0, SIGN_BIT, %f0 + retl + ld [%sp + 88], %fsr +END (__nearbyint_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint.S new file mode 100644 index 0000000000..47da9eaafe --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint.S @@ -0,0 +1,19 @@ +#include <sparc-ifunc.h> +#include <math_ldbl_opt.h> + +SPARC_ASM_VIS3_IFUNC(nearbyint) + +weak_alias (__nearbyint, nearbyint) + +#if LONG_DOUBLE_COMPAT(libm, GLIBC_2_1) +compat_symbol (libm, __nearbyint, nearbyintl, GLIBC_2_1) +#endif + +# undef weak_alias +# define weak_alias(a, b) +# undef compat_symbol +# define compat_symbol(a, b, c, d) + +#define __nearbyint __nearbyint_generic + +#include "../s_nearbyint.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S new file mode 100644 index 0000000000..2ac91a01c3 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S @@ -0,0 +1,62 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc32 v9 vis3 version. + + Copyright (C) 2013-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyintf_vis3) + movwtos %o0, %f1 + fcmps %fcc3, %f1, %f1 /* Check for sNaN */ + st %fsr, [%sp + 88] + sethi %hi(TWO_TWENTYTHREE), %o2 + sethi %hi(0xf8003e0), %o5 + ld [%sp + 88], %o4 + fzeros ZERO + or %o5, %lo(0xf8003e0), %o5 + fnegs ZERO, SIGN_BIT + andn %o4, %o5, %o4 + st %o4, [%sp + 80] + ld [%sp + 80], %fsr + movwtos %o2, %f16 + fabss %f1, %f14 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + retl + ld [%sp + 88], %fsr +END (__nearbyintf_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf.S new file mode 100644 index 0000000000..95100c1bfc --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(nearbyintf) + +weak_alias (__nearbyintf, nearbyintf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __nearbyintf __nearbyintf_generic + +#include "../s_nearbyintf.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S new file mode 100644 index 0000000000..39cb43706a --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S @@ -0,0 +1,55 @@ +/* Round float to int floating-point values, sparc32 v9 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__rint_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + + or %o0, %o1, %o0 + fzero ZERO + + movxtod %o0, %f0 + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + retl + for %f0, SIGN_BIT, %f0 +END (__rint_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S new file mode 100644 index 0000000000..de893faebf --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S @@ -0,0 +1,19 @@ +#include <sparc-ifunc.h> +#include <math_ldbl_opt.h> + +SPARC_ASM_VIS3_IFUNC(rint) + +weak_alias (__rint, rint) + +#if LONG_DOUBLE_COMPAT(libm, GLIBC_2_0) +compat_symbol (libm, __rint, rintl, GLIBC_2_0) +#endif + +# undef weak_alias +# define weak_alias(a, b) +# undef compat_symbol +# define compat_symbol(a, b, c, d) + +#define __rint __rint_generic + +#include "../s_rint.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S new file mode 100644 index 0000000000..26c9d82ede --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S @@ -0,0 +1,51 @@ +/* Round float to int floating-point values, sparc32 v9 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__rintf_vis3) + movwtos %o0, %f1 + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + + movwtos %o2, %f16 + fabss %f1, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + retl + fors %f0, SIGN_BIT, %f0 +END (__rintf_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S new file mode 100644 index 0000000000..38fd936086 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(rintf) + +weak_alias (__rintf, rintf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __rintf __rintf_generic + +#include "../s_rintf.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt_compat-vis3.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt_compat-vis3.S new file mode 100644 index 0000000000..06ff449150 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt_compat-vis3.S @@ -0,0 +1,49 @@ +/* sqrt function. sparc32 v9 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__sqrt_vis3) + movwtos %o0, %f0 + fzero %f8 + movwtos %o1, %f1 + fcmpd %f0, %f8 + fbl 1f + nop +8: retl + fsqrtd %f0, %f0 +1: +#ifdef SHARED + SETUP_PIC_REG_LEAF(o5, g1) + sethi %gdop_hix22(_LIB_VERSION), %g1 + xor %g1, %gdop_lox10(_LIB_VERSION), %g1 + ld [%o5 + %g1], %g1, %gdop(_LIB_VERSION) +#else + sethi %hi(_LIB_VERSION), %g1 + or %g1, %lo(_LIB_VERSION), %g1 +#endif + ld [%g1], %g1 + cmp %g1, -1 + be 8b + mov %o0, %o2 + mov %o1, %o3 + mov 26, %o4 + mov %o7, %g1 + call __kernel_standard + mov %g1, %o7 +END (__sqrt_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt_compat.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt_compat.S new file mode 100644 index 0000000000..1ccac19e29 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt_compat.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(sqrt) + +weak_alias (__sqrt, sqrt) + +# undef weak_alias +# define weak_alias(a, b) + +#define __sqrt __sqrt_generic + +#include "../w_sqrt_compat.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf_compat-vis3.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf_compat-vis3.S new file mode 100644 index 0000000000..5b21523fc0 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf_compat-vis3.S @@ -0,0 +1,47 @@ +/* sqrtf function. sparc32 v9 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__sqrtf_vis3) + movwtos %o0, %f0 + fzeros %f8 + fcmps %f0, %f8 + fbl 1f + nop +8: retl + fsqrts %f0, %f0 +1: +#ifdef SHARED + SETUP_PIC_REG_LEAF(o5, g1) + sethi %gdop_hix22(_LIB_VERSION), %g1 + xor %g1, %gdop_lox10(_LIB_VERSION), %g1 + ld [%o5 + %g1], %g1, %gdop(_LIB_VERSION) +#else + sethi %hi(_LIB_VERSION), %g1 + or %g1, %lo(_LIB_VERSION), %g1 +#endif + ld [%g1], %g1 + cmp %g1, -1 + be 8b + mov %o0, %o1 + mov 126, %o2 + mov %o7, %g1 + call __kernel_standard_f + mov %g1, %o7 +END (__sqrtf_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf_compat.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf_compat.S new file mode 100644 index 0000000000..f0e759a2c8 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf_compat.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(sqrtf) + +weak_alias (__sqrtf, sqrtf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __sqrtf __sqrtf_generic + +#include "../w_sqrtf_compat.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_fabs.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_fabs.S new file mode 100644 index 0000000000..bf51739b5a --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_fabs.S @@ -0,0 +1,28 @@ +/* Float absolute value, sparc32+v9 version. + Copyright (C) 2011-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__fabs) + st %o0, [%sp+72] + st %o1, [%sp+76] + ldd [%sp+72], %f0 + retl + fabsd %f0, %f0 +END (__fabs) +weak_alias (__fabs, fabs) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_isnan.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_isnan.S new file mode 100644 index 0000000000..62c4fc3593 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_isnan.S @@ -0,0 +1,40 @@ +/* isnan(). sparc32 v9 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <math_ldbl_opt.h> + +ENTRY (__isnan) + sethi %hi(0x7ff00000), %g1 + sllx %o0, 33, %o0 + sllx %g1, 32, %g1 + srlx %o0, 1, %o0 + or %o0, %o1, %o0 + sub %g1, %o0, %o0 + retl + srlx %o0, 63, %o0 +END (__isnan) +hidden_def (__isnan) +weak_alias (__isnan, isnan) + +#if !IS_IN (libm) +# if LONG_DOUBLE_COMPAT(libc, GLIBC_2_0) +compat_symbol (libc, __isnan, __isnanl, GLIBC_2_0); +compat_symbol (libc, isnan, isnanl, GLIBC_2_0); +# endif +#endif diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_llrint.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_llrint.S new file mode 100644 index 0000000000..62bd9f50c7 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_llrint.S @@ -0,0 +1,72 @@ +/* llrint(), sparc32 v9 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <math_ldbl_opt.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__llrint) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + + or %o0, %o1, %o0 + fzero ZERO + + stx %o0, [%sp + 72] + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + + ldd [%sp + 72], %f0 + + stx %o2, [%sp + 72] + fabsd %f0, %f14 + + ldd [%sp + 72], %f16 + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + for %f0, SIGN_BIT, %f0 + fdtox %f0, %f4 + std %f4, [%sp + 72] + retl + ldd [%sp + 72], %o0 +END (__llrint) +weak_alias (__llrint, llrint) + +#if LONG_DOUBLE_COMPAT(libm, GLIBC_2_1) +compat_symbol (libm, __llrint, llrintl, GLIBC_2_1) +#endif diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_llrintf.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_llrintf.S new file mode 100644 index 0000000000..cda284b124 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_llrintf.S @@ -0,0 +1,62 @@ +/* llrintf(), sparc32 v9 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__llrintf) + st %o0, [%sp + 68] + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + + ld [%sp + 68], %f1 + fnegs ZERO, SIGN_BIT + + st %o2, [%sp + 68] + fabss %f1, %f14 + + ld [%sp + 68], %f16 + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + fstox %f0, %f4 + std %f4, [%sp + 72] + retl + ldd [%sp + 72], %o0 +END (__llrintf) +weak_alias (__llrintf, llrintf) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_lrintf.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_lrintf.S new file mode 100644 index 0000000000..a242b755d0 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_lrintf.S @@ -0,0 +1,62 @@ +/* lrintf(), sparc32 v9 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__lrintf) + st %o0, [%sp + 68] + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + + ld [%sp + 68], %f1 + fnegs ZERO, SIGN_BIT + + st %o2, [%sp + 68] + fabss %f1, %f14 + + ld [%sp + 68], %f16 + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + fstoi %f0, %f3 + st %f3, [%sp + 68] + retl + ld [%sp + 68], %o0 +END (__lrintf) +weak_alias (__lrintf, lrintf) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S new file mode 100644 index 0000000000..c26d2e3e44 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S @@ -0,0 +1,73 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc32 v9 version. + + Copyright (C) 2013-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <math_ldbl_opt.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyint) + sllx %o0, 32, %o0 + or %o0, %o1, %o0 + stx %o0, [%sp + 72] + ldd [%sp + 72], %f0 + fcmpd %fcc3, %f0, %f0 /* Check for sNaN */ + st %fsr, [%sp + 88] + sethi %hi(TWO_FIFTYTWO), %o2 + sethi %hi(0xf8003e0), %o5 + ld [%sp + 88], %o4 + or %o5, %lo(0xf8003e0), %o5 + andn %o4, %o5, %o4 + fzero ZERO + st %o4, [%sp + 80] + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + ld [%sp + 80], %fsr + stx %o2, [%sp + 72] + fabsd %f0, %f14 + ldd [%sp + 72], %f16 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + for %f0, SIGN_BIT, %f0 + retl + ld [%sp + 88], %fsr +END (__nearbyint) +weak_alias (__nearbyint, nearbyint) + +#if LONG_DOUBLE_COMPAT(libm, GLIBC_2_1) +compat_symbol (libm, __nearbyint, nearbyintl, GLIBC_2_1) +#endif diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S new file mode 100644 index 0000000000..1e65c79ee6 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S @@ -0,0 +1,65 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc32 v9 version. + + Copyright (C) 2013-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyintf) + st %o0, [%sp + 68] + ld [%sp + 68], %f1 + fcmps %fcc3, %f1, %f1 /* Check for sNaN */ + st %fsr, [%sp + 88] + sethi %hi(TWO_TWENTYTHREE), %o2 + sethi %hi(0xf8003e0), %o5 + ld [%sp + 88], %o4 + fzeros ZERO + or %o5, %lo(0xf8003e0), %o5 + fnegs ZERO, SIGN_BIT + andn %o4, %o5, %o4 + st %o4, [%sp + 80] + ld [%sp + 80], %fsr + st %o2, [%sp + 68] + fabss %f1, %f14 + ld [%sp + 68], %f16 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + retl + ld [%sp + 88], %fsr +END (__nearbyintf) +weak_alias (__nearbyintf, nearbyintf) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_rint.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_rint.S new file mode 100644 index 0000000000..f3560ccc79 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_rint.S @@ -0,0 +1,69 @@ +/* Round float to int floating-point values, sparc32 v9 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <math_ldbl_opt.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__rint) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + + or %o0, %o1, %o0 + fzero ZERO + + stx %o0, [%sp + 72] + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + + ldd [%sp + 72], %f0 + + stx %o2, [%sp + 72] + fabsd %f0, %f14 + + ldd [%sp + 72], %f16 + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + retl + for %f0, SIGN_BIT, %f0 +END (__rint) +weak_alias (__rint, rint) + +#if LONG_DOUBLE_COMPAT(libm, GLIBC_2_0) +compat_symbol (libm, __rint, rintl, GLIBC_2_0) +#endif diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_rintf.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_rintf.S new file mode 100644 index 0000000000..dfdae9dcdd --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/s_rintf.S @@ -0,0 +1,59 @@ +/* Round float to int floating-point values, sparc32 v9 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__rintf) + st %o0, [%sp + 68] + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + + ld [%sp + 68], %f1 + fnegs ZERO, SIGN_BIT + + st %o2, [%sp + 68] + fabss %f1, %f14 + + ld [%sp + 68], %f16 + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + retl + fors %f0, SIGN_BIT, %f0 +END (__rintf) +weak_alias (__rintf, rintf) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/w_sqrt_compat.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/w_sqrt_compat.S new file mode 100644 index 0000000000..4415a82024 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/w_sqrt_compat.S @@ -0,0 +1,51 @@ +/* sqrt function. sparc32 v9 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__sqrt) + std %o0, [%sp + 80] + fzero %f8 + ldd [%sp + 80], %f0 + fcmpd %f0, %f8 + fbl 1f + nop +8: retl + fsqrtd %f0, %f0 +1: +#ifdef SHARED + SETUP_PIC_REG_LEAF(o5, g1) + sethi %gdop_hix22(_LIB_VERSION), %g1 + xor %g1, %gdop_lox10(_LIB_VERSION), %g1 + ld [%o5 + %g1], %g1, %gdop(_LIB_VERSION) +#else + sethi %hi(_LIB_VERSION), %g1 + or %g1, %lo(_LIB_VERSION), %g1 +#endif + ld [%g1], %g1 + cmp %g1, -1 + be 8b + mov %o0, %o2 + mov %o1, %o3 + mov 26, %o4 + mov %o7, %g1 + call __kernel_standard + mov %g1, %o7 +END (__sqrt) + +weak_alias (__sqrt, sqrt) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/w_sqrtf_compat.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/w_sqrtf_compat.S new file mode 100644 index 0000000000..1c3c97f8e9 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/fpu/w_sqrtf_compat.S @@ -0,0 +1,50 @@ +/* sqrtf function. sparc32 v9 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__sqrtf) + st %o0, [%sp + 72] + fzeros %f8 + ld [%sp + 72], %f0 + fcmps %f0, %f8 + fbl 1f + nop +8: retl + fsqrts %f0, %f0 +1: +#ifdef SHARED + SETUP_PIC_REG_LEAF(o5, g1) + sethi %gdop_hix22(_LIB_VERSION), %g1 + xor %g1, %gdop_lox10(_LIB_VERSION), %g1 + ld [%o5 + %g1], %g1, %gdop(_LIB_VERSION) +#else + sethi %hi(_LIB_VERSION), %g1 + or %g1, %lo(_LIB_VERSION), %g1 +#endif + ld [%g1], %g1 + cmp %g1, -1 + be 8b + mov %o0, %o1 + mov 126, %o2 + mov %o7, %g1 + call __kernel_standard_f + mov %g1, %o7 +END (__sqrtf) + +weak_alias (__sqrtf, sqrtf) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/hp-timing.h b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/hp-timing.h new file mode 100644 index 0000000000..2dfa2d2265 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/hp-timing.h @@ -0,0 +1,36 @@ +/* High precision, low overhead timing functions. sparcv9 version. + Copyright (C) 2001-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@redhat.com>, 2001. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _HP_TIMING_H +#define _HP_TIMING_H 1 + +#define HP_TIMING_AVAIL (1) +#define HP_SMALL_TIMING_AVAIL (1) +#define HP_TIMING_INLINE (1) + +typedef unsigned long long int hp_timing_t; + +#define HP_TIMING_NOW(Var) \ + __asm__ __volatile__ ("rd %%tick, %L0\n\t" \ + "srlx %L0, 32, %H0" \ + : "=r" (Var)) + +#include <hp-timing-common.h> + +#endif /* hp-timing.h */ diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/memchr.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/memchr.S new file mode 100644 index 0000000000..c5dfbef184 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/memchr.S @@ -0,0 +1,4 @@ +#define ASI_PNF 0x82 +#define ASI_BLK_P 0xf0 +#define XCC icc +#include <sparc64/memchr.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/memcmp.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/memcmp.S new file mode 100644 index 0000000000..44878f4486 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/memcmp.S @@ -0,0 +1,4 @@ +#define ASI_PNF 0x82 +#define ASI_BLK_P 0xf0 +#define XCC icc +#include <sparc64/memcmp.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/memcpy.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/memcpy.S new file mode 100644 index 0000000000..675ec496b9 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/memcpy.S @@ -0,0 +1,4 @@ +#define ASI_PNF 0x82 +#define ASI_BLK_P 0xf0 +#define XCC icc +#include <sparc64/memcpy.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/memset.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/memset.S new file mode 100644 index 0000000000..ac67b7ab7c --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/memset.S @@ -0,0 +1,4 @@ +#define ASI_PNF 0x82 +#define ASI_BLK_P 0xf0 +#define XCC icc +#include <sparc64/memset.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/mul_1.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/mul_1.S new file mode 100644 index 0000000000..ae4fc17325 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/mul_1.S @@ -0,0 +1,70 @@ +! SPARC v9 32-bit __mpn_mul_1 -- Multiply a limb vector with a single +! limb and store the product in a second limb vector. +! +! Copyright (C) 2013-2017 Free Software Foundation, Inc. +! This file is part of the GNU C Library. +! Contributed by David S. Miller <davem@davemloft.net> +! +! The GNU C Library is free software; you can redistribute it and/or +! modify it under the terms of the GNU Lesser General Public +! License as published by the Free Software Foundation; either +! version 2.1 of the License, or (at your option) any later version. +! +! The GNU C Library is distributed in the hope that it will be useful, +! but WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! Lesser General Public License for more details. +! +! You should have received a copy of the GNU Lesser General Public +! License along with the GNU C Library; if not, see +! <http://www.gnu.org/licenses/>. + +#include <sysdep.h> + +#define res_ptr %o0 +#define s1_ptr %o1 +#define sz %o2 +#define s2_limb %o3 +#define carry %o5 +#define tmp1 %g1 +#define tmp2 %g2 +#define tmp3 %g3 +#define tmp4 %o4 + +ENTRY(__mpn_mul_1) + srl sz, 0, sz + srl s2_limb, 0, s2_limb + subcc sz, 1, sz + be,pn %icc, .Lfinal_limb + clr carry + +.Lloop: + lduw [s1_ptr + 0x00], tmp1 + lduw [s1_ptr + 0x04], tmp2 + mulx tmp1, s2_limb, tmp3 + add s1_ptr, 8, s1_ptr + mulx tmp2, s2_limb, tmp4 + sub sz, 2, sz + add res_ptr, 8, res_ptr + add carry, tmp3, tmp3 + stw tmp3, [res_ptr - 0x08] + srlx tmp3, 32, carry + add carry, tmp4, tmp4 + stw tmp4, [res_ptr - 0x04] + brgz sz, .Lloop + srlx tmp4, 32, carry + + brlz,pt sz, .Lfinish + nop + +.Lfinal_limb: + lduw [s1_ptr + 0x00], tmp1 + mulx tmp1, s2_limb, tmp3 + add carry, tmp3, tmp3 + stw tmp3, [res_ptr + 0x00] + srlx tmp3, 32, carry + +.Lfinish: + retl + mov carry, %o0 +END(__mpn_mul_1) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/Makefile b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/Makefile new file mode 100644 index 0000000000..4ad7aff914 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/Makefile @@ -0,0 +1,12 @@ +ifeq ($(subdir),crypt) +libcrypt-sysdep_routines += md5-crop sha256-crop sha512-crop +endif + +ifeq ($(subdir),locale) +localedef-aux += md5-crop +endif + +ifeq ($(subdir),string) +sysdep_routines += memcpy-ultra3 memcpy-niagara1 memcpy-niagara2 \ + memset-niagara1 memcpy-niagara4 memset-niagara4 +endif diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/ifunc-impl-list.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/ifunc-impl-list.c new file mode 100644 index 0000000000..a04aa0f674 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/ifunc-impl-list.c @@ -0,0 +1 @@ +#include <sparc64/multiarch/ifunc-impl-list.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/md5-block.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/md5-block.c new file mode 100644 index 0000000000..3765cabae7 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/md5-block.c @@ -0,0 +1 @@ +#include <sparc64/multiarch/md5-block.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/md5-crop.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/md5-crop.S new file mode 100644 index 0000000000..11a3a81482 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/md5-crop.S @@ -0,0 +1 @@ +#include <sparc64/multiarch/md5-crop.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-niagara1.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-niagara1.S new file mode 100644 index 0000000000..10aef85fe1 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-niagara1.S @@ -0,0 +1,2 @@ +#define XCC icc +#include <sparc64/multiarch/memcpy-niagara1.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-niagara2.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-niagara2.S new file mode 100644 index 0000000000..6b1bf6ea70 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-niagara2.S @@ -0,0 +1,2 @@ +#define XCC icc +#include <sparc64/multiarch/memcpy-niagara2.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-niagara4.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-niagara4.S new file mode 100644 index 0000000000..75ef9c017e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-niagara4.S @@ -0,0 +1 @@ +#include <sparc64/multiarch/memcpy-niagara4.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-ultra3.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-ultra3.S new file mode 100644 index 0000000000..77adf151aa --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-ultra3.S @@ -0,0 +1,2 @@ +#define XCC icc +#include <sparc64/multiarch/memcpy-ultra3.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy.S new file mode 100644 index 0000000000..14df91e005 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy.S @@ -0,0 +1,4 @@ +#define ASI_PNF 0x82 +#define ASI_BLK_P 0xf0 +#define XCC icc +#include <sparc64/multiarch/memcpy.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memset-niagara1.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memset-niagara1.S new file mode 100644 index 0000000000..b432420876 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memset-niagara1.S @@ -0,0 +1,2 @@ +#define XCC icc +#include <sparc64/multiarch/memset-niagara1.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memset-niagara4.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memset-niagara4.S new file mode 100644 index 0000000000..6545019c46 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memset-niagara4.S @@ -0,0 +1 @@ +#include <sparc64/multiarch/memset-niagara4.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memset.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memset.S new file mode 100644 index 0000000000..8f8264337d --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/memset.S @@ -0,0 +1,4 @@ +#define ASI_PNF 0x82 +#define ASI_BLK_P 0xf0 +#define XCC icc +#include <sparc64/multiarch/memset.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/rtld-memcpy.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/rtld-memcpy.c new file mode 100644 index 0000000000..304ad4ef18 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/rtld-memcpy.c @@ -0,0 +1 @@ +#include <sparc64/multiarch/rtld-memcpy.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/rtld-memset.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/rtld-memset.c new file mode 100644 index 0000000000..f24ae880a9 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/rtld-memset.c @@ -0,0 +1 @@ +#include <sparc64/multiarch/rtld-memset.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/sha256-block.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/sha256-block.c new file mode 100644 index 0000000000..600c602b61 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/sha256-block.c @@ -0,0 +1 @@ +#include <sparc64/multiarch/sha256-block.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/sha256-crop.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/sha256-crop.S new file mode 100644 index 0000000000..4895405853 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/sha256-crop.S @@ -0,0 +1 @@ +#include <sparc64/multiarch/sha256-crop.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/sha512-block.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/sha512-block.c new file mode 100644 index 0000000000..7c7c54e5a6 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/sha512-block.c @@ -0,0 +1 @@ +#include <sparc64/multiarch/sha512-block.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/sha512-crop.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/sha512-crop.S new file mode 100644 index 0000000000..cc74a99d3c --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/multiarch/sha512-crop.S @@ -0,0 +1 @@ +#include <sparc64/multiarch/sha512-crop.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/pthread_barrier_wait.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/pthread_barrier_wait.c new file mode 100644 index 0000000000..246c8d49de --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/pthread_barrier_wait.c @@ -0,0 +1 @@ +#include <nptl/pthread_barrier_wait.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/pthread_spin_init.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/pthread_spin_init.c new file mode 100644 index 0000000000..1eede86abd --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/pthread_spin_init.c @@ -0,0 +1 @@ +#include <sysdeps/sparc/sparc64/pthread_spin_init.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/pthread_spin_lock.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/pthread_spin_lock.S new file mode 100644 index 0000000000..ce53dfa396 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/pthread_spin_lock.S @@ -0,0 +1 @@ +#include <sysdeps/sparc/sparc64/pthread_spin_lock.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/pthread_spin_trylock.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/pthread_spin_trylock.S new file mode 100644 index 0000000000..ffd632da0a --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/pthread_spin_trylock.S @@ -0,0 +1 @@ +#include <sysdeps/sparc/sparc64/pthread_spin_trylock.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/pthread_spin_unlock.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/pthread_spin_unlock.S new file mode 100644 index 0000000000..983c80377a --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/pthread_spin_unlock.S @@ -0,0 +1 @@ +#include <sysdeps/sparc/sparc64/pthread_spin_unlock.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/rawmemchr.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/rawmemchr.S new file mode 100644 index 0000000000..05c269ecc8 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/rawmemchr.S @@ -0,0 +1,4 @@ +#define ASI_PNF 0x82 +#define ASI_BLK_P 0xf0 +#define XCC icc +#include <sparc64/rawmemchr.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/rem.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/rem.S new file mode 100644 index 0000000000..5385bd8305 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/rem.S @@ -0,0 +1,22 @@ +/* + * Sparc v9 has divide. + * As divx takes 68 cycles and sdivcc only 36, + * we use sdivcc eventhough it is deprecated. + */ + +#include <sysdep.h> + + .text + .align 32 +ENTRY(.rem) + + sra %o0, 31, %o2 + wr %o2, 0, %y + sdivcc %o0, %o1, %o2 + xnor %o2, %g0, %o3 + movvs %icc, %o3, %o2 + smul %o2, %o1, %o2 + retl + sub %o0, %o2, %o0 + +END(.rem) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/rtld-memcpy.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/rtld-memcpy.c new file mode 100644 index 0000000000..6f8386bc76 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/rtld-memcpy.c @@ -0,0 +1 @@ +#include <sparc64/rtld-memcpy.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/rtld-memset.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/rtld-memset.c new file mode 100644 index 0000000000..49b29f5733 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/rtld-memset.c @@ -0,0 +1 @@ +#include <sparc64/rtld-memset.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/sdiv.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/sdiv.S new file mode 100644 index 0000000000..d765514cea --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/sdiv.S @@ -0,0 +1,20 @@ +/* + * Sparc v9 has divide. + * As divx takes 68 cycles and sdivcc only 36, + * we use sdivcc eventhough it is deprecated. + */ + +#include <sysdep.h> + + .text + .align 32 +ENTRY(.div) + + sra %o0, 31, %o2 + wr %o2, 0, %y + sdivcc %o0, %o1, %o0 + xnor %o0, %g0, %o2 + retl + movvs %icc, %o2, %o0 + +END(.div) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/sem_post.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/sem_post.c new file mode 100644 index 0000000000..6a2813caee --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/sem_post.c @@ -0,0 +1 @@ +#include <nptl/sem_post.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/sem_waitcommon.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/sem_waitcommon.c new file mode 100644 index 0000000000..d4a139572b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/sem_waitcommon.c @@ -0,0 +1 @@ +#include <nptl/sem_waitcommon.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/stpcpy.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/stpcpy.S new file mode 100644 index 0000000000..440ad7e215 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/stpcpy.S @@ -0,0 +1,4 @@ +#define ASI_PNF 0x82 +#define ASI_BLK_P 0xf0 +#define XCC icc +#include <sparc64/stpcpy.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/stpncpy.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/stpncpy.S new file mode 100644 index 0000000000..124136a0b2 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/stpncpy.S @@ -0,0 +1,4 @@ +#define ASI_PNF 0x82 +#define ASI_BLK_P 0xf0 +#define XCC icc +#include <sparc64/stpncpy.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strcat.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strcat.S new file mode 100644 index 0000000000..7a22235703 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strcat.S @@ -0,0 +1,4 @@ +#define ASI_PNF 0x82 +#define ASI_BLK_P 0xf0 +#define XCC icc +#include <sparc64/strcat.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strchr.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strchr.S new file mode 100644 index 0000000000..ddd32120d4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strchr.S @@ -0,0 +1,4 @@ +#define ASI_PNF 0x82 +#define ASI_BLK_P 0xf0 +#define XCC icc +#include <sparc64/strchr.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strcmp.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strcmp.S new file mode 100644 index 0000000000..5330f4359b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strcmp.S @@ -0,0 +1,4 @@ +#define ASI_PNF 0x82 +#define ASI_BLK_P 0xf0 +#define XCC icc +#include <sparc64/strcmp.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strcpy.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strcpy.S new file mode 100644 index 0000000000..0b35c9be08 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strcpy.S @@ -0,0 +1,4 @@ +#define ASI_PNF 0x82 +#define ASI_BLK_P 0xf0 +#define XCC icc +#include <sparc64/strcpy.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strcspn.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strcspn.S new file mode 100644 index 0000000000..f9d6beabe4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strcspn.S @@ -0,0 +1,4 @@ +#define ASI_PNF 0x82 +#define ASI_BLK_P 0xf0 +#define XCC icc +#include <sparc64/strcspn.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strlen.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strlen.S new file mode 100644 index 0000000000..28a216c076 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strlen.S @@ -0,0 +1 @@ +#include <sparc64/strlen.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strncmp.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strncmp.S new file mode 100644 index 0000000000..addd89e05b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strncmp.S @@ -0,0 +1,4 @@ +#define ASI_PNF 0x82 +#define ASI_BLK_P 0xf0 +#define XCC icc +#include <sparc64/strncmp.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strncpy.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strncpy.S new file mode 100644 index 0000000000..688f9dfd65 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strncpy.S @@ -0,0 +1,4 @@ +#define ASI_PNF 0x82 +#define ASI_BLK_P 0xf0 +#define XCC icc +#include <sparc64/strncpy.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strpbrk.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strpbrk.S new file mode 100644 index 0000000000..62294c0af4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strpbrk.S @@ -0,0 +1,4 @@ +#define ASI_PNF 0x82 +#define ASI_BLK_P 0xf0 +#define XCC icc +#include <sparc64/strpbrk.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strrchr.c b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strrchr.c new file mode 100644 index 0000000000..ec608d6ab3 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strrchr.c @@ -0,0 +1 @@ +/* strrchr is in strchr.S */ diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strspn.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strspn.S new file mode 100644 index 0000000000..291e798085 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/strspn.S @@ -0,0 +1,4 @@ +#define ASI_PNF 0x82 +#define ASI_BLK_P 0xf0 +#define XCC icc +#include <sparc64/strspn.S> diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/submul_1.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/submul_1.S new file mode 100644 index 0000000000..52b7d35aa4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/submul_1.S @@ -0,0 +1,82 @@ +! SPARC v9 32-bit __mpn_submul_1 -- Multiply a limb vector with a limb +! and subtract the result from a second limb vector. +! +! Copyright (C) 2013-2017 Free Software Foundation, Inc. +! This file is part of the GNU C Library. +! Contributed by David S. Miller <davem@davemloft.net> +! +! The GNU C Library is free software; you can redistribute it and/or +! modify it under the terms of the GNU Lesser General Public +! License as published by the Free Software Foundation; either +! version 2.1 of the License, or (at your option) any later version. +! +! The GNU C Library is distributed in the hope that it will be useful, +! but WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! Lesser General Public License for more details. +! +! You should have received a copy of the GNU Lesser General Public +! License along with the GNU C Library; if not, see +! <http://www.gnu.org/licenses/>. + +#include <sysdep.h> + +#define res_ptr %i0 +#define s1_ptr %i1 +#define sz_arg %i2 +#define s2l_arg %i3 +#define sz %o4 +#define carry %o5 +#define s2_limb %g1 +#define tmp1 %l0 +#define tmp2 %l1 +#define tmp3 %l2 +#define tmp4 %l3 +#define tmp64_1 %g3 +#define tmp64_2 %o3 + +ENTRY(__mpn_submul_1) + save %sp, -96, %sp + srl sz_arg, 0, sz + srl s2l_arg, 0, s2_limb + subcc sz, 1, sz + be,pn %icc, .Lfinal_limb + subcc %g0, 0, carry + +.Lloop: + lduw [s1_ptr + 0x00], tmp1 + lduw [res_ptr + 0x00], tmp3 + lduw [s1_ptr + 0x04], tmp2 + lduw [res_ptr + 0x04], tmp4 + mulx tmp1, s2_limb, tmp64_1 + add s1_ptr, 8, s1_ptr + mulx tmp2, s2_limb, tmp64_2 + sub sz, 2, sz + add res_ptr, 8, res_ptr + addx carry, tmp64_1, tmp64_1 + srlx tmp64_1, 32, carry + subcc tmp3, tmp64_1, tmp64_1 + stw tmp64_1, [res_ptr - 0x08] + addx carry, tmp64_2, tmp64_2 + srlx tmp64_2, 32, carry + subcc tmp4, tmp64_2, tmp64_2 + brgz sz, .Lloop + stw tmp64_2, [res_ptr - 0x04] + + brlz,pt sz, .Lfinish + nop + +.Lfinal_limb: + lduw [s1_ptr + 0x00], tmp1 + lduw [res_ptr + 0x00], tmp3 + mulx tmp1, s2_limb, tmp64_1 + addx carry, tmp64_1, tmp64_1 + srlx tmp64_1, 32, carry + subcc tmp3, tmp64_1, tmp64_1 + stw tmp64_1, [res_ptr + 0x00] + +.Lfinish: + addx carry, 0, carry + jmpl %i7 + 0x8, %g0 + restore carry, 0, %o0 +END(__mpn_submul_1) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/udiv.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/udiv.S new file mode 100644 index 0000000000..368f85ede2 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/udiv.S @@ -0,0 +1,18 @@ +/* + * Sparc v9 has divide. + * As divx takes 68 cycles and udiv only 37, + * we use udiv eventhough it is deprecated. + */ + +#include <sysdep.h> + + .text + .align 32 +ENTRY(.udiv) + + wr %g0, 0, %y + retl + udiv %o0, %o1, %o0 + +END(.udiv) +strong_alias (.udiv, __wrap_.udiv) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/umul.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/umul.S new file mode 100644 index 0000000000..608b72aca1 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/umul.S @@ -0,0 +1,17 @@ +/* + * Sparc v9 has multiply. + */ + +#include <sysdep.h> + + .text + .align 32 +ENTRY(.umul) + + srl %o0, 0, %o0 + srl %o1, 0, %o1 + mulx %o0, %o1, %o0 + retl + srlx %o0, 32, %o1 + +END(.umul) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/urem.S b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/urem.S new file mode 100644 index 0000000000..cab16c9193 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sparcv9/urem.S @@ -0,0 +1,19 @@ +/* + * Sparc v9 has divide. + * As divx takes 68 cycles and udiv only 37, + * we use udiv eventhough it is deprecated. + */ + +#include <sysdep.h> + + .text + .align 32 +ENTRY(.urem) + + wr %g0, 0, %y + udiv %o0, %o1, %o2 + umul %o2, %o1, %o2 + retl + sub %o0, %o2, %o0 + +END(.urem) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/stackguard-macros.h b/REORG.TODO/sysdeps/sparc/sparc32/stackguard-macros.h new file mode 100644 index 0000000000..1eef0f19f0 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/stackguard-macros.h @@ -0,0 +1,7 @@ +#include <stdint.h> + +#define STACK_CHK_GUARD \ + ({ uintptr_t x; asm ("ld [%%g7+0x14], %0" : "=r" (x)); x; }) + +#define POINTER_CHK_GUARD \ + ({ uintptr_t x; asm ("ld [%%g7+0x18], %0" : "=r" (x)); x; }) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/start.S b/REORG.TODO/sysdeps/sparc/sparc32/start.S new file mode 100644 index 0000000000..a06568d0e9 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/start.S @@ -0,0 +1,99 @@ +/* Startup code for elf32-sparc + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson <richard@gnu.ai.mit.edu>, 1997. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + In addition to the permissions in the GNU Lesser General Public + License, the Free Software Foundation gives you unlimited + permission to link the compiled version of this file with other + programs, and to distribute those programs without any restriction + coming from the use of this file. (The GNU Lesser General Public + License restrictions do apply in other respects; for example, they + cover modification of the file, and distribution when not linked + into another program.) + + Note that people who make modified versions of this file are not + obligated to grant this special exception for their modified + versions; it is their choice whether to do so. The GNU Lesser + General Public License gives permission to release a modified + version without this exception; this exception also makes it + possible to release a modified version which carries forward this + exception. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + + .section ".text" + .align 4 + .global _start + .type _start,#function +_start: +#ifdef SHARED + SETUP_PIC_REG(l7) +#endif + + /* Terminate the stack frame, and reserve space for functions to + drop their arguments. */ + mov %g0, %fp + sub %sp, 6*4, %sp + + /* Extract the arguments and environment as encoded on the stack. The + argument info starts after one register window (16 words) past the SP. */ + ld [%sp+22*4], %o1 + add %sp, 23*4, %o2 + + /* Load the addresses of the user entry points. */ +#ifndef SHARED + sethi %hi(main), %o0 + sethi %hi(__libc_csu_init), %o3 + sethi %hi(__libc_csu_fini), %o4 + or %o0, %lo(main), %o0 + or %o3, %lo(__libc_csu_init), %o3 + or %o4, %lo(__libc_csu_fini), %o4 +#else + sethi %gdop_hix22(main), %o0 + sethi %gdop_hix22(__libc_csu_init), %o3 + sethi %gdop_hix22(__libc_csu_fini), %o4 + xor %o0, %gdop_lox10(main), %o0 + xor %o3, %gdop_lox10(__libc_csu_init), %o3 + xor %o4, %gdop_lox10(__libc_csu_fini), %o4 + ld [%l7 + %o0], %o0, %gdop(main) + ld [%l7 + %o3], %o3, %gdop(__libc_csu_init) + ld [%l7 + %o4], %o4, %gdop(__libc_csu_fini) +#endif + + /* When starting a binary via the dynamic linker, %g1 contains the + address of the shared library termination function, which will be + registered with atexit(). If we are statically linked, this will + be NULL. */ + mov %g1, %o5 + + /* Let libc do the rest of the initialization, and call main. */ + call __libc_start_main + nop + + /* Die very horribly if exit returns. */ + unimp + + .size _start, .-_start + +/* Define a symbol for the first piece of initialized data. */ + .data + .globl __data_start +__data_start: + .long 0 +weak_alias (__data_start, data_start) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/stpcpy.S b/REORG.TODO/sysdeps/sparc/sparc32/stpcpy.S new file mode 100644 index 0000000000..2cbd69c3b4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/stpcpy.S @@ -0,0 +1,166 @@ +/* Copy SRC to DEST returning the address of the terminating '\0' in DEST. + For SPARC v7. + Copyright (C) 1996-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jj@ultra.linux.cz>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* Normally, this uses ((xword - 0x01010101) & 0x80808080) test + to find out if any byte in xword could be zero. This is fast, but + also gives false alarm for any byte in range 0x81-0xff. It does + not matter for correctness, as if this test tells us there could + be some zero byte, we check it byte by byte, but if bytes with + high bits set are common in the strings, then this will give poor + performance. You can #define EIGHTBIT_NOT_RARE and the algorithm + will use one tick slower, but more precise test + ((xword - 0x01010101) & (~xword) & 0x80808080), + which does not give any false alarms (but if some bits are set, + one cannot assume from it which bytes are zero and which are not). + It is yet to be measured, what is the correct default for glibc + in these days for an average user. + */ + + .text + .align 4 + +ENTRY(__stpcpy) + andcc %o1, 3, %g0 + be 20f + sethi %hi(0x80808080), %o4 + + ldub [%o1], %o5 + stb %o5, [%o0] + cmp %o5, 0 + add %o0, 1, %o0 + be 1f + add %o1, 1, %o1 + andcc %o1, 3, %g0 + be 4f + or %o4, %lo(0x80808080), %o3 + ldub [%o1], %o5 + stb %o5, [%o0] + cmp %o5, 0 + add %o0, 1, %o0 + be 1f + add %o1, 1, %o1 + andcc %o1, 3, %g0 + be 5f + sethi %hi(0x01010101), %o4 + ldub [%o1], %o5 + stb %o5, [%o0] + cmp %o5, 0 + add %o0, 1, %o0 + be 1f + add %o1, 1, %o1 + b 6f + or %o4, %lo(0x01010101), %o2 +1: retl + add %o0, -1, %o0 + +20: or %o4, %lo(0x80808080), %o3 +4: sethi %hi(0x01010101), %o4 +5: or %o4, %lo(0x01010101), %o2 +6: andcc %o0, 3, %g0 + bne 16f + sub %g0, 4, %g1 + +11: add %g1, 4, %g1 + ld [%o1 + %g1], %o5 + sub %o5, %o2, %o4 +#ifdef EIGHTBIT_NOT_RARE + andn %o4, %o5, %o4 +#endif + andcc %o4, %o3, %g0 + be,a 11b + st %o5, [%o0 + %g1] + + /* Check every byte. */ + srl %o5, 24, %g5 + andcc %g5, 0xff, %g0 + be 14f + srl %o5, 16, %g5 + andcc %g5, 0xff, %g0 + be 13f + srl %o5, 8, %g5 + andcc %g5, 0xff, %g0 + be 12f + andcc %o5, 0xff, %g0 + bne 11b + st %o5, [%o0 + %g1] + add %o0, %g1, %o0 + retl + add %o0, 3, %o0 +12: srl %o5, 16, %o5 + sth %o5, [%o0 + %g1] + add %g1, 2, %g1 + stb %g0, [%o0 + %g1] + retl + add %o0, %g1, %o0 +13: srl %o5, 16, %o5 + sth %o5, [%o0 + %g1] + add %g1, 1, %g1 + retl + add %o0, %g1, %o0 +14: stb %g0, [%o0 + %g1] + retl + add %o0, %g1, %o0 + +15: srl %o5, 24, %o4 + srl %o5, 16, %g1 + stb %o4, [%o0] + srl %o5, 8, %g4 + stb %g1, [%o0 + 1] + stb %g4, [%o0 + 2] + stb %o5, [%o0 + 3] + add %o0, 4, %o0 +16: ld [%o1], %o5 + sub %o5, %o2, %o4 + andcc %o4, %o3, %g0 + be 15b + add %o1, 4, %o1 + + /* Check every byte. */ + srl %o5, 24, %g5 + andcc %g5, 0xff, %g4 + be 19f + stb %g4, [%o0] + srl %o5, 16, %g5 + andcc %g5, 0xff, %g4 + be 18f + stb %g4, [%o0 + 1] + srl %o5, 8, %g5 + andcc %g5, 0xff, %g4 + be 17f + stb %g4, [%o0 + 2] + andcc %o5, 0xff, %g4 + stb %g4, [%o0 + 3] + bne 16b + add %o0, 4, %o0 + retl + sub %o0, 1, %o0 +17: retl + add %o0, 2, %o0 +18: retl + add %o0, 1, %o0 +19: retl + nop +END(__stpcpy) + +weak_alias (__stpcpy, stpcpy) +libc_hidden_def (__stpcpy) +libc_hidden_builtin_def (stpcpy) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/strcat.S b/REORG.TODO/sysdeps/sparc/sparc32/strcat.S new file mode 100644 index 0000000000..cfa2bbd5b7 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/strcat.S @@ -0,0 +1,352 @@ +/* strcat (dest, src) -- Append SRC on the end of DEST. + For SPARC v7. + Copyright (C) 1996-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jj@ultra.linux.cz>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* Normally, this uses ((xword - 0x01010101) & 0x80808080) test + to find out if any byte in xword could be zero. This is fast, but + also gives false alarm for any byte in range 0x81-0xff. It does + not matter for correctness, as if this test tells us there could + be some zero byte, we check it byte by byte, but if bytes with + high bits set are common in the strings, then this will give poor + performance. You can #define EIGHTBIT_NOT_RARE and the algorithm + will use one tick slower, but more precise test + ((xword - 0x01010101) & (~xword) & 0x80808080), + which does not give any false alarms (but if some bits are set, + one cannot assume from it which bytes are zero and which are not). + It is yet to be measured, what is the correct default for glibc + in these days for an average user. + */ + + .text + .align 4 + +ENTRY(strcat) + mov %o0, %g2 + andcc %o0, 3, %g0 + be 30f + sethi %hi(0x80808080), %o4 + + ldub [%o0], %o5 + cmp %o5, 0 + be 1f + add %o0, 1, %o0 + andcc %o0, 3, %g0 + be 7f + or %o4, %lo(0x80808080), %o3 + ldub [%o0], %o5 + cmp %o5, 0 + be 2f + add %o0, 1, %o0 + andcc %o0, 3, %g0 + be 8f + sethi %hi(0x01010101), %o4 + ldub [%o0], %o5 + cmp %o5, 0 + be 3f + add %o0, 1, %o0 + b 9f + or %o4, %lo(0x01010101), %o2 +1: or %o4, %lo(0x80808080), %o3 +2: sethi %hi(0x01010101), %o4 +3: or %o4, %lo(0x01010101), %o2 + b 3f + sub %o0, 1, %o0 + +30: or %o4, %lo(0x80808080), %o3 +7: sethi %hi(0x01010101), %o4 +8: or %o4, %lo(0x01010101), %o2 +9: ld [%o0], %o5 +7: sub %o5, %o2, %o4 +#ifdef EIGHTBIT_NOT_RARE + andn %o4, %o5, %o4 +#endif + andcc %o4, %o3, %g0 + be 9b + add %o0, 4, %o0 + + srl %o5, 24, %g5 + andcc %g5, 0xff, %g0 + be 3f + add %o0, -4, %o0 + srl %o5, 16, %g5 + andcc %g5, 0xff, %g0 + be 3f + add %o0, 1, %o0 + srl %o5, 8, %g5 + andcc %g5, 0xff, %g0 + be 3f + add %o0, 1, %o0 + andcc %o5, 0xff, %g0 + add %o0, 2, %o0 + bne,a 7b + ld [%o0], %o5 + sub %o0, 1, %o0 +3: andcc %o1, 3, %o4 + be 4f + nop + + cmp %o4, 2 + be 11f + cmp %o4, 3 + ldub [%o1], %o5 + add %o1, 1, %o1 + stb %o5, [%o0] + be 13f + cmp %o5, 0 + be 0f + add %o0, 1, %o0 +11: lduh [%o1], %o5 + add %o1, 2, %o1 + srl %o5, 8, %o4 + cmp %o4, 0 + stb %o4, [%o0] + bne,a 12f + stb %o5, [%o0 + 1] + retl + mov %g2, %o0 +12: andcc %o5, 0xff, %o5 + bne 4f + add %o0, 2, %o0 + retl + mov %g2, %o0 +13: bne 4f + add %o0, 1, %o0 + retl + mov %g2, %o0 + +4: andcc %o0, 3, %g3 + bne 12f +1: ld [%o1], %o5 + add %o1, 4, %o1 + sub %o5, %o2, %o4 +#ifdef EIGHTBIT_NOT_RARE + andn %o4, %o5, %o4 +#endif + add %o0, 4, %o0 + andcc %o4, %o3, %g0 + be,a 1b + st %o5, [%o0 - 4] + + srl %o5, 24, %g5 + andcc %g5, 0xff, %g0 + be 1f + srl %o5, 16, %g5 + andcc %g5, 0xff, %g0 + be 2f + srl %o5, 8, %g5 + andcc %g5, 0xff, %g0 + be 3f + andcc %o5, 0xff, %g0 + bne 1b + st %o5, [%o0 - 4] + retl + mov %g2, %o0 +3: srl %o5, 16, %o5 + sth %o5, [%o0 - 4] + stb %g0, [%o0 - 2] + retl + mov %g2, %o0 +2: srl %o5, 16, %o5 + sth %o5, [%o0 - 4] + retl + mov %g2, %o0 +1: stb %g0, [%o0 - 4] + retl + mov %g2, %o0 + +12: add %o1, 4, %o1 + sub %o5, %o2, %o4 + cmp %g3, 2 + be 2f + cmp %g3, 3 + be 3f + andcc %o4, %o3, %g0 + bne 5f + srl %o5, 24, %g5 + stb %g5, [%o0] + sub %o0, 1, %o0 + srl %o5, 8, %g5 + sth %g5, [%o0 + 2] +1: add %o0, 4, %o0 +4: sll %o5, 24, %g6 + ld [%o1], %o5 + add %o1, 4, %o1 + srl %o5, 8, %g5 + sub %o5, %o2, %o4 +#ifdef EIGHTBIT_NOT_RARE + andn %o4, %o5, %o4 +#endif + or %g5, %g6, %g5 + andcc %o4, %o3, %g0 + be,a 1b + st %g5, [%o0] + srl %o5, 24, %o4 + andcc %o4, 0xff, %g0 + be 6f + srl %o5, 16, %o4 + andcc %o4, 0xff, %g0 + be 7f + srl %o5, 8, %o4 + st %g5, [%o0] + andcc %o4, 0xff, %g0 + be 0f + andcc %o5, 0xff, %g0 +1: bne 4b + add %o0, 4, %o0 +9: stb %g0, [%o0] +0: retl + mov %g2, %o0 + +6: srl %g5, 16, %g5 + sth %g5, [%o0] + retl + mov %g2, %o0 + +7: srl %g5, 16, %g5 + sth %g5, [%o0] + stb %g0, [%o0 + 2] + retl + mov %g2, %o0 + +5: andcc %g5, 0xff, %g4 + be 9b + srl %o5, 16, %g5 + andcc %g5, 0xff, %g0 + be 7f + srl %o5, 8, %g5 + andcc %g5, 0xff, %g0 + stb %g4, [%o0] + sth %g5, [%o0 + 1] + sub %o0, 1, %o0 + bne 1b + andcc %o5, 0xff, %g0 + retl + mov %g2, %o0 + +7: stb %g4, [%o0] + stb %g0, [%o0 + 1] + retl + mov %g2, %o0 + +2: andcc %o4, %o3, %g0 + bne 5f + srl %o5, 16, %g5 + sth %g5, [%o0] + sub %o0, 2, %o0 +1: add %o0, 4, %o0 +4: sll %o5, 16, %g6 + ld [%o1], %o5 + add %o1, 4, %o1 + srl %o5, 16, %g5 + sub %o5, %o2, %o4 +#ifdef EIGHTBIT_NOT_RARE + andn %o4, %o5, %o4 +#endif + or %g5, %g6, %g5 + andcc %o4, %o3, %g0 + be,a 1b + st %g5, [%o0] + srl %o5, 24, %o4 + andcc %o4, 0xff, %g0 + be 7f + srl %o5, 16, %o4 + st %g5, [%o0] + andcc %o4, 0xff, %g0 + be 0b + srl %o5, 8, %o4 +1: andcc %o4, 0xff, %g0 + be 8f + andcc %o5, 0xff, %g0 + bne 4b + add %o0, 4, %o0 + sth %o5, [%o0] + retl + mov %g2, %o0 + +7: srl %g5, 16, %g5 + sth %g5, [%o0] + stb %g0, [%o0 + 2] + retl + mov %g2, %o0 + +8: stb %g0, [%o0 + 4] + retl + mov %g2, %o0 + +5: srl %o5, 24, %g5 + andcc %g5, 0xff, %g0 + be 9b + srl %o5, 16, %g5 + andcc %g5, 0xff, %g0 + sth %g5, [%o0] + sub %o0, 2, %o0 + bne 1b + srl %o5, 8, %o4 + retl + mov %g2, %o0 + +3: bne 5f + srl %o5, 24, %g5 + stb %g5, [%o0] + sub %o0, 3, %o0 +1: add %o0, 4, %o0 +4: sll %o5, 8, %g6 + ld [%o1], %o5 + add %o1, 4, %o1 + srl %o5, 24, %g5 + sub %o5, %o2, %o4 +#ifdef EIGHTBIT_NOT_RARE + andn %o4, %o5, %o4 +#endif + or %g5, %g6, %g5 + andcc %o4, %o3, %g0 + be 1b + st %g5, [%o0] + srl %o5, 24, %o4 + andcc %o4, 0xff, %g0 + be 0b + srl %o5, 16, %o4 +1: andcc %o4, 0xff, %g0 + be 8b + srl %o5, 8, %o4 + andcc %o4, 0xff, %g0 + be 9f + andcc %o5, 0xff, %g0 + bne 4b + add %o0, 4, %o0 + srl %o5, 8, %o5 + sth %o5, [%o0] + stb %g0, [%o0 + 2] + retl + mov %g2, %o0 +9: srl %o5, 8, %o5 + sth %o5, [%o0 + 4] + retl + mov %g2, %o0 +5: andcc %g5, 0xff, %g0 + stb %g5, [%o0] + sub %o0, 3, %o0 + bne 1b + srl %o5, 16, %o4 + retl + mov %g2, %o0 +END(strcat) +libc_hidden_builtin_def (strcat) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/strchr.S b/REORG.TODO/sysdeps/sparc/sparc32/strchr.S new file mode 100644 index 0000000000..f934473ea8 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/strchr.S @@ -0,0 +1,284 @@ +/* strchr (str, ch) -- Return pointer to first occurrence of CH in STR. + For SPARC v7. + Copyright (C) 1996-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jj@ultra.linux.cz> and + David S. Miller <davem@caip.rutgers.edu>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* Normally, this uses ((xword - 0x01010101) & 0x80808080) test + to find out if any byte in xword could be zero. This is fast, but + also gives false alarm for any byte in range 0x81-0xff. It does + not matter for correctness, as if this test tells us there could + be some zero byte, we check it byte by byte, but if bytes with + high bits set are common in the strings, then this will give poor + performance. You can #define EIGHTBIT_NOT_RARE and the algorithm + will use one tick slower, but more precise test + ((xword - 0x01010101) & (~xword) & 0x80808080), + which does not give any false alarms (but if some bits are set, + one cannot assume from it which bytes are zero and which are not). + It is yet to be measured, what is the correct default for glibc + in these days for an average user. + */ + + .text + .align 4 +ENTRY(strchr) + andcc %o1, 0xff, %o1 + be 12f + sll %o1, 8, %o2 + andcc %o0, 3, %g0 + or %o1, %o2, %o2 + sethi %hi(0x80808080), %o4 + sll %o2, 16, %o3 + be 13f + or %o3, %o2, %g2 + + ldub [%o0], %g4 + cmp %g4, %o1 + be 11f + add %o0, 1, %o0 + cmp %g4, 0 + be 9f + andcc %o0, 3, %g0 + be 4f + or %o4, %lo(0x80808080), %o3 + ldub [%o0], %g4 + cmp %g4, %o1 + be 11f + add %o0, 1, %o0 + cmp %g4, 0 + be 9f + andcc %o0, 3, %g0 + be 5f + sethi %hi(0x01010101), %o5 + ldub [%o0], %g4 + cmp %g4, %o1 + be 11f + add %o0, 1, %o0 + cmp %g4, 0 + be 9f + or %o5, %lo(0x01010101), %o2 + b 6f + ld [%o0], %g4 +11: retl + sub %o0, 1, %o0 + +13: or %o4, %lo(0x80808080), %o3 +4: sethi %hi(0x01010101), %o5 +5: or %o5, %lo(0x01010101), %o2 +7: ld [%o0], %g4 +6: xor %g4, %g2, %g5 + sub %g4, %o2, %o4 +#ifdef EIGHTBIT_NOT_RARE + sub %g5, %o2, %g6 + andn %o4, %g4, %o4 + andn %g6, %g5, %g5 +#else + sub %g5, %o2, %g5 +#endif + or %g5, %o4, %o4 + andcc %o4, %o3, %g0 + be 7b + add %o0, 4, %o0 + + /* Check every byte. */ +8: srl %g4, 24, %g5 +7: andcc %g5, 0xff, %g5 + be 9f + cmp %g5, %o1 + be 4f + srl %g4, 16, %g5 + andcc %g5, 0xff, %g5 + be 9f + cmp %g5, %o1 + be 3f + srl %g4, 8, %g5 + andcc %g5, 0xff, %g5 + be 9f + cmp %g5, %o1 + be 2f + andcc %g4, 0xff, %g5 + be 9f + cmp %g5, %o1 + bne,a 6b + ld [%o0], %g4 + retl + sub %o0, 1, %o0 +2: retl + sub %o0, 2, %o0 +3: retl + sub %o0, 3, %o0 +4: retl + sub %o0, 4, %o0 +9: retl + clr %o0 + +11: ldub [%o0], %o5 + cmp %o5, 0 + be 1f + add %o0, 1, %o0 + andcc %o0, 3, %g0 + be 4f + or %o4, %lo(0x80808080), %o3 + ldub [%o0], %o5 + cmp %o5, 0 + be 1f + add %o0, 1, %o0 + andcc %o0, 3, %g0 + be 5f + sethi %hi(0x01010101), %o4 + ldub [%o0], %o5 + cmp %o5, 0 + be 1f + add %o0, 1, %o0 + b 6f + or %o4, %lo(0x01010101), %o2 +1: retl + sub %o0, 1, %o0 + +12: andcc %o0, 3, %g0 + bne 11b + sethi %hi(0x80808080), %o4 + or %o4, %lo(0x80808080), %o3 +4: sethi %hi(0x01010101), %o4 +5: or %o4, %lo(0x01010101), %o2 +6: ld [%o0], %o5 +7: sub %o5, %o2, %o4 +#ifdef EIGHTBIT_NOT_RARE + andn %o4, %o5, %o4 +#endif + andcc %o4, %o3, %g0 + be 6b + add %o0, 4, %o0 + + /* Check every byte. */ + srl %o5, 24, %g5 + andcc %g5, 0xff, %g0 + be 8f + add %o0, -4, %o4 + srl %o5, 16, %g5 + andcc %g5, 0xff, %g0 + be 8f + add %o4, 1, %o4 + srl %o5, 8, %g5 + andcc %g5, 0xff, %g0 + be 8f + add %o4, 1, %o4 + andcc %o5, 0xff, %g0 + bne,a 7b + ld [%o0], %o5 + add %o4, 1, %o4 +8: retl + mov %o4, %o0 + +13: ldub [%o0], %g4 + cmp %g4, %o1 + add %o0, 1, %o0 + be,a 1f + sub %o0, 1, %o5 + cmp %g4, 0 + be 9f +1: andcc %o0, 3, %g0 + be 4f + or %o4, %lo(0x80808080), %o3 + ldub [%o0], %g4 + cmp %g4, %o1 + add %o0, 1, %o0 + be,a 1f + sub %o0, 1, %o5 + cmp %g4, 0 + be 9f +1: andcc %o0, 3, %g0 + be 5f + sethi %hi(0x01010101), %o4 + ldub [%o0], %g4 + cmp %g4, %o1 + add %o0, 1, %o0 + be,a 1f + sub %o0, 1, %o5 + cmp %g4, 0 + be 9f +1: or %o4, %lo(0x01010101), %o2 + b 7f + ld [%o0], %g4 +END(strchr) + +ENTRY(strrchr) + andcc %o1, 0xff, %o1 + clr %o5 + be 12b + sll %o1, 8, %o2 + andcc %o0, 3, %g0 + or %o1, %o2, %o2 + sethi %hi(0x80808080), %o4 + sll %o2, 16, %o3 + bne 13b + or %o3, %o2, %g2 + or %o4, %lo(0x80808080), %o3 +4: sethi %hi(0x01010101), %o4 +5: or %o4, %lo(0x01010101), %o2 +6: ld [%o0], %g4 +7: xor %g4, %g2, %g5 + sub %g4, %o2, %o4 +#ifdef EIGHTBIT_NOT_RARE + sub %g5, %o2, %g6 + andn %o4, %g4, %o4 + andn %g6, %g5, %g5 +#else + sub %g5, %o2, %g5 +#endif + or %g5, %o4, %o4 + andcc %o4, %o3, %g0 + be 6b + add %o0, 4, %o0 + + /* Check every byte. */ +3: srl %g4, 24, %g5 +8: andcc %g5, 0xff, %g5 + be 9f + cmp %g5, %o1 + be,a 1f + sub %o0, 4, %o5 +1: srl %g4, 16, %g5 + andcc %g5, 0xff, %g5 + be 9f + cmp %g5, %o1 + be,a 1f + sub %o0, 3, %o5 +1: srl %g4, 8, %g5 + andcc %g5, 0xff, %g5 + be 9f + cmp %g5, %o1 + be,a 1f + sub %o0, 2, %o5 +1: andcc %g4, 0xff, %g5 + be 9f + cmp %g5, %o1 + be,a 1f + sub %o0, 1, %o5 +1: b 7b + ld [%o0], %g4 +9: retl + mov %o5, %o0 +END(strrchr) + +weak_alias (strchr, index) +weak_alias (strrchr, rindex) +libc_hidden_builtin_def (strchr) +libc_hidden_builtin_def (strrchr) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/strcmp.S b/REORG.TODO/sysdeps/sparc/sparc32/strcmp.S new file mode 100644 index 0000000000..18e3700dd2 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/strcmp.S @@ -0,0 +1,259 @@ +/* Compare two strings for differences. + For SPARC v7. + Copyright (C) 1996-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jj@ultra.linux.cz>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* Normally, this uses ((xword - 0x01010101) & 0x80808080) test + to find out if any byte in xword could be zero. This is fast, but + also gives false alarm for any byte in range 0x81-0xff. It does + not matter for correctness, as if this test tells us there could + be some zero byte, we check it byte by byte, but if bytes with + high bits set are common in the strings, then this will give poor + performance. You can #define EIGHTBIT_NOT_RARE and the algorithm + will use one tick slower, but more precise test + ((xword - 0x01010101) & (~xword) & 0x80808080), + which does not give any false alarms (but if some bits are set, + one cannot assume from it which bytes are zero and which are not). + It is yet to be measured, what is the correct default for glibc + in these days for an average user. + */ + + .text + .align 4 + +ENTRY(strcmp) + andcc %o0, 3, %g0 + be 13f + sethi %hi(0x80808080), %g1 + + ldub [%o0], %o4 + add %o0, 1, %o0 + ldub [%o1], %o5 + cmp %o4, 0 + add %o1, 1, %o1 + be 2f + subcc %o4, %o5, %o4 + bne 2f + andcc %o0, 3, %g0 + be 4f + or %g1, %lo(0x80808080), %o3 + ldub [%o0], %o4 + add %o0, 1, %o0 + ldub [%o1], %o5 + cmp %o4, 0 + add %o1, 1, %o1 + be 2f + subcc %o4, %o5, %o4 + bne 2f + andcc %o0, 3, %g0 + be 5f + sethi %hi(0x01010101), %g1 + ldub [%o0], %o4 + add %o0, 1, %o0 + ldub [%o1], %o5 + cmp %o4, 0 + add %o1, 1, %o1 + be 2f + subcc %o4, %o5, %o4 + bne 2f + andcc %o1, 3, %g2 + bne 12f + or %g1, %lo(0x01010101), %o2 + b 1f + ld [%o0], %o4 +2: retl + mov %o4, %o0 + +13: or %g1, %lo(0x80808080), %o3 +4: sethi %hi(0x01010101), %g1 +5: andcc %o1, 3, %g2 + bne 12f + or %g1, %lo(0x01010101), %o2 + +0: ld [%o0], %o4 +1: ld [%o1], %o5 + sub %o4, %o2, %g1 + add %o0, 4, %o0 + cmp %o4, %o5 +#ifdef EIGHTBIT_NOT_RARE + andn %g1, %o4, %g1 +#endif + bne 11f + andcc %g1, %o3, %g0 + be 0b + add %o1, 4, %o1 + + srl %o4, 24, %g4 + andcc %g4, 0xff, %g0 + be 2f + srl %o4, 16, %g4 + andcc %g4, 0xff, %g0 + be 2f + srl %o4, 8, %g4 + andcc %g4, 0xff, %g0 + be 2f + andcc %o4, 0xff, %g0 + bne,a 1b + ld [%o0], %o4 +2: retl + clr %o0 + +11: srl %o4, 24, %g4 + srl %o5, 24, %g5 + andcc %g4, 0xff, %g0 + be 3f + subcc %g4, %g5, %g4 + bne 3f + srl %o5, 16, %g5 + srl %o4, 16, %g4 + andcc %g4, 0xff, %g0 + be 3f + subcc %g4, %g5, %g4 + bne 3f + srl %o5, 8, %g5 + srl %o4, 8, %g4 + andcc %g4, 0xff, %g0 + be 3f + subcc %g4, %g5, %g4 + bne 3f + subcc %o4, %o5, %o4 + retl + mov %o4, %o0 +3: retl + mov %g4, %o0 + +12: save %sp, -64, %sp + ld [%i0], %i4 + sll %g2, 3, %g3 + andn %i1, 3, %i1 + mov 32, %l1 + ld [%i1], %l2 + mov -1, %g6 + add %i1, 4, %i1 + sub %l1, %g3, %l1 + sll %g6, %g3, %g6 + +1: sll %l2, %g3, %g5 + and %i4, %g6, %l3 + sub %i4, %i2, %g1 +#ifdef EIGHTBIT_NOT_RARE + andn %g1, %i4, %g1 +#endif + andcc %g1, %i3, %g1 + bne 3f + cmp %g5, %l3 + bne 2f + add %i0, 4, %i0 + ld [%i1], %l2 + add %i1, 4, %i1 + srl %l2, %l1, %l4 + or %l4, %g5, %l4 + cmp %l4, %i4 + be,a 1b + ld [%i0], %i4 + restore %l4, %g0, %o3 + retl + sub %o4, %o3, %o0 + +2: sll %l2, %g3, %i2 + srl %i4, %g3, %i3 + srl %i2, %g3, %i2 + restore + retl + sub %o3, %o2, %o0 + +3: srl %i4, 24, %g4 + srl %g5, 24, %l6 + andcc %g4, 0xff, %g0 + be 4f + subcc %g4, %l6, %g4 + bne 4f + cmp %g2, 3 + be 6f + srl %i4, 16, %g4 + srl %g5, 16, %l6 + andcc %g4, 0xff, %g0 + be 4f + subcc %g4, %l6, %g4 + bne 4f + cmp %g2, 2 + be 5f + srl %i4, 8, %g4 + srl %g5, 8, %l6 + andcc %g4, 0xff, %g0 + be 4f + subcc %g4, %l6, %g4 + bne 4f + add %i0, 4, %i0 + ld [%i1], %l2 + add %i1, 4, %i1 + srl %l2, 24, %g5 + andcc %i4, 0xff, %g4 + be 4f + subcc %g4, %g5, %g4 + be,a 1b + ld [%i0], %i4 +4: jmpl %i7 + 8, %g0 + restore %g4, %g0, %o0 + +5: ld [%i1], %l2 + add %i1, 4, %i1 + add %i0, 4, %i0 + srl %l2, 24, %l6 + andcc %g4, 0xff, %g4 + be 4b + subcc %g4, %l6, %g4 + bne 4b + srl %l2, 16, %l6 + andcc %i4, 0xff, %g4 + and %l6, 0xff, %l6 + be 4b + subcc %g4, %l6, %g4 + be,a 1b + ld [%i0], %i4 + jmpl %i7 + 8, %g0 + restore %g4, %g0, %o0 + +6: ld [%i1], %l2 + add %i1, 4, %i1 + add %i0, 4, %i0 + srl %l2, 24, %l6 + andcc %g4, 0xff, %g4 + be 4b + subcc %g4, %l6, %g4 + bne 4b + srl %l2, 16, %l6 + srl %i4, 8, %g4 + and %l6, 0xff, %l6 + andcc %g4, 0xff, %g4 + be 4b + subcc %g4, %l6, %g4 + bne 4b + srl %l2, 8, %l6 + andcc %i4, 0xff, %g4 + and %l6, 0xff, %l6 + be 4b + subcc %g4, %l6, %g4 + be,a 1b + ld [%i0], %i4 + jmpl %i7 + 8, %g0 + restore %g4, %g0, %o0 +END(strcmp) +libc_hidden_builtin_def (strcmp) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/strcpy.S b/REORG.TODO/sysdeps/sparc/sparc32/strcpy.S new file mode 100644 index 0000000000..245b78d612 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/strcpy.S @@ -0,0 +1,276 @@ +/* Copy SRC to DEST returning DEST. + For SPARC v7. + Copyright (C) 1996-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jj@ultra.linux.cz>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* Normally, this uses ((xword - 0x01010101) & 0x80808080) test + to find out if any byte in xword could be zero. This is fast, but + also gives false alarm for any byte in range 0x81-0xff. It does + not matter for correctness, as if this test tells us there could + be some zero byte, we check it byte by byte, but if bytes with + high bits set are common in the strings, then this will give poor + performance. You can #define EIGHTBIT_NOT_RARE and the algorithm + will use one tick slower, but more precise test + ((xword - 0x01010101) & (~xword) & 0x80808080), + which does not give any false alarms (but if some bits are set, + one cannot assume from it which bytes are zero and which are not). + It is yet to be measured, what is the correct default for glibc + in these days for an average user. + */ + + .text + .align 4 + +ENTRY(strcpy) + mov %o0, %g2 + andcc %o1, 3, %g0 + be 10f + sethi %hi(0x80808080), %o4 + + ldub [%o1], %o5 + stb %o5, [%o0] + cmp %o5, 0 + add %o0, 1, %o0 + be 0f + add %o1, 1, %o1 + andcc %o1, 3, %g0 + be 4f + or %o4, %lo(0x80808080), %o3 + ldub [%o1], %o5 + stb %o5, [%o0] + cmp %o5, 0 + add %o0, 1, %o0 + be 0f + add %o1, 1, %o1 + andcc %o1, 3, %g0 + be 5f + sethi %hi(0x01010101), %o4 + ldub [%o1], %o5 + stb %o5, [%o0] + cmp %o5, 0 + add %o0, 1, %o0 + be 0f + add %o1, 1, %o1 + b 6f + andcc %o0, 3, %g3 + +10: or %o4, %lo(0x80808080), %o3 +4: sethi %hi(0x01010101), %o4 +5: andcc %o0, 3, %g3 +6: bne 10f + or %o4, %lo(0x01010101), %o2 +1: ld [%o1], %o5 + add %o1, 4, %o1 + sub %o5, %o2, %o4 + add %o0, 4, %o0 + andcc %o4, %o3, %g0 + be,a 1b + st %o5, [%o0 - 4] + + srl %o5, 24, %g5 + andcc %g5, 0xff, %g0 + be 1f + srl %o5, 16, %g5 + andcc %g5, 0xff, %g0 + be 2f + srl %o5, 8, %g5 + andcc %g5, 0xff, %g0 + be 3f + andcc %o5, 0xff, %g0 + bne 1b + st %o5, [%o0 - 4] + retl + mov %g2, %o0 +3: srl %o5, 16, %o5 + sth %o5, [%o0 - 4] + stb %g0, [%o0 - 2] + retl + mov %g2, %o0 +2: srl %o5, 16, %o5 + sth %o5, [%o0 - 4] + retl + mov %g2, %o0 +1: stb %g0, [%o0 - 4] + retl + mov %g2, %o0 + +10: ld [%o1], %o5 + add %o1, 4, %o1 + sub %o5, %o2, %o4 + cmp %g3, 2 + be 2f + cmp %g3, 3 + be 3f + andcc %o4, %o3, %g0 + bne 5f + srl %o5, 24, %g5 + stb %g5, [%o0] + sub %o0, 1, %o0 + srl %o5, 8, %g5 + sth %g5, [%o0 + 2] +1: add %o0, 4, %o0 +4: sll %o5, 24, %g6 + ld [%o1], %o5 + add %o1, 4, %o1 + srl %o5, 8, %g5 + sub %o5, %o2, %o4 + or %g5, %g6, %g5 + andcc %o4, %o3, %g0 + be,a 1b + st %g5, [%o0] + srl %o5, 24, %o4 + andcc %o4, 0xff, %g0 + be 6f + srl %o5, 16, %o4 + andcc %o4, 0xff, %g0 + be 7f + srl %o5, 8, %o4 + st %g5, [%o0] + andcc %o4, 0xff, %g0 + be 0f + andcc %o5, 0xff, %g0 +1: bne 4b + add %o0, 4, %o0 +9: stb %g0, [%o0] +0: retl + mov %g2, %o0 +6: srl %g5, 16, %g5 + sth %g5, [%o0] + retl + mov %g2, %o0 +7: srl %g5, 16, %g5 + sth %g5, [%o0] + stb %g0, [%o0 + 2] + retl + mov %g2, %o0 +5: andcc %g5, 0xff, %g4 + be 9b + srl %o5, 16, %g5 + andcc %g5, 0xff, %g0 + be 7f + srl %o5, 8, %g5 + andcc %g5, 0xff, %g0 + stb %g4, [%o0] + sth %g5, [%o0 + 1] + sub %o0, 1, %o0 + bne 1b + andcc %o5, 0xff, %g0 + retl + mov %g2, %o0 +7: stb %g4, [%o0] + stb %g0, [%o0 + 1] + retl + mov %g2, %o0 + +2: andcc %o4, %o3, %g0 + bne 5f + srl %o5, 16, %g5 + sth %g5, [%o0] + sub %o0, 2, %o0 +1: add %o0, 4, %o0 +4: sll %o5, 16, %g6 + ld [%o1], %o5 + add %o1, 4, %o1 + srl %o5, 16, %g5 + sub %o5, %o2, %o4 + or %g5, %g6, %g5 + andcc %o4, %o3, %g0 + be,a 1b + st %g5, [%o0] + srl %o5, 24, %o4 + andcc %o4, 0xff, %g0 + be 7f + srl %o5, 16, %o4 + st %g5, [%o0] + andcc %o4, 0xff, %g0 + be 0b + srl %o5, 8, %o4 +1: andcc %o4, 0xff, %g0 + be 8f + andcc %o5, 0xff, %g0 + bne 4b + add %o0, 4, %o0 + sth %o5, [%o0] + retl + mov %g2, %o0 +7: srl %g5, 16, %g5 + sth %g5, [%o0] + stb %g0, [%o0 + 2] + retl + mov %g2, %o0 +8: stb %g0, [%o0 + 4] + retl + mov %g2, %o0 +5: srl %o5, 24, %g5 + andcc %g5, 0xff, %g0 + be 9b + srl %o5, 16, %g5 + andcc %g5, 0xff, %g0 + sth %g5, [%o0] + sub %o0, 2, %o0 + bne 1b + srl %o5, 8, %o4 + retl + mov %g2, %o0 + +3: bne 5f + srl %o5, 24, %g5 + stb %g5, [%o0] + sub %o0, 3, %o0 +1: add %o0, 4, %o0 +4: sll %o5, 8, %g6 + ld [%o1], %o5 + add %o1, 4, %o1 + srl %o5, 24, %g5 + sub %o5, %o2, %o4 + or %g5, %g6, %g5 + andcc %o4, %o3, %g0 + be 1b + st %g5, [%o0] + srl %o5, 24, %o4 + andcc %o4, 0xff, %g0 + be 0b + srl %o5, 16, %o4 +1: andcc %o4, 0xff, %g0 + be 8b + srl %o5, 8, %o4 + andcc %o4, 0xff, %g0 + be 9f + andcc %o5, 0xff, %g0 + bne 4b + add %o0, 4, %o0 + srl %o5, 8, %o5 + sth %o5, [%o0] + stb %g0, [%o0 + 2] + retl + mov %g2, %o0 +9: srl %o5, 8, %o5 + sth %o5, [%o0 + 4] + retl + mov %g2, %o0 +5: andcc %g5, 0xff, %g0 + stb %g5, [%o0] + sub %o0, 3, %o0 + bne 1b + srl %o5, 16, %o4 + retl + mov %g2, %o0 +END(strcpy) +libc_hidden_builtin_def (strcpy) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/strlen.S b/REORG.TODO/sysdeps/sparc/sparc32/strlen.S new file mode 100644 index 0000000000..59baee884e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/strlen.S @@ -0,0 +1,75 @@ +/* Determine the length of a string. + For SPARC v7. + Copyright (C) 1996-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jj@ultra.linux.cz> and + David S. Miller <davem@davemloft.net>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .text + .align 4 + +ENTRY(strlen) + mov %o0, %o1 + andn %o0, 0x3, %o0 + + ld [%o0], %o5 + and %o1, 0x3, %g1 + mov -1, %g5 + + sethi %hi(0x01010101), %o2 + sll %g1, 3, %g1 + + or %o2, %lo(0x01010101), %o2 + srl %g5, %g1, %g2 + + orn %o5, %g2, %o5 + sll %o2, 7, %o3 +10: add %o0, 4, %o0 + + andn %o3, %o5, %g1 + sub %o5, %o2, %g2 + + andcc %g1, %g2, %g0 + be,a 10b + ld [%o0], %o5 + + srl %o5, 24, %g1 + + andcc %g1, 0xff, %g0 + be 90f + sub %o0, 4, %o0 + + srl %o5, 16, %g2 + + andcc %g2, 0xff, %g0 + be 90f + add %o0, 1, %o0 + + srl %o5, 8, %g1 + + andcc %g1, 0xff, %g0 + be 90f + add %o0, 1, %o0 + + add %o0, 1, %o0 + +90: retl + sub %o0, %o1, %o0 +END(strlen) +libc_hidden_builtin_def (strlen) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/strrchr.c b/REORG.TODO/sysdeps/sparc/sparc32/strrchr.c new file mode 100644 index 0000000000..ec608d6ab3 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/strrchr.c @@ -0,0 +1 @@ +/* strrchr is in strchr.S */ diff --git a/REORG.TODO/sysdeps/sparc/sparc32/sub_n.S b/REORG.TODO/sysdeps/sparc/sparc32/sub_n.S new file mode 100644 index 0000000000..22ca71fa93 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/sub_n.S @@ -0,0 +1,328 @@ +! SPARC __mpn_sub_n -- Subtract two limb vectors of the same length > 0 and +! store difference in a third limb vector. +! +! Copyright (C) 1995-2017 Free Software Foundation, Inc. +! +! This file is part of the GNU MP Library. +! +! The GNU MP Library is free software; you can redistribute it and/or modify +! it under the terms of the GNU Lesser General Public License as published by +! the Free Software Foundation; either version 2.1 of the License, or (at your +! option) any later version. +! +! The GNU MP Library is distributed in the hope that it will be useful, but +! WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +! or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +! License for more details. +! +! You should have received a copy of the GNU Lesser General Public License +! along with the GNU MP Library; see the file COPYING.LIB. If not, +! see <http://www.gnu.org/licenses/>. + + +! INPUT PARAMETERS +#define RES_PTR %o0 +#define S1_PTR %o1 +#define S2_PTR %o2 +#define SIZE %o3 + +#include <sysdep.h> + +ENTRY(__mpn_sub_n) + xor S2_PTR,RES_PTR,%g1 + andcc %g1,4,%g0 + bne LOC(1) ! branch if alignment differs + nop +! ** V1a ** + andcc RES_PTR,4,%g0 ! RES_PTR unaligned? Side effect: cy=0 + be LOC(v1) ! if no, branch + nop +/* Add least significant limb separately to align RES_PTR and S2_PTR */ + ld [S1_PTR],%g4 + add S1_PTR,4,S1_PTR + ld [S2_PTR],%g2 + add S2_PTR,4,S2_PTR + add SIZE,-1,SIZE + subcc %g4,%g2,%o4 + st %o4,[RES_PTR] + add RES_PTR,4,RES_PTR +LOC(v1): + addx %g0,%g0,%o4 ! save cy in register + cmp SIZE,2 ! if SIZE < 2 ... + bl LOC(end2) ! ... branch to tail code + subcc %g0,%o4,%g0 ! restore cy + + ld [S1_PTR+0],%g4 + addcc SIZE,-10,SIZE + ld [S1_PTR+4],%g1 + ldd [S2_PTR+0],%g2 + blt LOC(fin1) + subcc %g0,%o4,%g0 ! restore cy +/* Add blocks of 8 limbs until less than 8 limbs remain */ +LOC(loop1): + subxcc %g4,%g2,%o4 + ld [S1_PTR+8],%g4 + subxcc %g1,%g3,%o5 + ld [S1_PTR+12],%g1 + ldd [S2_PTR+8],%g2 + std %o4,[RES_PTR+0] + subxcc %g4,%g2,%o4 + ld [S1_PTR+16],%g4 + subxcc %g1,%g3,%o5 + ld [S1_PTR+20],%g1 + ldd [S2_PTR+16],%g2 + std %o4,[RES_PTR+8] + subxcc %g4,%g2,%o4 + ld [S1_PTR+24],%g4 + subxcc %g1,%g3,%o5 + ld [S1_PTR+28],%g1 + ldd [S2_PTR+24],%g2 + std %o4,[RES_PTR+16] + subxcc %g4,%g2,%o4 + ld [S1_PTR+32],%g4 + subxcc %g1,%g3,%o5 + ld [S1_PTR+36],%g1 + ldd [S2_PTR+32],%g2 + std %o4,[RES_PTR+24] + addx %g0,%g0,%o4 ! save cy in register + addcc SIZE,-8,SIZE + add S1_PTR,32,S1_PTR + add S2_PTR,32,S2_PTR + add RES_PTR,32,RES_PTR + bge LOC(loop1) + subcc %g0,%o4,%g0 ! restore cy + +LOC(fin1): + addcc SIZE,8-2,SIZE + blt LOC(end1) + subcc %g0,%o4,%g0 ! restore cy +/* Add blocks of 2 limbs until less than 2 limbs remain */ +LOC(loope1): + subxcc %g4,%g2,%o4 + ld [S1_PTR+8],%g4 + subxcc %g1,%g3,%o5 + ld [S1_PTR+12],%g1 + ldd [S2_PTR+8],%g2 + std %o4,[RES_PTR+0] + addx %g0,%g0,%o4 ! save cy in register + addcc SIZE,-2,SIZE + add S1_PTR,8,S1_PTR + add S2_PTR,8,S2_PTR + add RES_PTR,8,RES_PTR + bge LOC(loope1) + subcc %g0,%o4,%g0 ! restore cy +LOC(end1): + subxcc %g4,%g2,%o4 + subxcc %g1,%g3,%o5 + std %o4,[RES_PTR+0] + addx %g0,%g0,%o4 ! save cy in register + + andcc SIZE,1,%g0 + be LOC(ret1) + subcc %g0,%o4,%g0 ! restore cy +/* Add last limb */ + ld [S1_PTR+8],%g4 + ld [S2_PTR+8],%g2 + subxcc %g4,%g2,%o4 + st %o4,[RES_PTR+8] + +LOC(ret1): + retl + addx %g0,%g0,%o0 ! return carry-out from most sign. limb + +LOC(1): xor S1_PTR,RES_PTR,%g1 + andcc %g1,4,%g0 + bne LOC(2) + nop +! ** V1b ** + andcc RES_PTR,4,%g0 ! RES_PTR unaligned? Side effect: cy=0 + be LOC(v1b) ! if no, branch + nop +/* Add least significant limb separately to align RES_PTR and S1_PTR */ + ld [S2_PTR],%g4 + add S2_PTR,4,S2_PTR + ld [S1_PTR],%g2 + add S1_PTR,4,S1_PTR + add SIZE,-1,SIZE + subcc %g2,%g4,%o4 + st %o4,[RES_PTR] + add RES_PTR,4,RES_PTR +LOC(v1b): + addx %g0,%g0,%o4 ! save cy in register + cmp SIZE,2 ! if SIZE < 2 ... + bl LOC(end2) ! ... branch to tail code + subcc %g0,%o4,%g0 ! restore cy + + ld [S2_PTR+0],%g4 + addcc SIZE,-10,SIZE + ld [S2_PTR+4],%g1 + ldd [S1_PTR+0],%g2 + blt LOC(fin1b) + subcc %g0,%o4,%g0 ! restore cy +/* Add blocks of 8 limbs until less than 8 limbs remain */ +LOC(loop1b): + subxcc %g2,%g4,%o4 + ld [S2_PTR+8],%g4 + subxcc %g3,%g1,%o5 + ld [S2_PTR+12],%g1 + ldd [S1_PTR+8],%g2 + std %o4,[RES_PTR+0] + subxcc %g2,%g4,%o4 + ld [S2_PTR+16],%g4 + subxcc %g3,%g1,%o5 + ld [S2_PTR+20],%g1 + ldd [S1_PTR+16],%g2 + std %o4,[RES_PTR+8] + subxcc %g2,%g4,%o4 + ld [S2_PTR+24],%g4 + subxcc %g3,%g1,%o5 + ld [S2_PTR+28],%g1 + ldd [S1_PTR+24],%g2 + std %o4,[RES_PTR+16] + subxcc %g2,%g4,%o4 + ld [S2_PTR+32],%g4 + subxcc %g3,%g1,%o5 + ld [S2_PTR+36],%g1 + ldd [S1_PTR+32],%g2 + std %o4,[RES_PTR+24] + addx %g0,%g0,%o4 ! save cy in register + addcc SIZE,-8,SIZE + add S1_PTR,32,S1_PTR + add S2_PTR,32,S2_PTR + add RES_PTR,32,RES_PTR + bge LOC(loop1b) + subcc %g0,%o4,%g0 ! restore cy + +LOC(fin1b): + addcc SIZE,8-2,SIZE + blt LOC(end1b) + subcc %g0,%o4,%g0 ! restore cy +/* Add blocks of 2 limbs until less than 2 limbs remain */ +LOC(loope1b): + subxcc %g2,%g4,%o4 + ld [S2_PTR+8],%g4 + subxcc %g3,%g1,%o5 + ld [S2_PTR+12],%g1 + ldd [S1_PTR+8],%g2 + std %o4,[RES_PTR+0] + addx %g0,%g0,%o4 ! save cy in register + addcc SIZE,-2,SIZE + add S1_PTR,8,S1_PTR + add S2_PTR,8,S2_PTR + add RES_PTR,8,RES_PTR + bge LOC(loope1b) + subcc %g0,%o4,%g0 ! restore cy +LOC(end1b): + subxcc %g2,%g4,%o4 + subxcc %g3,%g1,%o5 + std %o4,[RES_PTR+0] + addx %g0,%g0,%o4 ! save cy in register + + andcc SIZE,1,%g0 + be LOC(ret1b) + subcc %g0,%o4,%g0 ! restore cy +/* Add last limb */ + ld [S2_PTR+8],%g4 + ld [S1_PTR+8],%g2 + subxcc %g2,%g4,%o4 + st %o4,[RES_PTR+8] + +LOC(ret1b): + retl + addx %g0,%g0,%o0 ! return carry-out from most sign. limb + +! ** V2 ** +/* If we come here, the alignment of S1_PTR and RES_PTR as well as the + alignment of S2_PTR and RES_PTR differ. Since there are only two ways + things can be aligned (that we care about) we now know that the alignment + of S1_PTR and S2_PTR are the same. */ + +LOC(2): cmp SIZE,1 + be LOC(jone) + nop + andcc S1_PTR,4,%g0 ! S1_PTR unaligned? Side effect: cy=0 + be LOC(v2) ! if no, branch + nop +/* Add least significant limb separately to align S1_PTR and S2_PTR */ + ld [S1_PTR],%g4 + add S1_PTR,4,S1_PTR + ld [S2_PTR],%g2 + add S2_PTR,4,S2_PTR + add SIZE,-1,SIZE + subcc %g4,%g2,%o4 + st %o4,[RES_PTR] + add RES_PTR,4,RES_PTR + +LOC(v2): + addx %g0,%g0,%o4 ! save cy in register + addcc SIZE,-8,SIZE + blt LOC(fin2) + subcc %g0,%o4,%g0 ! restore cy +/* Add blocks of 8 limbs until less than 8 limbs remain */ +LOC(loop2): + ldd [S1_PTR+0],%g2 + ldd [S2_PTR+0],%o4 + subxcc %g2,%o4,%g2 + st %g2,[RES_PTR+0] + subxcc %g3,%o5,%g3 + st %g3,[RES_PTR+4] + ldd [S1_PTR+8],%g2 + ldd [S2_PTR+8],%o4 + subxcc %g2,%o4,%g2 + st %g2,[RES_PTR+8] + subxcc %g3,%o5,%g3 + st %g3,[RES_PTR+12] + ldd [S1_PTR+16],%g2 + ldd [S2_PTR+16],%o4 + subxcc %g2,%o4,%g2 + st %g2,[RES_PTR+16] + subxcc %g3,%o5,%g3 + st %g3,[RES_PTR+20] + ldd [S1_PTR+24],%g2 + ldd [S2_PTR+24],%o4 + subxcc %g2,%o4,%g2 + st %g2,[RES_PTR+24] + subxcc %g3,%o5,%g3 + st %g3,[RES_PTR+28] + addx %g0,%g0,%o4 ! save cy in register + addcc SIZE,-8,SIZE + add S1_PTR,32,S1_PTR + add S2_PTR,32,S2_PTR + add RES_PTR,32,RES_PTR + bge LOC(loop2) + subcc %g0,%o4,%g0 ! restore cy + +LOC(fin2): + addcc SIZE,8-2,SIZE + blt LOC(end2) + subcc %g0,%o4,%g0 ! restore cy +LOC(loope2): + ldd [S1_PTR+0],%g2 + ldd [S2_PTR+0],%o4 + subxcc %g2,%o4,%g2 + st %g2,[RES_PTR+0] + subxcc %g3,%o5,%g3 + st %g3,[RES_PTR+4] + addx %g0,%g0,%o4 ! save cy in register + addcc SIZE,-2,SIZE + add S1_PTR,8,S1_PTR + add S2_PTR,8,S2_PTR + add RES_PTR,8,RES_PTR + bge LOC(loope2) + subcc %g0,%o4,%g0 ! restore cy +LOC(end2): + andcc SIZE,1,%g0 + be LOC(ret2) + subcc %g0,%o4,%g0 ! restore cy +/* Add last limb */ +LOC(jone): + ld [S1_PTR],%g4 + ld [S2_PTR],%g2 + subxcc %g4,%g2,%o4 + st %o4,[RES_PTR] + +LOC(ret2): + retl + addx %g0,%g0,%o0 ! return carry-out from most sign. limb + +END(__mpn_sub_n) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/submul_1.S b/REORG.TODO/sysdeps/sparc/sparc32/submul_1.S new file mode 100644 index 0000000000..58dd2a3fc6 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/submul_1.S @@ -0,0 +1,146 @@ +! SPARC __mpn_submul_1 -- Multiply a limb vector with a limb and subtract +! the result from a second limb vector. +! +! Copyright (C) 1992-2017 Free Software Foundation, Inc. +! +! This file is part of the GNU MP Library. +! +! The GNU MP Library is free software; you can redistribute it and/or modify +! it under the terms of the GNU Lesser General Public License as published by +! the Free Software Foundation; either version 2.1 of the License, or (at your +! option) any later version. +! +! The GNU MP Library is distributed in the hope that it will be useful, but +! WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +! or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +! License for more details. +! +! You should have received a copy of the GNU Lesser General Public License +! along with the GNU MP Library; see the file COPYING.LIB. If not, +! see <http://www.gnu.org/licenses/>. + + +! INPUT PARAMETERS +! RES_PTR o0 +! S1_PTR o1 +! SIZE o2 +! S2_LIMB o3 + +#include <sysdep.h> + +ENTRY(__mpn_submul_1) + ! Make S1_PTR and RES_PTR point at the end of their blocks + ! and put (- 4 x SIZE) in index/loop counter. + sll %o2,2,%o2 + add %o0,%o2,%o4 ! RES_PTR in o4 since o0 is retval + add %o1,%o2,%o1 + sub %g0,%o2,%o2 + + cmp %o3,0xfff + bgu LOC(large) + nop + + ld [%o1+%o2],%o5 + mov 0,%o0 + b LOC(0) + add %o4,-4,%o4 +LOC(loop0): + subcc %o5,%g1,%g1 + ld [%o1+%o2],%o5 + addx %o0,%g0,%o0 + st %g1,[%o4+%o2] +LOC(0): wr %g0,%o3,%y + sra %o5,31,%g2 + and %o3,%g2,%g2 + andcc %g1,0,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,%o5,%g1 + mulscc %g1,0,%g1 + sra %g1,20,%g4 + sll %g1,12,%g1 + rd %y,%g3 + srl %g3,20,%g3 + or %g1,%g3,%g1 + + addcc %g1,%o0,%g1 + addx %g2,%g4,%o0 ! add sign-compensation and cy to hi limb + addcc %o2,4,%o2 ! loop counter + bne LOC(loop0) + ld [%o4+%o2],%o5 + + subcc %o5,%g1,%g1 + addx %o0,%g0,%o0 + retl + st %g1,[%o4+%o2] + + +LOC(large): + ld [%o1+%o2],%o5 + mov 0,%o0 + sra %o3,31,%g4 ! g4 = mask of ones iff S2_LIMB < 0 + b LOC(1) + add %o4,-4,%o4 +LOC(loop): + subcc %o5,%g3,%g3 + ld [%o1+%o2],%o5 + addx %o0,%g0,%o0 + st %g3,[%o4+%o2] +LOC(1): wr %g0,%o5,%y + and %o5,%g4,%g2 + andcc %g0,%g0,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%o3,%g1 + mulscc %g1,%g0,%g1 + rd %y,%g3 + addcc %g3,%o0,%g3 + addx %g2,%g1,%o0 + addcc %o2,4,%o2 + bne LOC(loop) + ld [%o4+%o2],%o5 + + subcc %o5,%g3,%g3 + addx %o0,%g0,%o0 + retl + st %g3,[%o4+%o2] + +END(__mpn_submul_1) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/tls-macros.h b/REORG.TODO/sysdeps/sparc/sparc32/tls-macros.h new file mode 100644 index 0000000000..152216e8a8 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/tls-macros.h @@ -0,0 +1,66 @@ +#define TLS_LE(x) \ + ({ int *__l; \ + asm ("sethi %%tle_hix22(" #x "), %0" : "=r" (__l)); \ + asm ("xor %1, %%tle_lox10(" #x "), %0" : "=r" (__l) : "r" (__l)); \ + asm ("add %%g7, %1, %0" : "=r" (__l) : "r" (__l)); \ + __l; }) + +#ifdef __PIC__ +# define TLS_LOAD_PIC \ + ({ register long pc __asm__ ("%o7"); \ + long got; \ + asm ("sethi %%hi(_GLOBAL_OFFSET_TABLE_-4), %1\n\t" \ + "call .+8\n\t" \ + "add %1, %%lo(_GLOBAL_OFFSET_TABLE_+4), %1\n\t" \ + "add %1, %0, %1\n\t" \ + : "=r" (pc), "=r" (got)); \ + got; }) +#else +# define TLS_LOAD_PIC \ + ({ long got; \ + asm (".hidden _GLOBAL_OFFSET_TABLE_\n\t" \ + "sethi %%hi(_GLOBAL_OFFSET_TABLE_), %0\n\t" \ + "or %0, %%lo(_GLOBAL_OFFSET_TABLE_), %0" \ + : "=r" (got)); \ + got; }) +#endif + +#define TLS_IE(x) \ + ({ int *__l; \ + asm ("sethi %%tie_hi22(" #x "), %0" : "=r" (__l)); \ + asm ("add %1, %%tie_lo10(" #x "), %0" : "=r" (__l) : "r" (__l)); \ + asm ("ld [%1 + %2], %0, %%tie_ld(" #x ")" \ + : "=r" (__l) : "r" (TLS_LOAD_PIC), "r" (__l)); \ + asm ("add %%g7, %1, %0, %%tie_add(" #x ")" : "=r" (__l) : "r" (__l)); \ + __l; }) + +#define TLS_LD(x) \ + ({ int *__l; register void *__o0 asm ("%o0"); \ + long __o; \ + asm ("sethi %%tldm_hi22(" #x "), %0" : "=r" (__l)); \ + asm ("add %1, %%tldm_lo10(" #x "), %0" : "=r" (__l) : "r" (__l)); \ + asm ("add %1, %2, %0, %%tldm_add(" #x ")" \ + : "=r" (__o0) : "r" (TLS_LOAD_PIC), "r" (__l)); \ + asm ("call __tls_get_addr, %%tgd_call(" #x ")\n\t" \ + " nop" \ + : "=r" (__o0) : "0" (__o0) \ + : "g1", "g2", "g3", "g4", "g5", "g6", "o1", "o2", "o3", "o4", \ + "o5", "o7", "cc"); \ + asm ("sethi %%tldo_hix22(" #x "), %0" : "=r" (__o)); \ + asm ("xor %1, %%tldo_lox10(" #x "), %0" : "=r" (__o) : "r" (__o)); \ + asm ("add %1, %2, %0, %%tldo_add(" #x ")" : "=r" (__l) \ + : "r" (__o0), "r" (__o)); \ + __l; }) + +#define TLS_GD(x) \ + ({ int *__l; register void *__o0 asm ("%o0"); \ + asm ("sethi %%tgd_hi22(" #x "), %0" : "=r" (__l)); \ + asm ("add %1, %%tgd_lo10(" #x "), %0" : "=r" (__l) : "r" (__l)); \ + asm ("add %1, %2, %0, %%tgd_add(" #x ")" \ + : "=r" (__o0) : "r" (TLS_LOAD_PIC), "r" (__l)); \ + asm ("call __tls_get_addr, %%tgd_call(" #x ")\n\t" \ + " nop" \ + : "=r" (__o0) : "0" (__o0) \ + : "g1", "g2", "g3", "g4", "g5", "g6", "o1", "o2", "o3", "o4", \ + "o5", "o7", "cc"); \ + __o0; }) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/tst-audit.h b/REORG.TODO/sysdeps/sparc/sparc32/tst-audit.h new file mode 100644 index 0000000000..a437dade69 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/tst-audit.h @@ -0,0 +1,25 @@ +/* Definitions for testing PLT entry/exit auditing. SPARC32 version. + + Copyright (C) 2012-2017 Free Software Foundation, Inc. + + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library. If not, see + <http://www.gnu.org/licenses/>. */ + +#define pltenter la_sparc32_gnu_pltenter +#define pltexit la_sparc32_gnu_pltexit +#define La_regs La_sparc32_regs +#define La_retval La_sparc32_retval +#define int_retval lrv_reg[0] diff --git a/REORG.TODO/sysdeps/sparc/sparc32/udiv.S b/REORG.TODO/sysdeps/sparc/sparc32/udiv.S new file mode 100644 index 0000000000..ade0afdf40 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/udiv.S @@ -0,0 +1,347 @@ + /* This file is generated from divrem.m4; DO NOT EDIT! */ +/* + * Division and remainder, from Appendix E of the Sparc Version 8 + * Architecture Manual, with fixes from Gordon Irlam. + */ + +/* + * Input: dividend and divisor in %o0 and %o1 respectively. + * + * m4 parameters: + * .udiv name of function to generate + * div div=div => %o0 / %o1; div=rem => %o0 % %o1 + * false false=true => signed; false=false => unsigned + * + * Algorithm parameters: + * N how many bits per iteration we try to get (4) + * WORDSIZE total number of bits (32) + * + * Derived constants: + * TOPBITS number of bits in the top decade of a number + * + * Important variables: + * Q the partial quotient under development (initially 0) + * R the remainder so far, initially the dividend + * ITER number of main division loop iterations required; + * equal to ceil(log2(quotient) / N). Note that this + * is the log base (2^N) of the quotient. + * V the current comparand, initially divisor*2^(ITER*N-1) + * + * Cost: + * Current estimate for non-large dividend is + * ceil(log2(quotient) / N) * (10 + 7N/2) + C + * A large dividend is one greater than 2^(31-TOPBITS) and takes a + * different path, as the upper bits of the quotient must be developed + * one bit at a time. + */ + + + +#include <sysdep.h> +#include <sys/trap.h> + +ENTRY(.udiv) + + ! Ready to divide. Compute size of quotient; scale comparand. + orcc %o1, %g0, %o5 + bne 1f + mov %o0, %o3 + + ! Divide by zero trap. If it returns, return 0 (about as + ! wrong as possible, but that is what SunOS does...). + ta ST_DIV0 + retl + clr %o0 + +1: + cmp %o3, %o5 ! if %o1 exceeds %o0, done + blu LOC(got_result) ! (and algorithm fails otherwise) + clr %o2 + sethi %hi(1 << (32 - 4 - 1)), %g1 + cmp %o3, %g1 + blu LOC(not_really_big) + clr %o4 + + ! Here the dividend is >= 2**(31-N) or so. We must be careful here, + ! as our usual N-at-a-shot divide step will cause overflow and havoc. + ! The number of bits in the result here is N*ITER+SC, where SC <= N. + ! Compute ITER in an unorthodox manner: know we need to shift V into + ! the top decade: so do not even bother to compare to R. + 1: + cmp %o5, %g1 + bgeu 3f + mov 1, %g2 + sll %o5, 4, %o5 + b 1b + add %o4, 1, %o4 + + ! Now compute %g2. + 2: addcc %o5, %o5, %o5 + bcc LOC(not_too_big) + add %g2, 1, %g2 + + ! We get here if the %o1 overflowed while shifting. + ! This means that %o3 has the high-order bit set. + ! Restore %o5 and subtract from %o3. + sll %g1, 4, %g1 ! high order bit + srl %o5, 1, %o5 ! rest of %o5 + add %o5, %g1, %o5 + b LOC(do_single_div) + sub %g2, 1, %g2 + + LOC(not_too_big): + 3: cmp %o5, %o3 + blu 2b + nop + be LOC(do_single_div) + nop + /* NB: these are commented out in the V8-Sparc manual as well */ + /* (I do not understand this) */ + ! %o5 > %o3: went too far: back up 1 step + ! srl %o5, 1, %o5 + ! dec %g2 + ! do single-bit divide steps + ! + ! We have to be careful here. We know that %o3 >= %o5, so we can do the + ! first divide step without thinking. BUT, the others are conditional, + ! and are only done if %o3 >= 0. Because both %o3 and %o5 may have the high- + ! order bit set in the first step, just falling into the regular + ! division loop will mess up the first time around. + ! So we unroll slightly... + LOC(do_single_div): + subcc %g2, 1, %g2 + bl LOC(end_regular_divide) + nop + sub %o3, %o5, %o3 + mov 1, %o2 + b LOC(end_single_divloop) + nop + LOC(single_divloop): + sll %o2, 1, %o2 + bl 1f + srl %o5, 1, %o5 + ! %o3 >= 0 + sub %o3, %o5, %o3 + b 2f + add %o2, 1, %o2 + 1: ! %o3 < 0 + add %o3, %o5, %o3 + sub %o2, 1, %o2 + 2: + LOC(end_single_divloop): + subcc %g2, 1, %g2 + bge LOC(single_divloop) + tst %o3 + b,a LOC(end_regular_divide) + +LOC(not_really_big): +1: + sll %o5, 4, %o5 + cmp %o5, %o3 + bleu 1b + addcc %o4, 1, %o4 + be LOC(got_result) + sub %o4, 1, %o4 + + tst %o3 ! set up for initial iteration +LOC(divloop): + sll %o2, 4, %o2 + ! depth 1, accumulated bits 0 + bl LOC(1.16) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 2, accumulated bits 1 + bl LOC(2.17) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 3, accumulated bits 3 + bl LOC(3.19) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits 7 + bl LOC(4.23) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (7*2+1), %o2 + +LOC(4.23): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (7*2-1), %o2 + + +LOC(3.19): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits 5 + bl LOC(4.21) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (5*2+1), %o2 + +LOC(4.21): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (5*2-1), %o2 + + + +LOC(2.17): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 3, accumulated bits 1 + bl LOC(3.17) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits 3 + bl LOC(4.19) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (3*2+1), %o2 + +LOC(4.19): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (3*2-1), %o2 + + +LOC(3.17): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits 1 + bl LOC(4.17) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (1*2+1), %o2 + +LOC(4.17): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (1*2-1), %o2 + + + + +LOC(1.16): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 2, accumulated bits -1 + bl LOC(2.15) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 3, accumulated bits -1 + bl LOC(3.15) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits -1 + bl LOC(4.15) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-1*2+1), %o2 + +LOC(4.15): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-1*2-1), %o2 + + +LOC(3.15): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits -3 + bl LOC(4.13) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-3*2+1), %o2 + +LOC(4.13): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-3*2-1), %o2 + + + +LOC(2.15): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 3, accumulated bits -3 + bl LOC(3.13) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits -5 + bl LOC(4.11) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-5*2+1), %o2 + +LOC(4.11): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-5*2-1), %o2 + + +LOC(3.13): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits -7 + bl LOC(4.9) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-7*2+1), %o2 + +LOC(4.9): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-7*2-1), %o2 + + + + + 9: +LOC(end_regular_divide): + subcc %o4, 1, %o4 + bge LOC(divloop) + tst %o3 + bl,a LOC(got_result) + ! non-restoring fixup here (one instruction only!) + sub %o2, 1, %o2 + + +LOC(got_result): + + retl + mov %o2, %o0 + +END(.udiv) +strong_alias (.udiv, __wrap_.udiv) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/umul.S b/REORG.TODO/sysdeps/sparc/sparc32/umul.S new file mode 100644 index 0000000000..096554a2bc --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/umul.S @@ -0,0 +1,155 @@ +/* + * Unsigned multiply. Returns %o0 * %o1 in %o1%o0 (i.e., %o1 holds the + * upper 32 bits of the 64-bit product). + * + * This code optimizes short (less than 13-bit) multiplies. Short + * multiplies require 25 instruction cycles, and long ones require + * 45 instruction cycles. + * + * On return, overflow has occurred (%o1 is not zero) if and only if + * the Z condition code is clear, allowing, e.g., the following: + * + * call .umul + * nop + * bnz overflow (or tnz) + */ + +#include <sysdep.h> + +ENTRY(.umul) + or %o0, %o1, %o4 + mov %o0, %y ! multiplier -> Y + andncc %o4, 0xfff, %g0 ! test bits 12..31 of *both* args + be LOC(mul_shortway) ! if zero, can do it the short way + andcc %g0, %g0, %o4 ! zero the partial product; clear N & V + + /* + * Long multiply. 32 steps, followed by a final shift step. + */ + mulscc %o4, %o1, %o4 ! 1 + mulscc %o4, %o1, %o4 ! 2 + mulscc %o4, %o1, %o4 ! 3 + mulscc %o4, %o1, %o4 ! 4 + mulscc %o4, %o1, %o4 ! 5 + mulscc %o4, %o1, %o4 ! 6 + mulscc %o4, %o1, %o4 ! 7 + mulscc %o4, %o1, %o4 ! 8 + mulscc %o4, %o1, %o4 ! 9 + mulscc %o4, %o1, %o4 ! 10 + mulscc %o4, %o1, %o4 ! 11 + mulscc %o4, %o1, %o4 ! 12 + mulscc %o4, %o1, %o4 ! 13 + mulscc %o4, %o1, %o4 ! 14 + mulscc %o4, %o1, %o4 ! 15 + mulscc %o4, %o1, %o4 ! 16 + mulscc %o4, %o1, %o4 ! 17 + mulscc %o4, %o1, %o4 ! 18 + mulscc %o4, %o1, %o4 ! 19 + mulscc %o4, %o1, %o4 ! 20 + mulscc %o4, %o1, %o4 ! 21 + mulscc %o4, %o1, %o4 ! 22 + mulscc %o4, %o1, %o4 ! 23 + mulscc %o4, %o1, %o4 ! 24 + mulscc %o4, %o1, %o4 ! 25 + mulscc %o4, %o1, %o4 ! 26 + mulscc %o4, %o1, %o4 ! 27 + mulscc %o4, %o1, %o4 ! 28 + mulscc %o4, %o1, %o4 ! 29 + mulscc %o4, %o1, %o4 ! 30 + mulscc %o4, %o1, %o4 ! 31 + mulscc %o4, %o1, %o4 ! 32 + mulscc %o4, %g0, %o4 ! final shift + + /* + * Normally, with the shift-and-add approach, if both numbers are + * positive you get the correct result. With 32-bit two's-complement + * numbers, -x is represented as + * + * x 32 + * ( 2 - ------ ) mod 2 * 2 + * 32 + * 2 + * + * (the `mod 2' subtracts 1 from 1.bbbb). To avoid lots of 2^32s, + * we can treat this as if the radix point were just to the left + * of the sign bit (multiply by 2^32), and get + * + * -x = (2 - x) mod 2 + * + * Then, ignoring the `mod 2's for convenience: + * + * x * y = xy + * -x * y = 2y - xy + * x * -y = 2x - xy + * -x * -y = 4 - 2x - 2y + xy + * + * For signed multiplies, we subtract (x << 32) from the partial + * product to fix this problem for negative multipliers (see mul.s). + * Because of the way the shift into the partial product is calculated + * (N xor V), this term is automatically removed for the multiplicand, + * so we don't have to adjust. + * + * But for unsigned multiplies, the high order bit wasn't a sign bit, + * and the correction is wrong. So for unsigned multiplies where the + * high order bit is one, we end up with xy - (y << 32). To fix it + * we add y << 32. + */ +#if 0 + tst %o1 + bl,a 1f ! if %o1 < 0 (high order bit = 1), + add %o4, %o0, %o4 ! %o4 += %o0 (add y to upper half) +1: rd %y, %o0 ! get lower half of product + retl + addcc %o4, %g0, %o1 ! put upper half in place and set Z for %o1==0 +#else + /* Faster code from tege@sics.se. */ + sra %o1, 31, %o2 ! make mask from sign bit + and %o0, %o2, %o2 ! %o2 = 0 or %o0, depending on sign of %o1 + rd %y, %o0 ! get lower half of product + retl + addcc %o4, %o2, %o1 ! add compensation and put upper half in place +#endif + +LOC(mul_shortway): + /* + * Short multiply. 12 steps, followed by a final shift step. + * The resulting bits are off by 12 and (32-12) = 20 bit positions, + * but there is no problem with %o0 being negative (unlike above), + * and overflow is impossible (the answer is at most 24 bits long). + */ + mulscc %o4, %o1, %o4 ! 1 + mulscc %o4, %o1, %o4 ! 2 + mulscc %o4, %o1, %o4 ! 3 + mulscc %o4, %o1, %o4 ! 4 + mulscc %o4, %o1, %o4 ! 5 + mulscc %o4, %o1, %o4 ! 6 + mulscc %o4, %o1, %o4 ! 7 + mulscc %o4, %o1, %o4 ! 8 + mulscc %o4, %o1, %o4 ! 9 + mulscc %o4, %o1, %o4 ! 10 + mulscc %o4, %o1, %o4 ! 11 + mulscc %o4, %o1, %o4 ! 12 + mulscc %o4, %g0, %o4 ! final shift + + /* + * %o4 has 20 of the bits that should be in the result; %y has + * the bottom 12 (as %y's top 12). That is: + * + * %o4 %y + * +----------------+----------------+ + * | -12- | -20- | -12- | -20- | + * +------(---------+------)---------+ + * -----result----- + * + * The 12 bits of %o4 left of the `result' area are all zero; + * in fact, all top 20 bits of %o4 are zero. + */ + + rd %y, %o5 + sll %o4, 12, %o0 ! shift middle bits left 12 + srl %o5, 20, %o5 ! shift low bits right 20 + or %o5, %o0, %o0 + retl + addcc %g0, %g0, %o1 ! %o1 = zero, and set Z + +END(.umul) diff --git a/REORG.TODO/sysdeps/sparc/sparc32/urem.S b/REORG.TODO/sysdeps/sparc/sparc32/urem.S new file mode 100644 index 0000000000..d3a1a441fd --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc32/urem.S @@ -0,0 +1,346 @@ + /* This file is generated from divrem.m4; DO NOT EDIT! */ +/* + * Division and remainder, from Appendix E of the Sparc Version 8 + * Architecture Manual, with fixes from Gordon Irlam. + */ + +/* + * Input: dividend and divisor in %o0 and %o1 respectively. + * + * m4 parameters: + * .urem name of function to generate + * rem rem=div => %o0 / %o1; rem=rem => %o0 % %o1 + * false false=true => signed; false=false => unsigned + * + * Algorithm parameters: + * N how many bits per iteration we try to get (4) + * WORDSIZE total number of bits (32) + * + * Derived constants: + * TOPBITS number of bits in the top decade of a number + * + * Important variables: + * Q the partial quotient under development (initially 0) + * R the remainder so far, initially the dividend + * ITER number of main division loop iterations required; + * equal to ceil(log2(quotient) / N). Note that this + * is the log base (2^N) of the quotient. + * V the current comparand, initially divisor*2^(ITER*N-1) + * + * Cost: + * Current estimate for non-large dividend is + * ceil(log2(quotient) / N) * (10 + 7N/2) + C + * A large dividend is one greater than 2^(31-TOPBITS) and takes a + * different path, as the upper bits of the quotient must be developed + * one bit at a time. + */ + + + +#include <sysdep.h> +#include <sys/trap.h> + +ENTRY(.urem) + + ! Ready to divide. Compute size of quotient; scale comparand. + orcc %o1, %g0, %o5 + bne 1f + mov %o0, %o3 + + ! Divide by zero trap. If it returns, return 0 (about as + ! wrong as possible, but that is what SunOS does...). + ta ST_DIV0 + retl + clr %o0 + +1: + cmp %o3, %o5 ! if %o1 exceeds %o0, done + blu LOC(got_result) ! (and algorithm fails otherwise) + clr %o2 + sethi %hi(1 << (32 - 4 - 1)), %g1 + cmp %o3, %g1 + blu LOC(not_really_big) + clr %o4 + + ! Here the dividend is >= 2**(31-N) or so. We must be careful here, + ! as our usual N-at-a-shot divide step will cause overflow and havoc. + ! The number of bits in the result here is N*ITER+SC, where SC <= N. + ! Compute ITER in an unorthodox manner: know we need to shift V into + ! the top decade: so do not even bother to compare to R. + 1: + cmp %o5, %g1 + bgeu 3f + mov 1, %g2 + sll %o5, 4, %o5 + b 1b + add %o4, 1, %o4 + + ! Now compute %g2. + 2: addcc %o5, %o5, %o5 + bcc LOC(not_too_big) + add %g2, 1, %g2 + + ! We get here if the %o1 overflowed while shifting. + ! This means that %o3 has the high-order bit set. + ! Restore %o5 and subtract from %o3. + sll %g1, 4, %g1 ! high order bit + srl %o5, 1, %o5 ! rest of %o5 + add %o5, %g1, %o5 + b LOC(do_single_div) + sub %g2, 1, %g2 + + LOC(not_too_big): + 3: cmp %o5, %o3 + blu 2b + nop + be LOC(do_single_div) + nop + /* NB: these are commented out in the V8-Sparc manual as well */ + /* (I do not understand this) */ + ! %o5 > %o3: went too far: back up 1 step + ! srl %o5, 1, %o5 + ! dec %g2 + ! do single-bit divide steps + ! + ! We have to be careful here. We know that %o3 >= %o5, so we can do the + ! first divide step without thinking. BUT, the others are conditional, + ! and are only done if %o3 >= 0. Because both %o3 and %o5 may have the high- + ! order bit set in the first step, just falling into the regular + ! division loop will mess up the first time around. + ! So we unroll slightly... + LOC(do_single_div): + subcc %g2, 1, %g2 + bl LOC(end_regular_divide) + nop + sub %o3, %o5, %o3 + mov 1, %o2 + b LOC(end_single_divloop) + nop + LOC(single_divloop): + sll %o2, 1, %o2 + bl 1f + srl %o5, 1, %o5 + ! %o3 >= 0 + sub %o3, %o5, %o3 + b 2f + add %o2, 1, %o2 + 1: ! %o3 < 0 + add %o3, %o5, %o3 + sub %o2, 1, %o2 + 2: + LOC(end_single_divloop): + subcc %g2, 1, %g2 + bge LOC(single_divloop) + tst %o3 + b,a LOC(end_regular_divide) + +LOC(not_really_big): +1: + sll %o5, 4, %o5 + cmp %o5, %o3 + bleu 1b + addcc %o4, 1, %o4 + be LOC(got_result) + sub %o4, 1, %o4 + + tst %o3 ! set up for initial iteration +LOC(divloop): + sll %o2, 4, %o2 + ! depth 1, accumulated bits 0 + bl LOC(1.16) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 2, accumulated bits 1 + bl LOC(2.17) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 3, accumulated bits 3 + bl LOC(3.19) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits 7 + bl LOC(4.23) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (7*2+1), %o2 + +LOC(4.23): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (7*2-1), %o2 + + +LOC(3.19): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits 5 + bl LOC(4.21) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (5*2+1), %o2 + +LOC(4.21): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (5*2-1), %o2 + + + +LOC(2.17): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 3, accumulated bits 1 + bl LOC(3.17) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits 3 + bl LOC(4.19) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (3*2+1), %o2 + +LOC(4.19): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (3*2-1), %o2 + + +LOC(3.17): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits 1 + bl LOC(4.17) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (1*2+1), %o2 + +LOC(4.17): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (1*2-1), %o2 + + + + +LOC(1.16): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 2, accumulated bits -1 + bl LOC(2.15) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 3, accumulated bits -1 + bl LOC(3.15) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits -1 + bl LOC(4.15) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-1*2+1), %o2 + +LOC(4.15): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-1*2-1), %o2 + + +LOC(3.15): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits -3 + bl LOC(4.13) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-3*2+1), %o2 + +LOC(4.13): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-3*2-1), %o2 + + + +LOC(2.15): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 3, accumulated bits -3 + bl LOC(3.13) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits -5 + bl LOC(4.11) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-5*2+1), %o2 + +LOC(4.11): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-5*2-1), %o2 + + +LOC(3.13): + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits -7 + bl LOC(4.9) + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-7*2+1), %o2 + +LOC(4.9): + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-7*2-1), %o2 + + + + + 9: +LOC(end_regular_divide): + subcc %o4, 1, %o4 + bge LOC(divloop) + tst %o3 + bl,a LOC(got_result) + ! non-restoring fixup here (one instruction only!) + add %o3, %o1, %o3 + + +LOC(got_result): + + retl + mov %o3, %o0 + +END(.urem) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/Implies b/REORG.TODO/sysdeps/sparc/sparc64/Implies new file mode 100644 index 0000000000..7abc50efcc --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/Implies @@ -0,0 +1,7 @@ +wordsize-64 +# SPARC uses IEEE 754 floating point. +ieee754/ldbl-128 +ieee754/dbl-64/wordsize-64 +ieee754/dbl-64 +ieee754/flt-32 +sparc/sparc64/soft-fp diff --git a/REORG.TODO/sysdeps/sparc/sparc64/Makefile b/REORG.TODO/sysdeps/sparc/sparc64/Makefile new file mode 100644 index 0000000000..a5e403630e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/Makefile @@ -0,0 +1,21 @@ +sysdep-CFLAGS += -Wa,-Av9a -mvis + +ifeq ($(subdir),string) +sysdep_routines += align-cpy +endif + +ifeq ($(have-as-vis3),yes) +ASFLAGS-.o += -Wa,-Av9d +ASFLAGS-.os += -Wa,-Av9d +ASFLAGS-.op += -Wa,-Av9d +ASFLAGS-.oS += -Wa,-Av9d +endif + +# nscd uses atomic_spin_nop which in turn requires cpu_relax +ifeq ($(subdir),nscd) +routines += cpu_relax +endif + +ifeq ($(subdir),nptl) +libpthread-routines += cpu_relax +endif diff --git a/REORG.TODO/sysdeps/sparc/sparc64/Versions b/REORG.TODO/sysdeps/sparc/sparc64/Versions new file mode 100644 index 0000000000..4cef7bcc71 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/Versions @@ -0,0 +1,14 @@ +libc { + GLIBC_2.1.1 { + # SPARC v9 SYSV ABI helper functions + __align_cpy_1; __align_cpy_2; __align_cpy_4; + __align_cpy_8; __align_cpy_16; + } +} +libm { + GLIBC_2.1 { + # A generic bug got this omitted from other configurations' version + # sets, but we always had it. + exp2l; + } +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/add_n.S b/REORG.TODO/sysdeps/sparc/sparc64/add_n.S new file mode 100644 index 0000000000..e7f7c46c42 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/add_n.S @@ -0,0 +1,57 @@ +/* SPARC v9 __mpn_add_n -- Add two limb vectors of the same length > 0 and + store sum in a third limb vector. + + Copyright (C) 1995-2017 Free Software Foundation, Inc. + + This file is part of the GNU MP Library. + + The GNU MP Library is free software; you can redistribute it and/or modify + it under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation; either version 2.1 of the License, or (at your + option) any later version. + + The GNU MP Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with the GNU MP Library; see the file COPYING.LIB. If not, + see <http://www.gnu.org/licenses/>. */ + + +#include <sysdep.h> + + +/* INPUT PARAMETERS + res_ptr %o0 + s1_ptr %o1 + s2_ptr %o2 + size %o3 */ + + +ENTRY(__mpn_add_n) + + sub %g0,%o3,%g5 + sllx %o3,3,%g1 + add %o1,%g1,%o1 ! make s1_ptr point at end + add %o2,%g1,%o2 ! make s2_ptr point at end + add %o0,%g1,%o0 ! make res_ptr point at end + mov 0,%o4 ! clear carry variable + sllx %g5,3,%o5 ! compute initial address index + +1: ldx [%o2+%o5],%g1 ! load s2 limb + add %g5,1,%g5 ! increment loop count + ldx [%o1+%o5],%o3 ! load s1 limb + addcc %g1,%o4,%g1 ! add s2 limb and carry variable + movcc %xcc,0,%o4 ! if carry-out, o4 was 1; clear it + addcc %g1,%o3,%g1 ! add s1 limb to sum + stx %g1,[%o0+%o5] ! store result + add %o5,8,%o5 ! increment address index + brnz,pt %g5,1b + movcs %xcc,1,%o4 ! if s1 add gave carry, record it + + retl + mov %o4,%o0 + +END(__mpn_add_n) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/addmul_1.S b/REORG.TODO/sysdeps/sparc/sparc64/addmul_1.S new file mode 100644 index 0000000000..96450cc4c8 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/addmul_1.S @@ -0,0 +1,83 @@ +/* SPARC v9 __mpn_addmul_1 -- Multiply a limb vector with a single limb and + add the product to a second limb vector. + + Copyright (C) 1996-2017 Free Software Foundation, Inc. + + This file is part of the GNU MP Library. + + The GNU MP Library is free software; you can redistribute it and/or modify + it under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation; either version 2.1 of the License, or (at your + option) any later version. + + The GNU MP Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with the GNU MP Library; see the file COPYING.LIB. If not, + see <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + +/* INPUT PARAMETERS + res_ptr o0 + s1_ptr o1 + size o2 + s2_limb o3 */ + + +ENTRY(__mpn_addmul_1) + save %sp,-192,%sp + + sub %g0,%i2,%o7 + mov 0,%o0 ! zero cy_limb + sllx %o7,3,%o7 + sethi %hi(0x80000000),%o2 + srl %i3,0,%o1 ! extract low 32 bits of s2_limb + sub %i1,%o7,%o3 + srlx %i3,32,%i3 ! extract high 32 bits of s2_limb + sub %i0,%o7,%o4 + add %o2,%o2,%o2 ! o2 = 0x100000000 + + ! hi ! + ! mid-1 ! + ! mid-2 ! + ! lo ! +1: + ldx [%o3+%o7],%g5 + srl %g5,0,%i0 ! zero hi bits + ldx [%o4+%o7],%l1 + srlx %g5,32,%g5 + mulx %o1,%i0,%i4 ! lo product + mulx %i3,%i0,%i1 ! mid-1 product + mulx %o1,%g5,%l2 ! mid-2 product + mulx %i3,%g5,%i5 ! hi product + srlx %i4,32,%i0 ! extract high 32 bits of lo product... + add %i1,%i0,%i1 ! ...and add it to the mid-1 product + addcc %i1,%l2,%i1 ! add mid products + mov 0,%l0 ! we need the carry from that add... + movcs %xcc,%o2,%l0 ! ...compute it and... + sllx %i1,32,%i0 ! align low bits of mid product + add %i5,%l0,%i5 ! ...add to bit 32 of the hi product + srl %i4,0,%g5 ! zero high 32 bits of lo product + add %i0,%g5,%i0 ! combine into low 64 bits of result + srlx %i1,32,%i1 ! extract high bits of mid product... + addcc %i0,%o0,%i0 ! add cy_limb to low 64 bits of result + add %i5,%i1,%i1 ! ...and add them to the high result + mov 0,%g5 + movcs %xcc,1,%g5 + addcc %l1,%i0,%i0 + stx %i0,[%o4+%o7] + add %g5,1,%l1 + movcs %xcc,%l1,%g5 + addcc %o7,8,%o7 + bne,pt %xcc,1b + add %i1,%g5,%o0 ! compute new cy_limb + + jmpl %i7+8, %g0 + restore %o0,%g0,%o0 + +END(__mpn_addmul_1) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/align-cpy.S b/REORG.TODO/sysdeps/sparc/sparc64/align-cpy.S new file mode 100644 index 0000000000..e36799a405 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/align-cpy.S @@ -0,0 +1,84 @@ +/* Aligned copy routines specified by Sparc V9 ABI. + For 64-bit sparc. + Copyright (C) 2010-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller (davem@davemloft.net) + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .text + .align 8 +ENTRY(__align_cpy_8) +10: cmp %o0, %o1 + be,pn %xcc, 9f + mov %o0, %o3 + subcc %o2, 0x08, %o2 + be,pn %xcc, 8f +1: ldx [%o1 + 0x00], %o5 + ldx [%o1 + 0x08], %o4 + subcc %o2, 0x10, %o2 + add %o1, 0x10, %o1 + stx %o5, [%o3 + 0x00] + stx %o4, [%o3 + 0x08] + bg,pt %xcc, 1b + add %o3, 0x10, %o3 + bne,pn %xcc, 9f + nop + ldx [%o1 + 0x00], %o5 +8: stx %o5, [%o3 + 0x00] +9: retl + nop +END(__align_cpy_8) + + .align 8 +ENTRY(__align_cpy_4) +20: cmp %o0, %o1 + be,pn %xcc, 9f + mov %o0, %o3 + subcc %o2, 0x04, %o2 + be,pn %xcc, 8f +1: lduw [%o1 + 0x00], %o5 + lduw [%o1 + 0x04], %o4 + subcc %o2, 0x08, %o2 + add %o1, 0x08, %o1 + stw %o5, [%o3 + 0x00] + stw %o4, [%o3 + 0x04] + bg,pt %xcc, 1b + add %o3, 0x08, %o3 + bne,pn %xcc, 9f + nop + lduw [%o1 + 0x00], %o5 +8: stw %o5, [%o3 + 0x00] +9: retl + nop +END(__align_cpy_4) + + .align 8 +ENTRY(__align_cpy_2) + or %o0, %o1, %o3 + or %o2, %o3, %o3 + andcc %o3, 0x7, %g0 + be,pt %xcc, 10b + andcc %o3, 0x3, %g0 + be,pt %xcc, 20b + mov %o7, %g1 + call HIDDEN_JUMPTARGET(memcpy) + mov %o7, %g1 +END(__align_cpy_2) + +weak_alias (__align_cpy_8, __align_cpy_16) +weak_alias (__align_cpy_2, __align_cpy_1) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/atomic-machine.h b/REORG.TODO/sysdeps/sparc/sparc64/atomic-machine.h new file mode 100644 index 0000000000..72009329c3 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/atomic-machine.h @@ -0,0 +1,129 @@ +/* Atomic operations. sparc64 version. + Copyright (C) 2003-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jakub@redhat.com>, 2003. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <stdint.h> + +typedef int8_t atomic8_t; +typedef uint8_t uatomic8_t; +typedef int_fast8_t atomic_fast8_t; +typedef uint_fast8_t uatomic_fast8_t; + +typedef int16_t atomic16_t; +typedef uint16_t uatomic16_t; +typedef int_fast16_t atomic_fast16_t; +typedef uint_fast16_t uatomic_fast16_t; + +typedef int32_t atomic32_t; +typedef uint32_t uatomic32_t; +typedef int_fast32_t atomic_fast32_t; +typedef uint_fast32_t uatomic_fast32_t; + +typedef int64_t atomic64_t; +typedef uint64_t uatomic64_t; +typedef int_fast64_t atomic_fast64_t; +typedef uint_fast64_t uatomic_fast64_t; + +typedef intptr_t atomicptr_t; +typedef uintptr_t uatomicptr_t; +typedef intmax_t atomic_max_t; +typedef uintmax_t uatomic_max_t; + +#define __HAVE_64B_ATOMICS 1 +#define USE_ATOMIC_COMPILER_BUILTINS 0 + +/* XXX Is this actually correct? */ +#define ATOMIC_EXCHANGE_USES_CAS 1 + + +#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \ + (abort (), (__typeof (*mem)) 0) + +#define __arch_compare_and_exchange_val_16_acq(mem, newval, oldval) \ + (abort (), (__typeof (*mem)) 0) + +#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \ +({ \ + __typeof (*(mem)) __acev_tmp; \ + __typeof (mem) __acev_mem = (mem); \ + if (__builtin_constant_p (oldval) && (oldval) == 0) \ + __asm __volatile ("cas [%3], %%g0, %0" \ + : "=r" (__acev_tmp), "=m" (*__acev_mem) \ + : "m" (*__acev_mem), "r" (__acev_mem), \ + "0" (newval) : "memory"); \ + else \ + __asm __volatile ("cas [%4], %2, %0" \ + : "=r" (__acev_tmp), "=m" (*__acev_mem) \ + : "r" (oldval), "m" (*__acev_mem), "r" (__acev_mem), \ + "0" (newval) : "memory"); \ + __acev_tmp; }) + +#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \ +({ \ + __typeof (*(mem)) __acev_tmp; \ + __typeof (mem) __acev_mem = (mem); \ + if (__builtin_constant_p (oldval) && (oldval) == 0) \ + __asm __volatile ("casx [%3], %%g0, %0" \ + : "=r" (__acev_tmp), "=m" (*__acev_mem) \ + : "m" (*__acev_mem), "r" (__acev_mem), \ + "0" ((long) (newval)) : "memory"); \ + else \ + __asm __volatile ("casx [%4], %2, %0" \ + : "=r" (__acev_tmp), "=m" (*__acev_mem) \ + : "r" ((long) (oldval)), "m" (*__acev_mem), \ + "r" (__acev_mem), "0" ((long) (newval)) : "memory"); \ + __acev_tmp; }) + +#define atomic_exchange_acq(mem, newvalue) \ + ({ __typeof (*(mem)) __oldval, __val; \ + __typeof (mem) __memp = (mem); \ + __typeof (*(mem)) __value = (newvalue); \ + \ + if (sizeof (*(mem)) == 4) \ + __asm ("swap %0, %1" \ + : "=m" (*__memp), "=r" (__oldval) \ + : "m" (*__memp), "1" (__value) : "memory"); \ + else \ + { \ + __val = *__memp; \ + do \ + { \ + __oldval = __val; \ + __val = atomic_compare_and_exchange_val_acq (__memp, __value, \ + __oldval); \ + } \ + while (__builtin_expect (__val != __oldval, 0)); \ + } \ + __oldval; }) + +#define atomic_compare_and_exchange_val_24_acq(mem, newval, oldval) \ + atomic_compare_and_exchange_val_acq (mem, newval, oldval) + +#define atomic_exchange_24_rel(mem, newval) \ + atomic_exchange_rel (mem, newval) + +#define atomic_full_barrier() \ + __asm __volatile ("membar #LoadLoad | #LoadStore" \ + " | #StoreLoad | #StoreStore" : : : "memory") +#define atomic_read_barrier() \ + __asm __volatile ("membar #LoadLoad | #LoadStore" : : : "memory") +#define atomic_write_barrier() \ + __asm __volatile ("membar #LoadStore | #StoreStore" : : : "memory") + +extern void __cpu_relax (void); +#define atomic_spin_nop() __cpu_relax () diff --git a/REORG.TODO/sysdeps/sparc/sparc64/backtrace.h b/REORG.TODO/sysdeps/sparc/sparc64/backtrace.h new file mode 100644 index 0000000000..b9c95c51cf --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/backtrace.h @@ -0,0 +1,7 @@ +/* Private macros for guiding the backtrace implementation, sparc64 + version. */ + +#define backtrace_flush_register_windows() \ + asm volatile ("flushw") + +#define BACKTRACE_STACK_BIAS STACK_BIAS diff --git a/REORG.TODO/sysdeps/sparc/sparc64/bits/wordsize.h b/REORG.TODO/sysdeps/sparc/sparc64/bits/wordsize.h new file mode 100644 index 0000000000..2f66f10d72 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/bits/wordsize.h @@ -0,0 +1,11 @@ +/* Determine the wordsize from the preprocessor defines. */ + +#if defined __arch64__ || defined __sparcv9 +# define __WORDSIZE 64 +# define __WORDSIZE_TIME64_COMPAT32 1 +#else +# define __WORDSIZE 32 +# define __WORDSIZE_TIME64_COMPAT32 0 +# define __WORDSIZE32_SIZE_ULONG 0 +# define __WORDSIZE32_PTRDIFF_LONG 0 +#endif diff --git a/REORG.TODO/sysdeps/sparc/sparc64/bzero.c b/REORG.TODO/sysdeps/sparc/sparc64/bzero.c new file mode 100644 index 0000000000..37f0f6f993 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/bzero.c @@ -0,0 +1 @@ +/* bzero is in memset.S */ diff --git a/REORG.TODO/sysdeps/sparc/sparc64/cpu_relax.S b/REORG.TODO/sysdeps/sparc/sparc64/cpu_relax.S new file mode 100644 index 0000000000..5271164607 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/cpu_relax.S @@ -0,0 +1,67 @@ +/* CPU strand yielding for busy loops. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + Contributed by David S. Miller (davem@davemloft.net) + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .text +__cpu_relax_generic: + rd %ccr, %g0 + rd %ccr, %g0 + rd %ccr, %g0 + retl + nop + .size __cpu_relax_generic,.-__cpu_relax_generic + +__cpu_relax_pause: + wr %g0, 128, %asr27 + retl + nop + .size __cpu_relax_pause,.-__cpu_relax_pause + +ENTRY(__cpu_relax) + .type __cpu_relax, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif + set HWCAP_SPARC_PAUSE, %o1 + andcc %o0, %o1, %g0 + be 1f + nop +# ifdef SHARED + sethi %gdop_hix22(__cpu_relax_pause), %o1 + xor %o1, %gdop_lox10(__cpu_relax_pause), %o1 +# else + set __cpu_relax_pause, %o1 +# endif + ba 10f + nop +1: +# ifdef SHARED + sethi %gdop_hix22(__cpu_relax_generic), %o1 + xor %o1, %gdop_lox10(__cpu_relax_generic), %o1 +# else + set __cpu_relax_generic, %o1 +# endif +10: +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__cpu_relax) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/dl-irel.h b/REORG.TODO/sysdeps/sparc/sparc64/dl-irel.h new file mode 100644 index 0000000000..dfd4637557 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/dl-irel.h @@ -0,0 +1,65 @@ +/* Machine-dependent ELF indirect relocation inline functions. + SPARC 64-bit version. + Copyright (C) 2010-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _DL_IREL_H +#define _DL_IREL_H + +#include <stdio.h> +#include <unistd.h> +#include <dl-plt.h> +#include <ldsodefs.h> + +#define ELF_MACHINE_IRELA 1 + +static inline Elf64_Addr +__attribute ((always_inline)) +elf_ifunc_invoke (Elf64_Addr addr) +{ + return ((Elf64_Addr (*) (int)) (addr)) (GLRO(dl_hwcap)); +} + +static inline void +__attribute ((always_inline)) +elf_irela (const Elf64_Rela *reloc) +{ + unsigned int r_type = (reloc->r_info & 0xff); + + if (__glibc_likely (r_type == R_SPARC_IRELATIVE)) + { + Elf64_Addr *const reloc_addr = (void *) reloc->r_offset; + Elf64_Addr value = elf_ifunc_invoke(reloc->r_addend); + *reloc_addr = value; + } + else if (__glibc_likely (r_type == R_SPARC_JMP_IREL)) + { + Elf64_Addr *const reloc_addr = (void *) reloc->r_offset; + Elf64_Addr value = elf_ifunc_invoke(reloc->r_addend); + struct link_map map = { .l_addr = 0 }; + + /* 'high' is always zero, for large PLT entries the linker + emits an R_SPARC_IRELATIVE. */ + sparc64_fixup_plt (&map, reloc, reloc_addr, value, 0, 0); + } + else if (r_type == R_SPARC_NONE) + ; + else + __libc_fatal ("unexpected reloc type in static binary"); +} + +#endif /* dl-irel.h */ diff --git a/REORG.TODO/sysdeps/sparc/sparc64/dl-machine.h b/REORG.TODO/sysdeps/sparc/sparc64/dl-machine.h new file mode 100644 index 0000000000..1b59d78a25 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/dl-machine.h @@ -0,0 +1,685 @@ +/* Machine-dependent ELF dynamic relocation inline functions. Sparc64 version. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef dl_machine_h +#define dl_machine_h + +#define ELF_MACHINE_NAME "sparc64" + +#include <string.h> +#include <sys/param.h> +#include <ldsodefs.h> +#include <sysdep.h> +#include <dl-plt.h> + +#define ELF64_R_TYPE_ID(info) ((info) & 0xff) +#define ELF64_R_TYPE_DATA(info) ((info) >> 8) + +/* Return nonzero iff ELF header is compatible with the running host. */ +static inline int +elf_machine_matches_host (const Elf64_Ehdr *ehdr) +{ + return ehdr->e_machine == EM_SPARCV9; +} + +/* We have to do this because elf_machine_{dynamic,load_address} can be + invoked from functions that have no GOT references, and thus the compiler + has no obligation to load the PIC register. */ +#define LOAD_PIC_REG(PIC_REG) \ +do { Elf64_Addr tmp; \ + __asm("sethi %%hi(_GLOBAL_OFFSET_TABLE_-4), %1\n\t" \ + "rd %%pc, %0\n\t" \ + "add %1, %%lo(_GLOBAL_OFFSET_TABLE_+4), %1\n\t" \ + "add %0, %1, %0" \ + : "=r" (PIC_REG), "=r" (tmp)); \ +} while (0) + +/* Return the link-time address of _DYNAMIC. Conveniently, this is the + first element of the GOT. This must be inlined in a function which + uses global data. */ +static inline Elf64_Addr +elf_machine_dynamic (void) +{ + register Elf64_Addr *elf_pic_register __asm__("%l7"); + + LOAD_PIC_REG (elf_pic_register); + + return *elf_pic_register; +} + +/* Return the run-time load address of the shared object. */ +static inline Elf64_Addr +elf_machine_load_address (void) +{ + register Elf32_Addr *pc __asm ("%o7"); + register Elf64_Addr *got __asm ("%l7"); + + __asm ("sethi %%hi(_GLOBAL_OFFSET_TABLE_-4), %1\n\t" + "call 1f\n\t" + " add %1, %%lo(_GLOBAL_OFFSET_TABLE_+4), %1\n\t" + "call _DYNAMIC\n\t" + "call _GLOBAL_OFFSET_TABLE_\n" + "1:\tadd %1, %0, %1\n\t" : "=r" (pc), "=r" (got)); + + /* got is now l_addr + _GLOBAL_OFFSET_TABLE_ + *got is _DYNAMIC + pc[2]*4 is l_addr + _DYNAMIC - (long)pc - 8 + pc[3]*4 is l_addr + _GLOBAL_OFFSET_TABLE_ - (long)pc - 12 */ + return (Elf64_Addr) got - *got + (Elf32_Sword) ((pc[2] - pc[3]) * 4) - 4; +} + +static inline Elf64_Addr __attribute__ ((always_inline)) +elf_machine_fixup_plt (struct link_map *map, lookup_t t, + const Elf64_Rela *reloc, + Elf64_Addr *reloc_addr, Elf64_Addr value) +{ + sparc64_fixup_plt (map, reloc, reloc_addr, value + reloc->r_addend, + reloc->r_addend, 1); + return value; +} + +/* Return the final value of a plt relocation. */ +static inline Elf64_Addr +elf_machine_plt_value (struct link_map *map, const Elf64_Rela *reloc, + Elf64_Addr value) +{ + /* Don't add addend here, but in elf_machine_fixup_plt instead. + value + reloc->r_addend is the value which should actually be + stored into .plt data slot. */ + return value; +} + +/* ELF_RTYPE_CLASS_PLT iff TYPE describes relocation of a PLT entry, so + PLT entries should not be allowed to define the value. + ELF_RTYPE_CLASS_COPY iff TYPE should not be allowed to resolve to one + of the main executable's symbols, as for a COPY reloc. */ +#define elf_machine_type_class(type) \ + ((((type) == R_SPARC_JMP_SLOT \ + || ((type) >= R_SPARC_TLS_GD_HI22 && (type) <= R_SPARC_TLS_TPOFF64)) \ + * ELF_RTYPE_CLASS_PLT) \ + | (((type) == R_SPARC_COPY) * ELF_RTYPE_CLASS_COPY)) + +/* A reloc type used for ld.so cmdline arg lookups to reject PLT entries. */ +#define ELF_MACHINE_JMP_SLOT R_SPARC_JMP_SLOT + +/* The SPARC never uses Elf64_Rel relocations. */ +#define ELF_MACHINE_NO_REL 1 +#define ELF_MACHINE_NO_RELA 0 + +/* Set up the loaded object described by L so its unrelocated PLT + entries will jump to the on-demand fixup code in dl-runtime.c. */ + +static inline int +elf_machine_runtime_setup (struct link_map *l, int lazy, int profile) +{ + if (l->l_info[DT_JMPREL] && lazy) + { + extern void _dl_runtime_resolve_0 (void); + extern void _dl_runtime_resolve_1 (void); + extern void _dl_runtime_profile_0 (void); + extern void _dl_runtime_profile_1 (void); + Elf64_Addr res0_addr, res1_addr; + unsigned int *plt = (void *) D_PTR (l, l_info[DT_PLTGOT]); + + if (__builtin_expect(profile, 0)) + { + res0_addr = (Elf64_Addr) &_dl_runtime_profile_0; + res1_addr = (Elf64_Addr) &_dl_runtime_profile_1; + + if (GLRO(dl_profile) != NULL + && _dl_name_match_p (GLRO(dl_profile), l)) + GL(dl_profile_map) = l; + } + else + { + res0_addr = (Elf64_Addr) &_dl_runtime_resolve_0; + res1_addr = (Elf64_Addr) &_dl_runtime_resolve_1; + } + + /* PLT0 looks like: + + sethi %uhi(_dl_runtime_{resolve,profile}_0), %g4 + sethi %hi(_dl_runtime_{resolve,profile}_0), %g5 + or %g4, %ulo(_dl_runtime_{resolve,profile}_0), %g4 + or %g5, %lo(_dl_runtime_{resolve,profile}_0), %g5 + sllx %g4, 32, %g4 + add %g4, %g5, %g5 + jmpl %g5, %g4 + nop + */ + + plt[0] = 0x09000000 | (res0_addr >> (64 - 22)); + plt[1] = 0x0b000000 | ((res0_addr >> 10) & 0x003fffff); + plt[2] = 0x88112000 | ((res0_addr >> 32) & 0x3ff); + plt[3] = 0x8a116000 | (res0_addr & 0x3ff); + plt[4] = 0x89293020; + plt[5] = 0x8a010005; + plt[6] = 0x89c14000; + plt[7] = 0x01000000; + + /* PLT1 looks like: + + sethi %uhi(_dl_runtime_{resolve,profile}_1), %g4 + sethi %hi(_dl_runtime_{resolve,profile}_1), %g5 + or %g4, %ulo(_dl_runtime_{resolve,profile}_1), %g4 + or %g5, %lo(_dl_runtime_{resolve,profile}_1), %g5 + sllx %g4, 32, %g4 + add %g4, %g5, %g5 + jmpl %g5, %g4 + nop + */ + + plt[8] = 0x09000000 | (res1_addr >> (64 - 22)); + plt[9] = 0x0b000000 | ((res1_addr >> 10) & 0x003fffff); + plt[10] = 0x88112000 | ((res1_addr >> 32) & 0x3ff); + plt[11] = 0x8a116000 | (res1_addr & 0x3ff); + plt[12] = 0x89293020; + plt[13] = 0x8a010005; + plt[14] = 0x89c14000; + plt[15] = 0x01000000; + + /* Now put the magic cookie at the beginning of .PLT2 + Entry .PLT3 is unused by this implementation. */ + *((struct link_map **)(&plt[16])) = l; + + if (__builtin_expect (l->l_info[VALIDX(DT_GNU_PRELINKED)] != NULL, 0) + || __builtin_expect (l->l_info [VALIDX (DT_GNU_LIBLISTSZ)] != NULL, 0)) + { + /* Need to reinitialize .plt to undo prelinking. */ + Elf64_Rela *rela = (Elf64_Rela *) D_PTR (l, l_info[DT_JMPREL]); + Elf64_Rela *relaend + = (Elf64_Rela *) ((char *) rela + + l->l_info[DT_PLTRELSZ]->d_un.d_val); + + /* prelink must ensure there are no R_SPARC_NONE relocs left + in .rela.plt. */ + while (rela < relaend) + { + if (__builtin_expect (rela->r_addend, 0) != 0) + { + Elf64_Addr slot = ((rela->r_offset + l->l_addr + 0x400 + - (Elf64_Addr) plt) + / 0x1400) * 0x1400 + + (Elf64_Addr) plt - 0x400; + /* ldx [%o7 + X], %g1 */ + unsigned int first_ldx = *(unsigned int *)(slot + 12); + Elf64_Addr ptr = slot + (first_ldx & 0xfff) + 4; + + *(Elf64_Addr *) (rela->r_offset + l->l_addr) + = (Elf64_Addr) plt + - (slot + ((rela->r_offset + l->l_addr - ptr) / 8) * 24 + + 4); + ++rela; + continue; + } + + *(unsigned int *) (rela->r_offset + l->l_addr) + = 0x03000000 | (rela->r_offset + l->l_addr - (Elf64_Addr) plt); + *(unsigned int *) (rela->r_offset + l->l_addr + 4) + = 0x30680000 | ((((Elf64_Addr) plt + 32 - rela->r_offset + - l->l_addr - 4) >> 2) & 0x7ffff); + __asm __volatile ("flush %0" : : "r" (rela->r_offset + + l->l_addr)); + __asm __volatile ("flush %0+4" : : "r" (rela->r_offset + + l->l_addr)); + ++rela; + } + } + } + + return lazy; +} + +/* The PLT uses Elf64_Rela relocs. */ +#define elf_machine_relplt elf_machine_rela + +/* Undo the sub %sp, 6*8, %sp; add %sp, STACK_BIAS + 22*8, %o0 below + (but w/o STACK_BIAS) to get at the value we want in __libc_stack_end. */ +#define DL_STACK_END(cookie) \ + ((void *) (((long) (cookie)) - (22 - 6) * 8)) + +/* Initial entry point code for the dynamic linker. + The C function `_dl_start' is the real entry point; + its return value is the user program's entry point. */ + +#define RTLD_GOT_ADDRESS(pic_reg, reg, symbol) \ + "sethi %gdop_hix22(" #symbol "), " #reg "\n\t" \ + "xor " #reg ", %gdop_lox10(" #symbol "), " #reg "\n\t" \ + "ldx [" #pic_reg " + " #reg "], " #reg ", %gdop(" #symbol ")\n" + +#define __S1(x) #x +#define __S(x) __S1(x) + +#define RTLD_START __asm__ ( "\n" \ +" .text\n" \ +" .global _start\n" \ +" .type _start, @function\n" \ +" .align 32\n" \ +"_start:\n" \ +" /* Make room for functions to drop their arguments on the stack. */\n" \ +" sub %sp, 6*8, %sp\n" \ +" /* Pass pointer to argument block to _dl_start. */\n" \ +" call _dl_start\n" \ +" add %sp," __S(STACK_BIAS) "+22*8,%o0\n" \ +" /* FALLTHRU */\n" \ +" .size _start, .-_start\n" \ +"\n" \ +" .global _dl_start_user\n" \ +" .type _dl_start_user, @function\n" \ +"_dl_start_user:\n" \ +" /* Load the GOT register. */\n" \ +"1: call 11f\n" \ +" sethi %hi(_GLOBAL_OFFSET_TABLE_-(1b-.)), %l7\n" \ +"11: or %l7, %lo(_GLOBAL_OFFSET_TABLE_-(1b-.)), %l7\n" \ +" add %l7, %o7, %l7\n" \ +" /* Save the user entry point address in %l0. */\n" \ +" mov %o0, %l0\n" \ +" /* See if we were run as a command with the executable file name as an\n" \ +" extra leading argument. If so, we must shift things around since we\n" \ +" must keep the stack doubleword aligned. */\n" \ + RTLD_GOT_ADDRESS(%l7, %g5, _dl_skip_args) \ +" ld [%g5], %i0\n" \ +" brz,pt %i0, 2f\n" \ +" ldx [%sp + " __S(STACK_BIAS) " + 22*8], %i5\n" \ +" /* Find out how far to shift. */\n" \ +" sub %i5, %i0, %i5\n" \ +" sllx %i0, 3, %l6\n" \ + RTLD_GOT_ADDRESS(%l7, %l4, _dl_argv) \ +" stx %i5, [%sp + " __S(STACK_BIAS) " + 22*8]\n" \ +" add %sp, " __S(STACK_BIAS) " + 23*8, %i1\n" \ +" add %i1, %l6, %i2\n" \ +" ldx [%l4], %l5\n" \ +" /* Copy down argv. */\n" \ +"12: ldx [%i2], %i3\n" \ +" add %i2, 8, %i2\n" \ +" stx %i3, [%i1]\n" \ +" brnz,pt %i3, 12b\n" \ +" add %i1, 8, %i1\n" \ +" sub %l5, %l6, %l5\n" \ +" /* Copy down envp. */\n" \ +"13: ldx [%i2], %i3\n" \ +" add %i2, 8, %i2\n" \ +" stx %i3, [%i1]\n" \ +" brnz,pt %i3, 13b\n" \ +" add %i1, 8, %i1\n" \ +" /* Copy down auxiliary table. */\n" \ +"14: ldx [%i2], %i3\n" \ +" ldx [%i2 + 8], %i4\n" \ +" add %i2, 16, %i2\n" \ +" stx %i3, [%i1]\n" \ +" stx %i4, [%i1 + 8]\n" \ +" brnz,pt %i3, 14b\n" \ +" add %i1, 16, %i1\n" \ +" stx %l5, [%l4]\n" \ +" /* %o0 = _dl_loaded, %o1 = argc, %o2 = argv, %o3 = envp. */\n" \ +"2:\t" RTLD_GOT_ADDRESS(%l7, %o0, _rtld_local) \ +" sllx %i5, 3, %o3\n" \ +" add %sp, " __S(STACK_BIAS) " + 23*8, %o2\n" \ +" add %o3, 8, %o3\n" \ +" mov %i5, %o1\n" \ +" add %o2, %o3, %o3\n" \ +" call _dl_init\n" \ +" ldx [%o0], %o0\n" \ +" /* Pass our finalizer function to the user in %g1. */\n" \ + RTLD_GOT_ADDRESS(%l7, %g1, _dl_fini) \ +" /* Jump to the user's entry point and deallocate the extra stack we got. */\n" \ +" jmp %l0\n" \ +" add %sp, 6*8, %sp\n" \ +" .size _dl_start_user, . - _dl_start_user\n" \ +" .previous\n"); + +#endif /* dl_machine_h */ + +#define ARCH_LA_PLTENTER sparc64_gnu_pltenter +#define ARCH_LA_PLTEXIT sparc64_gnu_pltexit + +#ifdef RESOLVE_MAP + +/* Perform the relocation specified by RELOC and SYM (which is fully resolved). + MAP is the object containing the reloc. */ + +auto inline void +__attribute__ ((always_inline)) +elf_machine_rela (struct link_map *map, const Elf64_Rela *reloc, + const Elf64_Sym *sym, const struct r_found_version *version, + void *const reloc_addr_arg, int skip_ifunc) +{ + Elf64_Addr *const reloc_addr = reloc_addr_arg; +#if !defined RTLD_BOOTSTRAP && !defined RESOLVE_CONFLICT_FIND_MAP + const Elf64_Sym *const refsym = sym; +#endif + Elf64_Addr value; + const unsigned long int r_type = ELF64_R_TYPE_ID (reloc->r_info); +#if !defined RESOLVE_CONFLICT_FIND_MAP + struct link_map *sym_map = NULL; +#endif + +#if !defined RTLD_BOOTSTRAP && !defined HAVE_Z_COMBRELOC + /* This is defined in rtld.c, but nowhere in the static libc.a; make the + reference weak so static programs can still link. This declaration + cannot be done when compiling rtld.c (i.e. #ifdef RTLD_BOOTSTRAP) + because rtld.c contains the common defn for _dl_rtld_map, which is + incompatible with a weak decl in the same file. */ + weak_extern (_dl_rtld_map); +#endif + + if (__glibc_unlikely (r_type == R_SPARC_NONE)) + return; + + if (__glibc_unlikely (r_type == R_SPARC_SIZE64)) + { + *reloc_addr = sym->st_size + reloc->r_addend; + return; + } + +#if !defined RTLD_BOOTSTRAP || !defined HAVE_Z_COMBRELOC + if (__glibc_unlikely (r_type == R_SPARC_RELATIVE)) + { +# if !defined RTLD_BOOTSTRAP && !defined HAVE_Z_COMBRELOC + if (map != &_dl_rtld_map) /* Already done in rtld itself. */ +# endif + *reloc_addr += map->l_addr + reloc->r_addend; + return; + } +#endif + +#ifndef RESOLVE_CONFLICT_FIND_MAP + if (__builtin_expect (ELF64_ST_BIND (sym->st_info) == STB_LOCAL, 0) + && sym->st_shndx != SHN_UNDEF) + { + value = map->l_addr; + } + else + { + sym_map = RESOLVE_MAP (&sym, version, r_type); + value = sym_map == NULL ? 0 : sym_map->l_addr + sym->st_value; + } +#else + value = 0; +#endif + + value += reloc->r_addend; /* Assume copy relocs have zero addend. */ + + if (sym != NULL + && __builtin_expect (ELFW(ST_TYPE) (sym->st_info) == STT_GNU_IFUNC, 0) + && __builtin_expect (sym->st_shndx != SHN_UNDEF, 1) + && __builtin_expect (!skip_ifunc, 1)) + value = ((Elf64_Addr (*) (int)) value) (GLRO(dl_hwcap)); + + switch (r_type) + { +#if !defined RTLD_BOOTSTRAP && !defined RESOLVE_CONFLICT_FIND_MAP + case R_SPARC_COPY: + if (sym == NULL) + /* This can happen in trace mode if an object could not be + found. */ + break; + if (sym->st_size > refsym->st_size + || (GLRO(dl_verbose) && sym->st_size < refsym->st_size)) + { + const char *strtab; + + strtab = (const void *) D_PTR (map, l_info[DT_STRTAB]); + _dl_error_printf ("\ +%s: Symbol `%s' has different size in shared object, consider re-linking\n", + RTLD_PROGNAME, strtab + refsym->st_name); + } + memcpy (reloc_addr_arg, (void *) value, + MIN (sym->st_size, refsym->st_size)); + break; +#endif + case R_SPARC_64: + case R_SPARC_GLOB_DAT: + *reloc_addr = value; + break; + case R_SPARC_IRELATIVE: + value = ((Elf64_Addr (*) (int)) value) (GLRO(dl_hwcap)); + *reloc_addr = value; + break; + case R_SPARC_JMP_IREL: + value = ((Elf64_Addr (*) (int)) value) (GLRO(dl_hwcap)); + /* 'high' is always zero, for large PLT entries the linker + emits an R_SPARC_IRELATIVE. */ +#ifdef RESOLVE_CONFLICT_FIND_MAP + sparc64_fixup_plt (NULL, reloc, reloc_addr, value, 0, 0); +#else + sparc64_fixup_plt (map, reloc, reloc_addr, value, 0, 0); +#endif + break; + case R_SPARC_JMP_SLOT: +#ifdef RESOLVE_CONFLICT_FIND_MAP + /* R_SPARC_JMP_SLOT conflicts against .plt[32768+] + relocs should be turned into R_SPARC_64 relocs + in .gnu.conflict section. + r_addend non-zero does not mean it is a .plt[32768+] + reloc, instead it is the actual address of the function + to call. */ + sparc64_fixup_plt (NULL, reloc, reloc_addr, value, 0, 0); +#else + sparc64_fixup_plt (map, reloc, reloc_addr, value, reloc->r_addend, 0); +#endif + break; +#ifndef RESOLVE_CONFLICT_FIND_MAP + case R_SPARC_TLS_DTPMOD64: + /* Get the information from the link map returned by the + resolv function. */ + if (sym_map != NULL) + *reloc_addr = sym_map->l_tls_modid; + break; + case R_SPARC_TLS_DTPOFF64: + /* During relocation all TLS symbols are defined and used. + Therefore the offset is already correct. */ + *reloc_addr = (sym == NULL ? 0 : sym->st_value) + reloc->r_addend; + break; + case R_SPARC_TLS_TPOFF64: + /* The offset is negative, forward from the thread pointer. */ + /* We know the offset of object the symbol is contained in. + It is a negative value which will be added to the + thread pointer. */ + if (sym != NULL) + { + CHECK_STATIC_TLS (map, sym_map); + *reloc_addr = sym->st_value - sym_map->l_tls_offset + + reloc->r_addend; + } + break; +# ifndef RTLD_BOOTSTRAP + case R_SPARC_TLS_LE_HIX22: + case R_SPARC_TLS_LE_LOX10: + if (sym != NULL) + { + CHECK_STATIC_TLS (map, sym_map); + value = sym->st_value - sym_map->l_tls_offset + + reloc->r_addend; + if (r_type == R_SPARC_TLS_LE_HIX22) + *(unsigned int *)reloc_addr = + ((*(unsigned int *)reloc_addr & 0xffc00000) + | (((~value) >> 10) & 0x3fffff)); + else + *(unsigned int *)reloc_addr = + ((*(unsigned int *)reloc_addr & 0xffffe000) | (value & 0x3ff) + | 0x1c00); + } + break; +# endif +#endif +#ifndef RTLD_BOOTSTRAP + case R_SPARC_8: + *(char *) reloc_addr = value; + break; + case R_SPARC_16: + *(short *) reloc_addr = value; + break; + case R_SPARC_32: + *(unsigned int *) reloc_addr = value; + break; + case R_SPARC_DISP8: + *(char *) reloc_addr = (value - (Elf64_Addr) reloc_addr); + break; + case R_SPARC_DISP16: + *(short *) reloc_addr = (value - (Elf64_Addr) reloc_addr); + break; + case R_SPARC_DISP32: + *(unsigned int *) reloc_addr = (value - (Elf64_Addr) reloc_addr); + break; + case R_SPARC_DISP64: + *reloc_addr = (value - (Elf64_Addr) reloc_addr); + break; + case R_SPARC_REGISTER: + *reloc_addr = value; + break; + case R_SPARC_WDISP30: + *(unsigned int *) reloc_addr = + ((*(unsigned int *)reloc_addr & 0xc0000000) | + (((value - (Elf64_Addr) reloc_addr) >> 2) & 0x3fffffff)); + break; + + /* MEDLOW code model relocs */ + case R_SPARC_LO10: + *(unsigned int *) reloc_addr = + ((*(unsigned int *)reloc_addr & ~0x3ff) | + (value & 0x3ff)); + break; + case R_SPARC_HI22: + *(unsigned int *) reloc_addr = + ((*(unsigned int *)reloc_addr & 0xffc00000) | + ((value >> 10) & 0x3fffff)); + break; + case R_SPARC_OLO10: + *(unsigned int *) reloc_addr = + ((*(unsigned int *)reloc_addr & ~0x1fff) | + (((value & 0x3ff) + ELF64_R_TYPE_DATA (reloc->r_info)) & 0x1fff)); + break; + + /* ABS34 code model reloc */ + case R_SPARC_H34: + *(unsigned int *) reloc_addr = + ((*(unsigned int *)reloc_addr & 0xffc00000) | + ((value >> 12) & 0x3fffff)); + + /* MEDMID code model relocs */ + case R_SPARC_H44: + *(unsigned int *) reloc_addr = + ((*(unsigned int *)reloc_addr & 0xffc00000) | + ((value >> 22) & 0x3fffff)); + break; + case R_SPARC_M44: + *(unsigned int *) reloc_addr = + ((*(unsigned int *)reloc_addr & ~0x3ff) | + ((value >> 12) & 0x3ff)); + break; + case R_SPARC_L44: + *(unsigned int *) reloc_addr = + ((*(unsigned int *)reloc_addr & ~0xfff) | + (value & 0xfff)); + break; + + /* MEDANY code model relocs */ + case R_SPARC_HH22: + *(unsigned int *) reloc_addr = + ((*(unsigned int *)reloc_addr & 0xffc00000) | + (value >> 42)); + break; + case R_SPARC_HM10: + *(unsigned int *) reloc_addr = + ((*(unsigned int *)reloc_addr & ~0x3ff) | + ((value >> 32) & 0x3ff)); + break; + case R_SPARC_LM22: + *(unsigned int *) reloc_addr = + ((*(unsigned int *)reloc_addr & 0xffc00000) | + ((value >> 10) & 0x003fffff)); + break; + case R_SPARC_UA16: + ((unsigned char *) reloc_addr_arg) [0] = value >> 8; + ((unsigned char *) reloc_addr_arg) [1] = value; + break; + case R_SPARC_UA32: + ((unsigned char *) reloc_addr_arg) [0] = value >> 24; + ((unsigned char *) reloc_addr_arg) [1] = value >> 16; + ((unsigned char *) reloc_addr_arg) [2] = value >> 8; + ((unsigned char *) reloc_addr_arg) [3] = value; + break; + case R_SPARC_UA64: + if (! ((long) reloc_addr_arg & 3)) + { + /* Common in .eh_frame */ + ((unsigned int *) reloc_addr_arg) [0] = value >> 32; + ((unsigned int *) reloc_addr_arg) [1] = value; + break; + } + ((unsigned char *) reloc_addr_arg) [0] = value >> 56; + ((unsigned char *) reloc_addr_arg) [1] = value >> 48; + ((unsigned char *) reloc_addr_arg) [2] = value >> 40; + ((unsigned char *) reloc_addr_arg) [3] = value >> 32; + ((unsigned char *) reloc_addr_arg) [4] = value >> 24; + ((unsigned char *) reloc_addr_arg) [5] = value >> 16; + ((unsigned char *) reloc_addr_arg) [6] = value >> 8; + ((unsigned char *) reloc_addr_arg) [7] = value; + break; +#endif +#if !defined RTLD_BOOTSTRAP || defined _NDEBUG + default: + _dl_reloc_bad_type (map, r_type, 0); + break; +#endif + } +} + +auto inline void +__attribute__ ((always_inline)) +elf_machine_rela_relative (Elf64_Addr l_addr, const Elf64_Rela *reloc, + void *const reloc_addr_arg) +{ + Elf64_Addr *const reloc_addr = reloc_addr_arg; + *reloc_addr = l_addr + reloc->r_addend; +} + +auto inline void +__attribute__ ((always_inline)) +elf_machine_lazy_rel (struct link_map *map, + Elf64_Addr l_addr, const Elf64_Rela *reloc, + int skip_ifunc) +{ + Elf64_Addr *const reloc_addr = (void *) (l_addr + reloc->r_offset); + const unsigned int r_type = ELF64_R_TYPE (reloc->r_info); + + if (__glibc_likely (r_type == R_SPARC_JMP_SLOT)) + ; + else if (r_type == R_SPARC_JMP_IREL + || r_type == R_SPARC_IRELATIVE) + { + Elf64_Addr value = map->l_addr + reloc->r_addend; + if (__glibc_likely (!skip_ifunc)) + value = ((Elf64_Addr (*) (int)) value) (GLRO(dl_hwcap)); + if (r_type == R_SPARC_JMP_IREL) + { + /* 'high' is always zero, for large PLT entries the linker + emits an R_SPARC_IRELATIVE. */ + sparc64_fixup_plt (map, reloc, reloc_addr, value, 0, 1); + } + else + *reloc_addr = value; + } + else if (r_type == R_SPARC_NONE) + ; + else + _dl_reloc_bad_type (map, r_type, 1); +} + +#endif /* RESOLVE_MAP */ diff --git a/REORG.TODO/sysdeps/sparc/sparc64/dl-plt.h b/REORG.TODO/sysdeps/sparc/sparc64/dl-plt.h new file mode 100644 index 0000000000..daad1063b3 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/dl-plt.h @@ -0,0 +1,167 @@ +/* PLT fixups. Sparc 64-bit version. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _DL_PLT_H +#define _DL_PLT_H + +/* We have 4 cases to handle. And we code different code sequences + for each one. I love V9 code models... */ +static inline void __attribute__ ((always_inline)) +sparc64_fixup_plt (struct link_map *map, const Elf64_Rela *reloc, + Elf64_Addr *reloc_addr, Elf64_Addr value, + Elf64_Addr high, int t) +{ + unsigned int *insns = (unsigned int *) reloc_addr; + Elf64_Addr plt_vaddr = (Elf64_Addr) reloc_addr; + Elf64_Sxword disp = value - plt_vaddr; + + /* 't' is '0' if we are resolving this PLT entry for RTLD bootstrap, + in which case we'll be resolving all PLT entries and thus can + optimize by overwriting instructions starting at the first PLT entry + instruction and we need not be mindful of thread safety. + + Otherwise, 't' is '1'. + + Now move plt_vaddr up to the call instruction. */ + plt_vaddr += ((t + 1) * 4); + + /* PLT entries .PLT32768 and above look always the same. */ + if (__builtin_expect (high, 0) != 0) + { + *reloc_addr = value - map->l_addr; + } + /* Near destination. */ + else if (disp >= -0x800000 && disp < 0x800000) + { + unsigned int insn; + + /* ba,a */ + insn = 0x30800000 | ((disp >> 2) & 0x3fffff); + + if (disp >= -0x100000 && disp < 0x100000) + { + /* ba,a,pt %icc */ + insn = 0x30480000 | ((disp >> 2) & 0x07ffff); + } + + /* As this is just one instruction, it is thread safe and so we + can avoid the unnecessary sethi FOO, %g1. Each 64-bit PLT + entry is 8 instructions long, so we can't run into the 'jmp' + delay slot problems 32-bit PLTs can. */ + insns[0] = insn; + __asm __volatile ("flush %0" : : "r" (insns)); + } + /* 32-bit Sparc style, the target is in the lower 32-bits of + address space. */ + else if (insns += t, (value >> 32) == 0) + { + /* sethi %hi(target), %g1 + jmpl %g1 + %lo(target), %g0 */ + + insns[1] = 0x81c06000 | (value & 0x3ff); + __asm __volatile ("flush %0 + 4" : : "r" (insns)); + + insns[0] = 0x03000000 | ((unsigned int)(value >> 10)); + __asm __volatile ("flush %0" : : "r" (insns)); + } + /* We can also get somewhat simple sequences if the distance between + the target and the PLT entry is within +/- 2GB. */ + else if ((plt_vaddr > value + && ((plt_vaddr - value) >> 31) == 0) + || (value > plt_vaddr + && ((value - plt_vaddr) >> 31) == 0)) + { + unsigned int displacement; + + if (plt_vaddr > value) + displacement = (0 - (plt_vaddr - value)); + else + displacement = value - plt_vaddr; + + /* mov %o7, %g1 + call displacement + mov %g1, %o7 */ + + insns[2] = 0x9e100001; + __asm __volatile ("flush %0 + 8" : : "r" (insns)); + + insns[1] = 0x40000000 | (displacement >> 2); + __asm __volatile ("flush %0 + 4" : : "r" (insns)); + + insns[0] = 0x8210000f; + __asm __volatile ("flush %0" : : "r" (insns)); + } + /* Worst case, ho hum... */ + else + { + unsigned int high32 = (value >> 32); + unsigned int low32 = (unsigned int) value; + + /* ??? Some tricks can be stolen from the sparc64 egcs backend + constant formation code I wrote. -DaveM */ + + if (__glibc_unlikely (high32 & 0x3ff)) + { + /* sethi %hh(value), %g1 + sethi %lm(value), %g5 + or %g1, %hm(value), %g1 + or %g5, %lo(value), %g5 + sllx %g1, 32, %g1 + jmpl %g1 + %g5, %g0 + nop */ + + insns[5] = 0x81c04005; + __asm __volatile ("flush %0 + 20" : : "r" (insns)); + + insns[4] = 0x83287020; + __asm __volatile ("flush %0 + 16" : : "r" (insns)); + + insns[3] = 0x8a116000 | (low32 & 0x3ff); + __asm __volatile ("flush %0 + 12" : : "r" (insns)); + + insns[2] = 0x82106000 | (high32 & 0x3ff); + } + else + { + /* sethi %hh(value), %g1 + sethi %lm(value), %g5 + sllx %g1, 32, %g1 + or %g5, %lo(value), %g5 + jmpl %g1 + %g5, %g0 + nop */ + + insns[4] = 0x81c04005; + __asm __volatile ("flush %0 + 16" : : "r" (insns)); + + insns[3] = 0x8a116000 | (low32 & 0x3ff); + __asm __volatile ("flush %0 + 12" : : "r" (insns)); + + insns[2] = 0x83287020; + } + + __asm __volatile ("flush %0 + 8" : : "r" (insns)); + + insns[1] = 0x0b000000 | (low32 >> 10); + __asm __volatile ("flush %0 + 4" : : "r" (insns)); + + insns[0] = 0x03000000 | (high32 >> 10); + __asm __volatile ("flush %0" : : "r" (insns)); + } +} + +#endif /* dl-plt.h */ diff --git a/REORG.TODO/sysdeps/sparc/sparc64/dl-trampoline.S b/REORG.TODO/sysdeps/sparc/sparc64/dl-trampoline.S new file mode 100644 index 0000000000..8e1a6efb13 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/dl-trampoline.S @@ -0,0 +1,325 @@ +/* PLT trampolines. Sparc 64-bit version. + Copyright (C) 2005-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .text + .align 32 + + /* %g1: PLT offset loaded by PLT entry + * %g4: callers PC, which is PLT0 + 24, therefore we + * add (32 + 8) to get the address of PLT2 which + * is where the magic cookie is stored + */ + .globl _dl_runtime_resolve_0 + .type _dl_runtime_resolve_0, @function +_dl_runtime_resolve_0: + cfi_startproc + + save %sp, -192, %sp + cfi_def_cfa_register(%fp) + cfi_window_save + cfi_register(%o7, %i7) + + sethi %hi(1047552), %l2 + ldx [%g4 + 32 + 8], %o0 + sub %g1, %g4, %l0 + xor %l2, -1016, %l2 + sethi %hi(5120), %l3 /* 160 * 32 */ + add %l0, %l2, %l0 + sethi %hi(32768), %l4 + udivx %l0, %l3, %l3 + sllx %l3, 2, %l1 + add %l1, %l3, %l1 + sllx %l1, 10, %l2 + sub %l4, 4, %l4 + sllx %l1, 5, %l1 + sub %l0, %l2, %l0 + udivx %l0, 24, %l0 + add %l0, %l4, %l0 + add %l1, %l0, %l1 + add %l1, %l1, %l0 + add %l0, %l1, %l0 + call _dl_fixup + sllx %l0, 3, %o1 + jmp %o0 + restore + + cfi_endproc + + .size _dl_runtime_resolve_0, .-_dl_runtime_resolve_0 + + /* %g1: PLT offset loaded by PLT entry + * %g4: callers PC, which is PLT1 + 24, therefore we + * add 8 to get the address of PLT2 which + * is where the magic cookie is stored + */ + .globl _dl_runtime_resolve_1 + .type _dl_runtime_resolve_1, @function +_dl_runtime_resolve_1: + cfi_startproc + + save %sp, -192, %sp + cfi_def_cfa_register(%fp) + cfi_window_save + cfi_register(%o7, %i7) + + srlx %g1, 12, %o1 + ldx [%g4 + 8], %o0 + add %o1, %o1, %o3 + sub %o1, 96, %o1 + call _dl_fixup + add %o1, %o3, %o1 + jmp %o0 + restore + + cfi_endproc + + .size _dl_runtime_resolve_1, .-_dl_runtime_resolve_1 + + /* For the profiling cases we pass in our stack frame + * as the base of the La_sparc64_regs, so it looks + * like: + * %l0 %sp + * ... + * %l7 %sp + (7 * 8) + * %i0 %sp + (8 * 8) + * ... + * %i7 %sp + (15 * 8) + * %f0 %sp + (16 * 8) + * %f16 %sp + (31 * 8) + * framesize %sp + (32 * 8) + */ + + .globl _dl_profile_save_regs + .type _dl_profile_save_regs, @function +_dl_profile_save_regs: + cfi_startproc + + stx %l0, [%sp + STACK_BIAS + ( 0 * 8)] + stx %l1, [%sp + STACK_BIAS + ( 1 * 8)] + stx %l2, [%sp + STACK_BIAS + ( 2 * 8)] + stx %l3, [%sp + STACK_BIAS + ( 3 * 8)] + stx %l4, [%sp + STACK_BIAS + ( 4 * 8)] + stx %l5, [%sp + STACK_BIAS + ( 5 * 8)] + stx %l6, [%sp + STACK_BIAS + ( 6 * 8)] + stx %l7, [%sp + STACK_BIAS + ( 7 * 8)] + stx %i0, [%sp + STACK_BIAS + ( 8 * 8)] + stx %i1, [%sp + STACK_BIAS + ( 9 * 8)] + stx %i2, [%sp + STACK_BIAS + (10 * 8)] + stx %i3, [%sp + STACK_BIAS + (11 * 8)] + stx %i4, [%sp + STACK_BIAS + (12 * 8)] + stx %i5, [%sp + STACK_BIAS + (13 * 8)] + stx %i6, [%sp + STACK_BIAS + (14 * 8)] + stx %i7, [%sp + STACK_BIAS + (15 * 8)] + std %f0, [%sp + STACK_BIAS + (16 * 8)] + std %f2, [%sp + STACK_BIAS + (17 * 8)] + std %f4, [%sp + STACK_BIAS + (18 * 8)] + std %f6, [%sp + STACK_BIAS + (19 * 8)] + std %f8, [%sp + STACK_BIAS + (20 * 8)] + std %f10, [%sp + STACK_BIAS + (21 * 8)] + std %f12, [%sp + STACK_BIAS + (22 * 8)] + std %f14, [%sp + STACK_BIAS + (23 * 8)] + std %f16, [%sp + STACK_BIAS + (24 * 8)] + std %f18, [%sp + STACK_BIAS + (25 * 8)] + std %f20, [%sp + STACK_BIAS + (26 * 8)] + std %f22, [%sp + STACK_BIAS + (27 * 8)] + std %f24, [%sp + STACK_BIAS + (28 * 8)] + std %f26, [%sp + STACK_BIAS + (29 * 8)] + std %f28, [%sp + STACK_BIAS + (30 * 8)] + retl + std %f30, [%sp + STACK_BIAS + (31 * 8)] + + cfi_endproc + + .size _dl_profile_save_regs, .-_dl_profile_save_regs + + /* If we are going to call pltexit, then we must replicate + * the caller's stack frame. + * %o0: PLT resolved function address + */ + .globl _dl_profile_invoke + .type _dl_profile_invoke, @function +_dl_profile_invoke: + cfi_startproc + + add %l0, 7, %l0 + andn %l0, 7, %l0 + add %l0, (8 * 8), %g1 + + sub %sp, %g1, %sp + srlx %l0, 3, %l7 + mov %o0, %l1 + mov %i0, %o0 + mov %i1, %o1 + mov %i2, %o2 + mov %i3, %o3 + mov %i4, %o4 + mov %i5, %o5 + add %fp, STACK_BIAS, %l2 + brz %l0, 2f + add %sp, STACK_BIAS, %l3 +1: ldx [%l2], %l4 + add %l2, 0x8, %l2 + subcc %l7, 1, %l7 + stx %l4, [%l3] + bne,pt %xcc, 1b + add %l3, 0x8, %l3 + +2: jmpl %l1, %o7 + nop + + stx %o0, [%sp + STACK_BIAS + (16 * 8)] + stx %o1, [%sp + STACK_BIAS + (17 * 8)] + stx %o2, [%sp + STACK_BIAS + (18 * 8)] + stx %o3, [%sp + STACK_BIAS + (19 * 8)] + std %f0, [%sp + STACK_BIAS + (20 * 8)] + std %f2, [%sp + STACK_BIAS + (21 * 8)] + std %f4, [%sp + STACK_BIAS + (22 * 8)] + std %f8, [%sp + STACK_BIAS + (23 * 8)] + + mov %l5, %o0 + mov %l6, %o1 + add %sp, STACK_BIAS + (24 * 8), %o2 + call _dl_call_pltexit + add %sp, STACK_BIAS + (16 * 8), %o3 + + ldx [%sp + STACK_BIAS + (16 * 8)], %i0 + ldx [%sp + STACK_BIAS + (17 * 8)], %i1 + ldx [%sp + STACK_BIAS + (18 * 8)], %i2 + ldx [%sp + STACK_BIAS + (19 * 8)], %i3 + ldd [%sp + STACK_BIAS + (20 * 8)], %f0 + ldd [%sp + STACK_BIAS + (21 * 8)], %f2 + ldd [%sp + STACK_BIAS + (22 * 8)], %f4 + ldd [%sp + STACK_BIAS + (23 * 8)], %f8 + + jmpl %i7 + 8, %g0 + restore + + cfi_endproc + + .size _dl_profile_invoke, .-_dl_profile_invoke + + /* %g1: PLT offset loaded by PLT entry + * %g4: callers PC, which is PLT0 + 24, therefore we + * add (32 + 8) to get the address of PLT2 which + * is where the magic cookie is stored + */ + .align 32 + .globl _dl_runtime_profile_0 + .type _dl_runtime_profile_0, @function +_dl_runtime_profile_0: + cfi_startproc + + save %sp, -336, %sp + cfi_def_cfa_register(%fp) + cfi_window_save + cfi_register(%o7, %i7) + + sethi %hi(1047552), %l2 + ldx [%g4 + 32 + 8], %o0 + sub %g1, %g4, %l0 + xor %l2, -1016, %l2 + sethi %hi(5120), %l3 /* 160 * 32 */ + add %l0, %l2, %l0 + sethi %hi(32768), %l4 + udivx %l0, %l3, %l3 + sllx %l3, 2, %l1 + add %l1, %l3, %l1 + sllx %l1, 10, %l2 + sub %l4, 4, %l4 + sllx %l1, 5, %l1 + sub %l0, %l2, %l0 + udivx %l0, 24, %l0 + add %l0, %l4, %l0 + add %l1, %l0, %l1 + add %l1, %l1, %l0 + add %l0, %l1, %l0 + + mov %i7, %o2 + sllx %l0, 3, %o1 + + mov %o0, %l5 + mov %o1, %l6 + + call _dl_profile_save_regs + nop + + add %sp, STACK_BIAS, %o3 + call _dl_profile_fixup + add %sp, (STACK_BIAS + (32 * 8)), %o4 + + ldx [%sp + STACK_BIAS + (32 * 8)], %l0 + brlz,pt %l0, 1f + nop + + call _dl_profile_invoke + nop + +1: jmp %o0 + restore + + cfi_endproc + + .size _dl_runtime_profile_0, .-_dl_runtime_profile_0 + + /* %g1: PLT offset loaded by PLT entry + * %g4: callers PC, which is PLT1 + 24, therefore we + * add 8 to get the address of PLT2 which + * is where the magic cookie is stored + */ + .globl _dl_runtime_profile_1 + .type _dl_runtime_profile_1, @function +_dl_runtime_profile_1: + cfi_startproc + + save %sp, -336, %sp + cfi_def_cfa_register(%fp) + cfi_window_save + cfi_register(%o7, %i7) + + srlx %g1, 12, %o1 + ldx [%g4 + 8], %o0 + add %o1, %o1, %o3 + sub %o1, 96, %o1 + mov %i7, %o2 + add %o1, %o3, %o1 + + mov %o0, %l5 + mov %o1, %l6 + + call _dl_profile_save_regs + nop + + add %sp, STACK_BIAS, %o3 + call _dl_profile_fixup + add %sp, (STACK_BIAS + (32 * 8)), %o4 + + ldx [%sp + STACK_BIAS + (32 * 8)], %l0 + brlz,pt %l0, 1f + nop + + call _dl_profile_invoke + nop + +1: jmp %o0 + restore + + cfi_endproc + + .size _dl_runtime_resolve_1, .-_dl_runtime_resolve_1 diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/e_sqrtl.c b/REORG.TODO/sysdeps/sparc/sparc64/fpu/e_sqrtl.c new file mode 100644 index 0000000000..c540d05841 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/e_sqrtl.c @@ -0,0 +1,31 @@ +/* Long double square root, sparc64 version. + Copyright (C) 2000-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jakub@redhat.com>, 2000. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math.h> + +extern void _Qp_sqrt(long double *, const long double *); + +long double +__ieee754_sqrtl (long double x) +{ + long double ret; + _Qp_sqrt (&ret, &x); + return ret; +} +strong_alias (__ieee754_sqrtl, __sqrtl_finite) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/Makefile b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/Makefile new file mode 100644 index 0000000000..03a271dfa4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/Makefile @@ -0,0 +1,22 @@ +ifeq ($(subdir),math) +ifeq ($(have-as-vis3),yes) +libm-sysdep_routines += m_signbitf-vis3 m_signbit-vis3 m_finitef-vis3 \ + m_finite-vis3 m_isinff-vis3 m_isinf-vis3 \ + m_isnanf-vis3 m_isnan-vis3 s_lrintf-vis3 \ + s_lrint-vis3 s_rintf-vis3 s_rint-vis3 \ + s_fmaf-vis3 s_fma-vis3 \ + s_nearbyint-vis3 s_nearbyintf-vis3 \ + s_ceilf-vis3 s_ceil-vis3 s_floorf-vis3 \ + s_floor-vis3 s_truncf-vis3 s_trunc-vis3 +sysdep_routines += s_signbitf-vis3 s_signbit-vis3 s_finitef-vis3 \ + s_finite-vis3 s_isinff-vis3 s_isinf-vis3 \ + s_isnanf-vis3 s_isnan-vis3 + +CFLAGS-s_ceilf-vis3.c += -Wa,-Av9d -mvis3 +CFLAGS-s_ceil-vis3.c += -Wa,-Av9d -mvis3 +CFLAGS-s_floorf-vis3.c += -Wa,-Av9d -mvis3 +CFLAGS-s_floor-vis3.c += -Wa,-Av9d -mvis3 +CFLAGS-s_truncf-vis3.c += -Wa,-Av9d -mvis3 +CFLAGS-s_trunc-vis3.c += -Wa,-Av9d -mvis3 +endif +endif diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.c b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.c new file mode 100644 index 0000000000..fa9c5d33ea --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.c @@ -0,0 +1,23 @@ +/* ceil function, sparc64 vis3 version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math.h> + +#define __ceil __ceil_vis3 + +#include <sysdeps/ieee754/dbl-64/wordsize-64/s_ceil.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.c b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.c new file mode 100644 index 0000000000..efa05e94df --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.c @@ -0,0 +1,32 @@ +/* ceil function, sparc64 version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifdef HAVE_AS_VIS3_SUPPORT +# include <sparc-ifunc.h> +# include <math.h> + +extern double __ceil_vis3 (double); +extern double __ceil_generic (double); + +sparc_libm_ifunc(__ceil, hwcap & HWCAP_SPARC_VIS3 ? __ceil_vis3 : __ceil_generic); +weak_alias (__ceil, ceil) + +# define __ceil __ceil_generic +#endif + +#include <sysdeps/ieee754/dbl-64/wordsize-64/s_ceil.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.c b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.c new file mode 100644 index 0000000000..1d918de7af --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.c @@ -0,0 +1,23 @@ +/* Float ceil function, sparc64 vis3 version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math.h> + +#define __ceilf __ceilf_vis3 + +#include <sysdeps/ieee754/flt-32/s_ceilf.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.c b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.c new file mode 100644 index 0000000000..62ada7fd2a --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.c @@ -0,0 +1,32 @@ +/* Float ceil function, sparc64 version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifdef HAVE_AS_VIS3_SUPPORT +# include <sparc-ifunc.h> +# include <math.h> + +extern float __ceilf_vis3 (float); +extern float __ceilf_generic (float); + +sparc_libm_ifunc(__ceilf, hwcap & HWCAP_SPARC_VIS3 ? __ceilf_vis3 : __ceilf_generic); +weak_alias (__ceilf, ceilf) + +# define __ceilf __ceilf_generic +#endif + +#include <sysdeps/ieee754/flt-32/s_ceilf.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_finite-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_finite-vis3.S new file mode 100644 index 0000000000..0e2b5f6b00 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_finite-vis3.S @@ -0,0 +1,28 @@ +/* finite(). sparc64 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__finite_vis3) + fabsd %f0, %f0 + movstouw %f0, %o0 + sethi %hi(0x7ff00000), %o2 + sub %o0, %o2, %o0 + retl + srl %o0, 31, %o0 +END (__finite_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_finite.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_finite.S new file mode 100644 index 0000000000..78406a62b1 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_finite.S @@ -0,0 +1,15 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(finite) + +hidden_def (__finite) +weak_alias (__finite, finite) + +# undef weak_alias +# define weak_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __finite __finite_generic + +#include "../s_finite.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_finitef-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_finitef-vis3.S new file mode 100644 index 0000000000..59e17bc75c --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_finitef-vis3.S @@ -0,0 +1,28 @@ +/* finitef(). sparc64 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__finitef_vis3) + fabss %f1, %f0 + movstouw %f0, %o0 + sethi %hi(0x7f800000), %o2 + sub %o0, %o2, %o0 + retl + srl %o0, 31, %o0 +END (__finitef_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_finitef.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_finitef.S new file mode 100644 index 0000000000..cafd41fd92 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_finitef.S @@ -0,0 +1,15 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(finitef) + +hidden_def (__finitef) +weak_alias (__finitef, finitef) + +# undef weak_alias +# define weak_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __finitef __finitef_generic + +#include "../s_finitef.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.c b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.c new file mode 100644 index 0000000000..04f6183664 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.c @@ -0,0 +1,23 @@ +/* floor function, sparc64 vis3 version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math.h> + +#define __floor __floor_vis3 + +#include <sysdeps/ieee754/dbl-64/wordsize-64/s_floor.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_floor.c b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_floor.c new file mode 100644 index 0000000000..d097f68866 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_floor.c @@ -0,0 +1,32 @@ +/* floor function, sparc64 version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifdef HAVE_AS_VIS3_SUPPORT +# include <sparc-ifunc.h> +# include <math.h> + +extern double __floor_vis3 (double); +extern double __floor_generic (double); + +sparc_libm_ifunc(__floor, hwcap & HWCAP_SPARC_VIS3 ? __floor_vis3 : __floor_generic); +weak_alias (__floor, floor) + +# define __floor __floor_generic +#endif + +#include <sysdeps/ieee754/dbl-64/wordsize-64/s_floor.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.c b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.c new file mode 100644 index 0000000000..0ff49e6802 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.c @@ -0,0 +1,23 @@ +/* Float floor function, sparc64 vis3 version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math.h> + +#define __floorf __floorf_vis3 + +#include <sysdeps/ieee754/flt-32/s_floorf.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.c b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.c new file mode 100644 index 0000000000..2a6c710349 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.c @@ -0,0 +1,32 @@ +/* Float floor function, sparc64 version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifdef HAVE_AS_VIS3_SUPPORT +# include <sparc-ifunc.h> +# include <math.h> + +extern float __floorf_vis3 (float); +extern float __floorf_generic (float); + +sparc_libm_ifunc(__floorf, hwcap & HWCAP_SPARC_VIS3 ? __floorf_vis3 : __floorf_generic); +weak_alias (__floorf, floorf) + +# define __floorf __floorf_generic +#endif + +#include <sysdeps/ieee754/flt-32/s_floorf.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_fma-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_fma-vis3.S new file mode 100644 index 0000000000..343ce37de9 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_fma-vis3.S @@ -0,0 +1,25 @@ +/* fma function, sparc64 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__fma_vis3) + retl + fmaddd %f0, %f2, %f4, %f0 +END (__fma_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_fma.c b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_fma.c new file mode 100644 index 0000000000..3f2f1622c8 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_fma.c @@ -0,0 +1,14 @@ +#ifdef HAVE_AS_VIS3_SUPPORT +# include <sparc-ifunc.h> +# include <math.h> + +extern double __fma_vis3 (double, double, double); +extern double __fma_generic (double, double, double); + +sparc_libm_ifunc(__fma, hwcap & HWCAP_SPARC_FMAF ? __fma_vis3 : __fma_generic); +weak_alias (__fma, fma) + +# define __fma __fma_generic +#endif + +#include <sysdeps/ieee754/dbl-64/s_fma.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_fmaf-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_fmaf-vis3.S new file mode 100644 index 0000000000..c2fa72a211 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_fmaf-vis3.S @@ -0,0 +1,25 @@ +/* fmaf function, sparc64 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__fmaf_vis3) + retl + fmadds %f1, %f3, %f5, %f0 +END (__fmaf_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_fmaf.c b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_fmaf.c new file mode 100644 index 0000000000..7a273a3b13 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_fmaf.c @@ -0,0 +1,14 @@ +#ifdef HAVE_AS_VIS3_SUPPORT +# include <sparc-ifunc.h> +# include <math.h> + +extern float __fmaf_vis3 (float, float, float); +extern float __fmaf_generic (float, float, float); + +sparc_libm_ifunc(__fmaf, hwcap & HWCAP_SPARC_FMAF ? __fmaf_vis3 : __fmaf_generic); +weak_alias (__fmaf, fmaf) + +# define __fmaf __fmaf_generic +#endif + +#include <sysdeps/ieee754/dbl-64/s_fmaf.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isinf-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isinf-vis3.S new file mode 100644 index 0000000000..54ff556eb8 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isinf-vis3.S @@ -0,0 +1,31 @@ +/* isinf(). sparc64 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__isinf_vis3) + movdtox %f0, %g1 + sethi %hi(0x7ff00000), %o2 + sllx %o2, 32, %o2 + sllx %g1, 1, %o4 + srlx %o4, 1, %o5 + srax %g1, 62, %o0 + xor %o5, %o2, %o3 + retl + movrne %o3, %g0, %o0 +END (__isinf_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.S new file mode 100644 index 0000000000..ed9b62640d --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.S @@ -0,0 +1,15 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(isinf) + +hidden_def (__isinf) +weak_alias (__isinf, isinf) + +# undef weak_alias +# define weak_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __isinf __isinf_generic + +#include "../s_isinf.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isinff-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isinff-vis3.S new file mode 100644 index 0000000000..853bfc64e4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isinff-vis3.S @@ -0,0 +1,30 @@ +/* isinff(). sparc64 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__isinff_vis3) + movstouw %f1, %g1 + sethi %hi(0x7f800000), %o2 + sll %g1, 1, %o4 + srl %o4, 1, %o5 + sra %g1, 30, %o0 + xor %o5, %o2, %o3 + retl + movrne %o3, %g0, %o0 +END (__isinff_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isinff.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isinff.S new file mode 100644 index 0000000000..04517398f8 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isinff.S @@ -0,0 +1,15 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(isinff) + +hidden_def (__isinff) +weak_alias (__isinff, isinff) + +# undef weak_alias +# define weak_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __isinff __isinff_generic + +#include "../s_isinff.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isnan-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isnan-vis3.S new file mode 100644 index 0000000000..6dbb8dee2c --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isnan-vis3.S @@ -0,0 +1,30 @@ +/* isnan(). sparc64 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__isnan_vis3) + movdtox %f0, %o0 + sethi %hi(0x7ff00000), %g1 + sllx %g1, 32, %g1 + sllx %o0, 1, %o0 + srlx %o0, 1, %o0 + sub %g1, %o0, %o0 + retl + srlx %o0, 63, %o0 +END (__isnan_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.S new file mode 100644 index 0000000000..40e985a5d4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.S @@ -0,0 +1,15 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(isnan) + +hidden_def (__isnan) +weak_alias (__isnan, isnan) + +# undef weak_alias +# define weak_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __isnan __isnan_generic + +#include "../s_isnan.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf-vis3.S new file mode 100644 index 0000000000..46fbf6de9f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf-vis3.S @@ -0,0 +1,29 @@ +/* isnanf(). sparc64 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__isnanf_vis3) + movstouw %f1, %o0 + sethi %hi(0x7f800000), %g1 + sll %o0, 1, %o0 + srl %o0, 1, %o0 + sub %g1, %o0, %o0 + retl + srl %o0, 31, %o0 +END (__isnanf_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf.S new file mode 100644 index 0000000000..6b53b69d2e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf.S @@ -0,0 +1,15 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(isnanf) + +hidden_def (__isnanf) +weak_alias (__isnanf, isnanf) + +# undef weak_alias +# define weak_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __isnanf __isnanf_generic + +#include "../s_isnanf.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_lrint-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_lrint-vis3.S new file mode 100644 index 0000000000..87895371dd --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_lrint-vis3.S @@ -0,0 +1,52 @@ +/* lrint(), sparc64 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__lrint_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o2, 32, %o2 + fzero ZERO + + fnegd ZERO, SIGN_BIT + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + for %f0, SIGN_BIT, %f0 + fdtox %f0, %f4 + retl + movdtox %f4, %o0 +END (__lrint_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.S new file mode 100644 index 0000000000..94af8f028c --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.S @@ -0,0 +1,17 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(lrint) + +weak_alias (__lrint, lrint) + +strong_alias (__lrint, __llrint) +weak_alias (__llrint, llrint) + +# undef weak_alias +# define weak_alias(a, b) +# undef strong_alias +# define strong_alias(a, b) + +#define __lrint __lrint_generic + +#include "../s_lrint.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf-vis3.S new file mode 100644 index 0000000000..3ef005d433 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf-vis3.S @@ -0,0 +1,51 @@ +/* lrintf(), sparc64 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__lrintf_vis3) + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + movwtos %o2, %f16 + fabss %f1, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + fstox %f0, %f4 + retl + movdtox %f4, %o0 +END (__lrintf_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf.S new file mode 100644 index 0000000000..e6ea4061c3 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf.S @@ -0,0 +1,17 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(lrintf) + +weak_alias (__lrintf, lrintf) + +strong_alias (__lrintf, __llrintf) +weak_alias (__llrintf, llrintf) + +# undef weak_alias +# define weak_alias(a, b) +# undef strong_alias +# define strong_alias(a, b) + +#define __lrintf __lrintf_generic + +#include "../s_lrintf.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint-vis3.S new file mode 100644 index 0000000000..67e570a800 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint-vis3.S @@ -0,0 +1,62 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc64 vis3 version. + + Copyright (C) 2013-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyint_vis3) + fcmpd %fcc3, %f0, %f0 /* Check for sNaN */ + stx %fsr, [%sp + STACK_BIAS + 144] + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o2, 32, %o2 + ldx [%sp + STACK_BIAS + 144], %o4 + sethi %hi(0xf8003e0), %o5 + fzero ZERO + or %o5, %lo(0xf8003e0), %o5 + fnegd ZERO, SIGN_BIT + andn %o4, %o5, %o4 + movxtod %o2, %f16 + stx %o4, [%sp + STACK_BIAS + 136] + ldx [%sp + STACK_BIAS + 136], %fsr + fabsd %f0, %f14 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + for %f0, SIGN_BIT, %f0 + retl + ldx [%sp + STACK_BIAS + 144], %fsr +END (__nearbyint_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint.S new file mode 100644 index 0000000000..bb75ab3606 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(nearbyint) + +weak_alias (__nearbyint, nearbyint) + +# undef weak_alias +# define weak_alias(a, b) + +#define __nearbyint __nearbyint_generic + +#include "../s_nearbyint.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf-vis3.S new file mode 100644 index 0000000000..208af37d0d --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf-vis3.S @@ -0,0 +1,61 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc64 vis3 version. + + Copyright (C) 2013-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyintf_vis3) + fcmps %fcc3, %f1, %f1 /* Check for sNaN */ + stx %fsr, [%sp + STACK_BIAS + 144] + sethi %hi(0xf8003e0), %o5 + sethi %hi(TWO_TWENTYTHREE), %o2 + ldx [%sp + STACK_BIAS + 144], %o4 + or %o5, %lo(0xf8003e0), %o5 + fzeros ZERO + andn %o4, %o5, %o4 + fnegs ZERO, SIGN_BIT + movwtos %o2, %f16 + stx %o4, [%sp + STACK_BIAS + 136] + ldx [%sp + STACK_BIAS + 136], %fsr + fabss %f1, %f14 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + retl + ldx [%sp + STACK_BIAS + 144], %fsr +END (__nearbyintf_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf.S new file mode 100644 index 0000000000..95100c1bfc --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(nearbyintf) + +weak_alias (__nearbyintf, nearbyintf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __nearbyintf __nearbyintf_generic + +#include "../s_nearbyintf.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_rint-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_rint-vis3.S new file mode 100644 index 0000000000..495a02222e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_rint-vis3.S @@ -0,0 +1,50 @@ +/* Round float to int floating-point values, sparc64 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__rint_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o2, 32, %o2 + fzero ZERO + + fnegd ZERO, SIGN_BIT + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + retl + for %f0, SIGN_BIT, %f0 +END (__rint_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_rint.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_rint.S new file mode 100644 index 0000000000..cc980eb8c7 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_rint.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(rint) + +weak_alias (__rint, rint) + +# undef weak_alias +# define weak_alias(a, b) + +#define __rint __rint_generic + +#include "../s_rint.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_rintf-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_rintf-vis3.S new file mode 100644 index 0000000000..521c0b21ec --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_rintf-vis3.S @@ -0,0 +1,49 @@ +/* Round float to int floating-point values, sparc64 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__rintf_vis3) + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + movwtos %o2, %f16 + fabss %f1, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + retl + fors %f0, SIGN_BIT, %f0 +END (__rintf_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.S new file mode 100644 index 0000000000..38fd936086 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(rintf) + +weak_alias (__rintf, rintf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __rintf __rintf_generic + +#include "../s_rintf.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_signbit-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_signbit-vis3.S new file mode 100644 index 0000000000..bce7c9795a --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_signbit-vis3.S @@ -0,0 +1,25 @@ +/* signbit(). sparc64 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__signbit_vis3) + movdtox %f0, %o0 + retl + srlx %o0, 63, %o0 +END (__signbit_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_signbit.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_signbit.S new file mode 100644 index 0000000000..b8ff64a547 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_signbit.S @@ -0,0 +1,20 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(signbit) + +/* On 64-bit the double version will also always work for + long-double-precision since in both cases the word with the + sign bit in it is passed always in register %f0. */ +strong_alias (__signbit, __signbitl) +hidden_def (__signbitl) + +# undef weak_alias +# define weak_alias(a, b) +# undef strong_alias +# define strong_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __signbit __signbit_generic + +#include "../s_signbit.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf-vis3.S new file mode 100644 index 0000000000..7833e725e6 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf-vis3.S @@ -0,0 +1,25 @@ +/* signbitf(). sparc64 vis3 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__signbitf_vis3) + movstouw %f1, %o0 + retl + srl %o0, 31, %o0 +END (__signbitf_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf.S new file mode 100644 index 0000000000..d57e999b90 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_signbitf.S @@ -0,0 +1,10 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(signbitf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __signbitf __signbitf_generic + +#include "../s_signbitf.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_trunc-vis3.c b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_trunc-vis3.c new file mode 100644 index 0000000000..38ee29a8d3 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_trunc-vis3.c @@ -0,0 +1,23 @@ +/* trunc function, sparc64 vis3 version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math.h> + +#define __trunc __trunc_vis3 + +#include <sysdeps/ieee754/dbl-64/wordsize-64/s_trunc.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_trunc.c b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_trunc.c new file mode 100644 index 0000000000..dc67f423f1 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_trunc.c @@ -0,0 +1,32 @@ +/* trunc function, sparc64 version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifdef HAVE_AS_VIS3_SUPPORT +# include <sparc-ifunc.h> +# include <math.h> + +extern double __trunc_vis3 (double); +extern double __trunc_generic (double); + +sparc_libm_ifunc(__trunc, hwcap & HWCAP_SPARC_VIS3 ? __trunc_vis3 : __trunc_generic); +weak_alias (__trunc, trunc) + +# define __trunc __trunc_generic +#endif + +#include <sysdeps/ieee754/dbl-64/wordsize-64/s_trunc.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_truncf-vis3.c b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_truncf-vis3.c new file mode 100644 index 0000000000..302aa56047 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_truncf-vis3.c @@ -0,0 +1,23 @@ +/* Float trunc function, sparc64 vis3 version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <math.h> + +#define __truncf __truncf_vis3 + +#include <sysdeps/ieee754/flt-32/s_truncf.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_truncf.c b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_truncf.c new file mode 100644 index 0000000000..980a313ae1 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/multiarch/s_truncf.c @@ -0,0 +1,32 @@ +/* Float trunc function, sparc64 version. + Copyright (C) 2016-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifdef HAVE_AS_VIS3_SUPPORT +# include <sparc-ifunc.h> +# include <math.h> + +extern float __truncf_vis3 (float); +extern float __truncf_generic (float); + +sparc_libm_ifunc(__truncf, hwcap & HWCAP_SPARC_VIS3 ? __truncf_vis3 : __truncf_generic); +weak_alias (__truncf, truncf) + +# define __truncf __truncf_generic +#endif + +#include <sysdeps/ieee754/flt-32/s_truncf.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_copysign.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_copysign.S new file mode 100644 index 0000000000..e50d8cd246 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_copysign.S @@ -0,0 +1,30 @@ +/* copysign function, sparc64 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__copysign) + fzeros %f7 + fnegs %f7, %f7 + fands %f2, %f7, %f9 + fandnot2s %f0, %f7, %f0 + retl + fors %f0, %f9, %f0 +END (__copysign) +weak_alias (__copysign, copysign)
\ No newline at end of file diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_copysignf.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_copysignf.S new file mode 100644 index 0000000000..2f24217274 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_copysignf.S @@ -0,0 +1,30 @@ +/* float copysign function, sparc64 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__copysignf) + fzeros %f7 + fnegs %f7, %f7 + fands %f3, %f7, %f9 + fandnot2s %f1, %f7, %f1 + retl + fors %f1, %f9, %f0 +END (__copysignf) +weak_alias (__copysignf, copysignf)
\ No newline at end of file diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_fabs.c b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_fabs.c new file mode 100644 index 0000000000..db5ecf2162 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_fabs.c @@ -0,0 +1,5 @@ +double __fabs (double x) +{ + return __builtin_fabs (x); +} +weak_alias (__fabs, fabs) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_fabsf.c b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_fabsf.c new file mode 100644 index 0000000000..8a218e4942 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_fabsf.c @@ -0,0 +1,5 @@ +float __fabsf (float x) +{ + return __builtin_fabsf (x); +} +weak_alias (__fabsf, fabsf) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_fabsl.c b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_fabsl.c new file mode 100644 index 0000000000..67e9f47071 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_fabsl.c @@ -0,0 +1,5 @@ +long double __fabsl (long double x) +{ + return __builtin_fabsl (x); +} +weak_alias (__fabsl, fabsl) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_finite.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_finite.S new file mode 100644 index 0000000000..28ee074c1d --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_finite.S @@ -0,0 +1,31 @@ +/* finite(). sparc64 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__finite) + fabsd %f0, %f0 + st %f0, [%sp + STACK_BIAS + 128] + sethi %hi(0x7ff00000), %o2 + ld [%sp + STACK_BIAS + 128], %o0 + sub %o0, %o2, %o0 + retl + srl %o0, 31, %o0 +END (__finite) +hidden_def (__finite) +weak_alias (__finite, finite) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_finitef.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_finitef.S new file mode 100644 index 0000000000..f3edca3c57 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_finitef.S @@ -0,0 +1,31 @@ +/* finitef(). sparc64 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__finitef) + fabss %f1, %f0 + st %f0, [%sp + STACK_BIAS + 128] + sethi %hi(0x7f800000), %o2 + ld [%sp + STACK_BIAS + 128], %o0 + sub %o0, %o2, %o0 + retl + srl %o0, 31, %o0 +END (__finitef) +hidden_def (__finitef) +weak_alias (__finitef, finitef) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_fma.c b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_fma.c new file mode 100644 index 0000000000..8f62605870 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_fma.c @@ -0,0 +1,2 @@ +/* Always use dbl-64 version because long double is emulated in software. */ +#include <sysdeps/ieee754/dbl-64/s_fma.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_isinf.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_isinf.S new file mode 100644 index 0000000000..b333a99f54 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_isinf.S @@ -0,0 +1,34 @@ +/* isinf(). sparc64 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__isinf) + std %f0, [%sp + STACK_BIAS + 128] + sethi %hi(0x7ff00000), %o2 + ldx [%sp + STACK_BIAS + 128], %g1 + sllx %o2, 32, %o2 + sllx %g1, 1, %o4 + srlx %o4, 1, %o5 + srax %g1, 62, %o0 + xor %o5, %o2, %o3 + retl + movrne %o3, %g0, %o0 +END (__isinf) +hidden_def (__isinf) +weak_alias (__isinf, isinf) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_isinff.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_isinff.S new file mode 100644 index 0000000000..a5ecf15a9f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_isinff.S @@ -0,0 +1,33 @@ +/* isinff(). sparc64 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__isinff) + st %f1, [%sp + STACK_BIAS + 128] + sethi %hi(0x7f800000), %o2 + lduw [%sp + STACK_BIAS + 128], %g1 + sll %g1, 1, %o4 + srl %o4, 1, %o5 + sra %g1, 30, %o0 + xor %o5, %o2, %o3 + retl + movrne %o3, %g0, %o0 +END (__isinff) +hidden_def (__isinff) +weak_alias (__isinff, isinff) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_isnan.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_isnan.S new file mode 100644 index 0000000000..21084ce379 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_isnan.S @@ -0,0 +1,33 @@ +/* isnan(). sparc64 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__isnan) + std %f0, [%sp + STACK_BIAS + 128] + sethi %hi(0x7ff00000), %g1 + ldx [%sp + STACK_BIAS + 128], %o0 + sllx %g1, 32, %g1 + sllx %o0, 1, %o0 + srlx %o0, 1, %o0 + sub %g1, %o0, %o0 + retl + srlx %o0, 63, %o0 +END (__isnan) +hidden_def (__isnan) +weak_alias (__isnan, isnan) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_isnanf.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_isnanf.S new file mode 100644 index 0000000000..a012f42746 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_isnanf.S @@ -0,0 +1,32 @@ +/* isnanf(). sparc64 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__isnanf) + st %f1, [%sp + STACK_BIAS + 128] + sethi %hi(0x7f800000), %g1 + lduw [%sp + STACK_BIAS + 128], %o0 + sll %o0, 1, %o0 + srl %o0, 1, %o0 + sub %g1, %o0, %o0 + retl + srl %o0, 31, %o0 +END (__isnanf) +hidden_def (__isnanf) +weak_alias (__isnanf, isnanf) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_llrint.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_llrint.S new file mode 100644 index 0000000000..7c8e941b77 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_llrint.S @@ -0,0 +1 @@ +/* llrint is implemented in s_lrint.S */ diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_llrintf.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_llrintf.S new file mode 100644 index 0000000000..abab3b9a2b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_llrintf.S @@ -0,0 +1 @@ +/* llrintf is implemented in s_lrint.S */ diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_lrint.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_lrint.S new file mode 100644 index 0000000000..0a3162f947 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_lrint.S @@ -0,0 +1,63 @@ +/* lrint(), sparc64 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__lrint) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o2, 32, %o2 + fzero ZERO + + fnegd ZERO, SIGN_BIT + stx %o2, [%sp + STACK_BIAS + 128] + fabsd %f0, %f14 + + ldd [%sp + STACK_BIAS + 128], %f16 + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + for %f0, SIGN_BIT, %f0 + fdtox %f0, %f4 + std %f4, [%sp + STACK_BIAS + 128] + retl + ldx [%sp + STACK_BIAS + 128], %o0 +END (__lrint) +weak_alias (__lrint, lrint) + +strong_alias (__lrint, __llrint) +weak_alias (__llrint, llrint) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_lrintf.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_lrintf.S new file mode 100644 index 0000000000..5f2405ad9e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_lrintf.S @@ -0,0 +1,62 @@ +/* lrintf(), sparc64 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__lrintf) + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + st %o2, [%sp + STACK_BIAS + 128] + fabss %f1, %f14 + + ld [%sp + STACK_BIAS + 128], %f16 + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + fstox %f0, %f4 + std %f4, [%sp + STACK_BIAS + 128] + retl + ldx [%sp + STACK_BIAS + 128], %o0 +END (__lrintf) +weak_alias (__lrintf, lrintf) + +strong_alias (__lrintf, __llrintf) +weak_alias (__llrintf, llrintf) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_nearbyint.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_nearbyint.S new file mode 100644 index 0000000000..05ed2bce40 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_nearbyint.S @@ -0,0 +1,64 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc64 version. + + Copyright (C) 2013-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyint) + fcmpd %fcc3, %f0, %f0 /* Check for sNaN */ + stx %fsr, [%sp + STACK_BIAS + 144] + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o2, 32, %o2 + ldx [%sp + STACK_BIAS + 144], %o4 + sethi %hi(0xf8003e0), %o5 + fzero ZERO + or %o5, %lo(0xf8003e0), %o5 + fnegd ZERO, SIGN_BIT + andn %o4, %o5, %o4 + stx %o2, [%sp + STACK_BIAS + 128] + stx %o4, [%sp + STACK_BIAS + 136] + ldx [%sp + STACK_BIAS + 136], %fsr + fabsd %f0, %f14 + ldd [%sp + STACK_BIAS + 128], %f16 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + for %f0, SIGN_BIT, %f0 + retl + ldx [%sp + STACK_BIAS + 144], %fsr +END (__nearbyint) +weak_alias (__nearbyint, nearbyint) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_nearbyintf.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_nearbyintf.S new file mode 100644 index 0000000000..55e3639a87 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_nearbyintf.S @@ -0,0 +1,63 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc64 version. + + Copyright (C) 2013-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyintf) + fcmps %fcc3, %f1, %f1 /* Check for sNaN */ + stx %fsr, [%sp + STACK_BIAS + 144] + sethi %hi(0xf8003e0), %o5 + sethi %hi(TWO_TWENTYTHREE), %o2 + ldx [%sp + STACK_BIAS + 144], %o4 + or %o5, %lo(0xf8003e0), %o5 + fzeros ZERO + andn %o4, %o5, %o4 + fnegs ZERO, SIGN_BIT + st %o2, [%sp + STACK_BIAS + 128] + stx %o4, [%sp + STACK_BIAS + 136] + ldx [%sp + STACK_BIAS + 136], %fsr + fabss %f1, %f14 + ld [%sp + STACK_BIAS + 128], %f16 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + retl + ldx [%sp + STACK_BIAS + 144], %fsr +END (__nearbyintf) +weak_alias (__nearbyintf, nearbyintf) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_rint.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_rint.S new file mode 100644 index 0000000000..8d0134c90c --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_rint.S @@ -0,0 +1,57 @@ +/* Round float to int floating-point values, sparc64 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__rint) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o2, 32, %o2 + fzero ZERO + + fnegd ZERO, SIGN_BIT + stx %o2, [%sp + STACK_BIAS + 128] + fabsd %f0, %f14 + + ldd [%sp + STACK_BIAS + 128], %f16 + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + retl + for %f0, SIGN_BIT, %f0 +END (__rint) +weak_alias (__rint, rint) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_rintf.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_rintf.S new file mode 100644 index 0000000000..a2f9261382 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_rintf.S @@ -0,0 +1,56 @@ +/* Round float to int floating-point values, sparc64 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__rintf) + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + st %o2, [%sp + STACK_BIAS + 128] + fabss %f1, %f14 + + ld [%sp + STACK_BIAS + 128], %f16 + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + retl + fors %f0, SIGN_BIT, %f0 +END (__rintf) +weak_alias (__rintf, rintf) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_signbit.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_signbit.S new file mode 100644 index 0000000000..979917b5d0 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_signbit.S @@ -0,0 +1,32 @@ +/* signbit(). sparc64 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__signbit) + st %f0, [%sp + STACK_BIAS + 128] + ld [%sp + STACK_BIAS + 128], %o0 + retl + srl %o0, 31, %o0 +END (__signbit) + +/* On 64-bit the double version will also always work for + long-double-precision since in both cases the word with the + sign bit in it is passed always in register %f0. */ +strong_alias (__signbit, __signbitl) +hidden_def (__signbitl) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_signbitf.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_signbitf.S new file mode 100644 index 0000000000..cb96983868 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_signbitf.S @@ -0,0 +1,26 @@ +/* signbitf(). sparc64 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__signbitf) + st %f1, [%sp + STACK_BIAS + 128] + ld [%sp + STACK_BIAS + 128], %o0 + retl + srl %o0, 31, %o0 +END (__signbitf) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_signbitl.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_signbitl.S new file mode 100644 index 0000000000..f5e5fb9253 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/s_signbitl.S @@ -0,0 +1 @@ +/* signbitl is implemented in s_signbit.S */ diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/w_sqrt_compat.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/w_sqrt_compat.S new file mode 100644 index 0000000000..de95e52e8e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/w_sqrt_compat.S @@ -0,0 +1,48 @@ +/* sqrt function. sparc64 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__sqrt) + fzero %f8 + fcmpd %fcc2, %f0, %f8 + fbl,pn %fcc2, 1f + nop +8: retl + fsqrtd %f0, %f0 +1: +#ifdef SHARED + SETUP_PIC_REG_LEAF(o5, g1) + sethi %gdop_hix22(_LIB_VERSION), %g1 + xor %g1, %gdop_lox10(_LIB_VERSION), %g1 + ldx [%o5 + %g1], %g1, %gdop(_LIB_VERSION) +#else + sethi %hi(_LIB_VERSION), %g1 + or %g1, %lo(_LIB_VERSION), %g1 +#endif + ld [%g1], %g1 + cmp %g1, -1 + be,pt %icc, 8b + fmovd %f0, %f2 + mov 26, %o2 + mov %o7, %g1 + call __kernel_standard + mov %g1, %o7 +END (__sqrt) + +weak_alias (__sqrt, sqrt) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/fpu/w_sqrtf_compat.S b/REORG.TODO/sysdeps/sparc/sparc64/fpu/w_sqrtf_compat.S new file mode 100644 index 0000000000..0c253fe43a --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/fpu/w_sqrtf_compat.S @@ -0,0 +1,48 @@ +/* sqrtf function. sparc64 version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__sqrtf) + fzeros %f8 + fcmps %fcc2, %f1, %f8 + fbl,pn %fcc2, 1f + nop +8: retl + fsqrts %f1, %f0 +1: +#ifdef SHARED + SETUP_PIC_REG_LEAF(o5, g1) + sethi %gdop_hix22(_LIB_VERSION), %g1 + xor %g1, %gdop_lox10(_LIB_VERSION), %g1 + ldx [%o5 + %g1], %g1, %gdop(_LIB_VERSION) +#else + sethi %hi(_LIB_VERSION), %g1 + or %g1, %lo(_LIB_VERSION), %g1 +#endif + ld [%g1], %g1 + cmp %g1, -1 + be,pt %icc, 8b + fmovs %f1, %f3 + mov 126, %o2 + mov %o7, %g1 + call __kernel_standard_f + mov %g1, %o7 +END (__sqrtf) + +weak_alias (__sqrtf, sqrtf) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/hp-timing.h b/REORG.TODO/sysdeps/sparc/sparc64/hp-timing.h new file mode 100644 index 0000000000..433dd28d06 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/hp-timing.h @@ -0,0 +1,33 @@ +/* High precision, low overhead timing functions. sparc64 version. + Copyright (C) 2001-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@redhat.com>, 2001. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef _HP_TIMING_H +#define _HP_TIMING_H 1 + +#define HP_TIMING_AVAIL (1) +#define HP_SMALL_TIMING_AVAIL (1) +#define HP_TIMING_INLINE (1) + +typedef unsigned long int hp_timing_t; + +#define HP_TIMING_NOW(Var) __asm__ __volatile__ ("rd %%tick, %0" : "=r" (Var)) + +#include <hp-timing-common.h> + +#endif /* hp-timing.h */ diff --git a/REORG.TODO/sysdeps/sparc/sparc64/jmpbuf-unwind.h b/REORG.TODO/sysdeps/sparc/sparc64/jmpbuf-unwind.h new file mode 100644 index 0000000000..eb2e2e2fb4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/jmpbuf-unwind.h @@ -0,0 +1,37 @@ +/* Copyright (C) 2005-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2005. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <setjmp.h> +#include <stdint.h> +#include <unwind.h> + +/* Test if longjmp to JMPBUF would unwind the frame + containing a local variable at ADDRESS. */ +#define _JMPBUF_UNWINDS(jmpbuf, address, demangle) \ + ((unsigned long int) (address) \ + < (jmpbuf)->__uc_mcontext.__mc_gregs[MC_O6] + 2047) + +#define _JMPBUF_CFA_UNWINDS_ADJ(_jmpbuf, _context, _adj) \ + _JMPBUF_UNWINDS_ADJ (_jmpbuf, (void *) _Unwind_GetCFA (_context), _adj) + +#define _JMPBUF_UNWINDS_ADJ(_jmpbuf, _address, _adj) \ + ((uintptr_t) (_address) - (_adj) \ + < (uintptr_t) (_jmpbuf)[0].__uc_mcontext.__mc_gregs[MC_O6] + 2047 - (_adj)) + +/* We use the normal lobngjmp for unwinding. */ +#define __libc_unwind_longjmp(buf, val) __libc_longjmp (buf, val) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/lshift.S b/REORG.TODO/sysdeps/sparc/sparc64/lshift.S new file mode 100644 index 0000000000..74ce43bb01 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/lshift.S @@ -0,0 +1,95 @@ +/* SPARC v9 __mpn_lshift -- + + Copyright (C) 1996-2017 Free Software Foundation, Inc. + + This file is part of the GNU MP Library. + + The GNU MP Library is free software; you can redistribute it and/or modify + it under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation; either version 2.1 of the License, or (at your + option) any later version. + + The GNU MP Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with the GNU MP Library; see the file COPYING.LIB. If not, + see <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +/* INPUT PARAMETERS + res_ptr %o0 + src_ptr %o1 + size %o2 + cnt %o3 */ + + .register %g2, #scratch + .register %g3, #scratch + +ENTRY(__mpn_lshift) + sllx %o2,3,%g1 + add %o1,%g1,%o1 ! make %o1 point at end of src + ldx [%o1-8],%g2 ! load first limb + sub %g0,%o3,%o5 ! negate shift count + add %o0,%g1,%o0 ! make %o0 point at end of res + add %o2,-1,%o2 + andcc %o2,4-1,%g4 ! number of limbs in first loop + srlx %g2,%o5,%g1 ! compute function result + be,pn %xcc,.L0 ! if multiple of 4 limbs, skip first loop + mov %g1,%g5 + + sub %o2,%g4,%o2 ! adjust count for main loop + +.Loop0: ldx [%o1-16],%g3 + add %o0,-8,%o0 + add %o1,-8,%o1 + sllx %g2,%o3,%o4 + addcc %g4,-1,%g4 + srlx %g3,%o5,%g1 + mov %g3,%g2 + or %o4,%g1,%o4 + bne,pt %xcc,.Loop0 + stx %o4,[%o0+0] + +.L0: brz,pn %o2,.Lend + nop + +.Loop: ldx [%o1-16],%g3 + add %o0,-32,%o0 + sllx %g2,%o3,%o4 + addcc %o2,-4,%o2 + srlx %g3,%o5,%g1 + + ldx [%o1-24],%g2 + sllx %g3,%o3,%g4 + or %o4,%g1,%o4 + stx %o4,[%o0+24] + srlx %g2,%o5,%g1 + + ldx [%o1-32],%g3 + sllx %g2,%o3,%o4 + or %g4,%g1,%g4 + stx %g4,[%o0+16] + srlx %g3,%o5,%g1 + + ldx [%o1-40],%g2 + sllx %g3,%o3,%g4 + or %o4,%g1,%o4 + stx %o4,[%o0+8] + srlx %g2,%o5,%g1 + + add %o1,-32,%o1 + or %g4,%g1,%g4 + bne,pt %xcc,.Loop + stx %g4,[%o0+0] + +.Lend: sllx %g2,%o3,%g2 + stx %g2,[%o0-8] + + jmpl %o7+8, %g0 + mov %g5,%o0 + +END(__mpn_lshift) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/memchr.S b/REORG.TODO/sysdeps/sparc/sparc64/memchr.S new file mode 100644 index 0000000000..e82075510b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/memchr.S @@ -0,0 +1,260 @@ +/* memchr (str, ch, n) -- Return pointer to first occurrence of CH in STR less + than N. + For SPARC v9. + Copyright (C) 1998-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jan Vondrak <jvon4518@ss1000.ms.mff.cuni.cz> and + Jakub Jelinek <jj@ultra.linux.cz>. + This version is developed using the same algorithm as the fast C + version which carries the following introduction: + Based on strlen implementation by Torbjorn Granlund (tege@sics.se), + with help from Dan Sahlin (dan@sics.se) and + commentary by Jim Blandy (jimb@ai.mit.edu); + adaptation to memchr suggested by Dick Karpinski (dick@cca.ucsf.edu), + and implemented by Roland McGrath (roland@ai.mit.edu). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <asm/asi.h> +#ifndef XCC +#define XCC xcc +#define USE_BPR + .register %g2, #scratch + .register %g3, #scratch +#endif + + /* Normally, this uses + ((xword - 0x0101010101010101) & 0x8080808080808080) test + to find out if any byte in xword could be zero. This is fast, but + also gives false alarm for any byte in range 0x81-0xff. It does + not matter for correctness, as if this test tells us there could + be some zero byte, we check it byte by byte, but if bytes with + high bits set are common in the strings, then this will give poor + performance. You can #define EIGHTBIT_NOT_RARE and the algorithm + will use one tick slower, but more precise test + ((xword - 0x0101010101010101) & (~xword) & 0x8080808080808080), + which does not give any false alarms (but if some bits are set, + one cannot assume from it which bytes are zero and which are not). + It is yet to be measured, what is the correct default for glibc + in these days for an average user. + */ + + .text + .align 32 +ENTRY(__memchr) + and %o1, 0xff, %o1 /* IEU0 Group */ +#ifdef USE_BPR + brz,pn %o2, 12f /* CTI+IEU1 */ +#else + tst %o2 /* IEU1 */ + be,pn %XCC, 12f /* CTI */ +#endif + sll %o1, 8, %g3 /* IEU0 Group */ + addcc %o0, %o2, %o2 /* IEU1 */ + movcs %XCC, -1, %o2 /* IEU0 Group */ + + sethi %hi(0x01010101), %g1 /* IEU0 Group */ + or %g3, %o1, %g3 /* IEU1 */ + ldub [%o0], %o3 /* Load */ + sllx %g3, 16, %g5 /* IEU0 Group */ + + or %g1, %lo(0x01010101), %g1 /* IEU1 */ + sllx %g1, 32, %g2 /* IEU0 Group */ + or %g3, %g5, %g3 /* IEU1 */ + sllx %g3, 32, %g5 /* IEU0 Group */ + + cmp %o3, %o1 /* IEU1 */ + be,pn %xcc, 13f /* CTI */ + or %g1, %g2, %g1 /* IEU0 Group */ + andcc %o0, 7, %g0 /* IEU1 */ + + bne,a,pn %icc, 21f /* CTI */ + add %o0, 1, %o0 /* IEU0 Group */ + ldx [%o0], %o3 /* Load Group */ + sllx %g1, 7, %g2 /* IEU0 */ + + or %g3, %g5, %g3 /* IEU1 */ +1: add %o0, 8, %o0 /* IEU0 Group */ + xor %o3, %g3, %o4 /* IEU1 */ + /* %g1 = 0101010101010101 * + * %g2 = 8080088080808080 * + * %g3 = c c c c c c c c * + * %o3 = value * + * %o4 = value XOR c */ +2: cmp %o0, %o2 /* IEU1 Group */ + + bgu,pn %XCC, 11f /* CTI */ + ldxa [%o0] ASI_PNF, %o3 /* Load */ + sub %o4, %g1, %o5 /* IEU0 Group */ + add %o0, 8, %o0 /* IEU1 */ +#ifdef EIGHTBIT_NOT_RARE + andn %o5, %o4, %o5 /* IEU0 Group */ +#endif + + andcc %o5, %g2, %g0 /* IEU1 Group */ + be,a,pt %xcc, 2b /* CTI */ + xor %o3, %g3, %o4 /* IEU0 */ + srlx %o4, 56, %g5 /* IEU0 */ + + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 3f /* CTI */ + srlx %o4, 48, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 4f /* CTI */ + srlx %o4, 40, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 5f /* CTI */ + + srlx %o4, 32, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 6f /* CTI */ + srlx %o4, 24, %g5 /* IEU0 */ + + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 7f /* CTI */ + srlx %o4, 16, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 8f /* CTI */ + srlx %o4, 8, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 9f /* CTI */ + + andcc %o4, 0xff, %g0 /* IEU1 Group */ + bne,pt %icc, 2b /* CTI */ + xor %o3, %g3, %o4 /* IEU0 */ + retl /* CTI+IEU1 Group */ + + add %o0, -9, %o0 /* IEU0 */ + + .align 16 +3: retl /* CTI+IEU1 Group */ + add %o0, -16, %o0 /* IEU0 */ +4: retl /* CTI+IEU1 Group */ + add %o0, -15, %o0 /* IEU0 */ + +5: retl /* CTI+IEU1 Group */ + add %o0, -14, %o0 /* IEU0 */ +6: retl /* CTI+IEU1 Group */ + add %o0, -13, %o0 /* IEU0 */ + +7: retl /* CTI+IEU1 Group */ + add %o0, -12, %o0 /* IEU0 */ +8: retl /* CTI+IEU1 Group */ + add %o0, -11, %o0 /* IEU0 */ + +9: retl /* CTI+IEU1 Group */ + add %o0, -10, %o0 /* IEU0 */ +11: sub %o4, %g1, %o5 /* IEU0 Group */ + sub %o0, 8, %o0 /* IEU1 */ + + andcc %o5, %g2, %g0 /* IEU1 Group */ + be,pt %xcc, 12f /* CTI */ + sub %o2, %o0, %o2 /* IEU0 */ + tst %o2 /* IEU1 Group */ + + be,pn %XCC, 12f /* CTI */ + srlx %o4, 56, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 13f /* CTI */ + + cmp %o2, 1 /* IEU0 */ + be,pn %XCC, 12f /* CTI Group */ + srlx %o4, 48, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 14f /* CTI */ + cmp %o2, 2 /* IEU1 Group */ + be,pn %XCC, 12f /* CTI */ + srlx %o4, 40, %g5 /* IEU0 */ + + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 15f /* CTI */ + cmp %o2, 3 /* IEU1 Group */ + be,pn %XCC, 12f /* CTI */ + + srlx %o4, 32, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 16f /* CTI */ + cmp %o2, 4 /* IEU1 Group */ + + be,pn %XCC, 12f /* CTI */ + srlx %o4, 24, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 17f /* CTI */ + + cmp %o2, 5 /* IEU1 Group */ + be,pn %XCC, 12f /* CTI */ + srlx %o4, 16, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 18f /* CTI */ + cmp %o2, 6 /* IEU1 Group */ + be,pn %XCC, 12f /* CTI */ + srlx %o4, 8, %g5 /* IEU0 */ + + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 19f /* CTI */ + nop /* IEU0 */ +12: retl /* CTI+IEU1 Group */ + + clr %o0 /* IEU0 */ + nop /* Stub */ +13: retl /* CTI+IEU1 Group */ + nop /* IEU0 */ + +14: retl /* CTI+IEU1 Group */ + add %o0, 1, %o0 /* IEU0 */ +15: retl /* CTI+IEU1 Group */ + add %o0, 2, %o0 /* IEU0 */ + +16: retl /* CTI+IEU1 Group */ + add %o0, 3, %o0 /* IEU0 */ +17: retl /* CTI+IEU1 Group */ + add %o0, 4, %o0 /* IEU0 */ + +18: retl /* CTI+IEU1 Group */ + add %o0, 5, %o0 /* IEU0 */ +19: retl /* CTI+IEU1 Group */ + add %o0, 6, %o0 /* IEU0 */ + +21: cmp %o0, %o2 /* IEU1 */ + be,pn %XCC, 12b /* CTI */ + sllx %g1, 7, %g2 /* IEU0 Group */ + ldub [%o0], %o3 /* Load */ + + or %g3, %g5, %g3 /* IEU1 */ +22: andcc %o0, 7, %g0 /* IEU1 Group */ + be,a,pn %icc, 1b /* CTI */ + ldx [%o0], %o3 /* Load */ + + cmp %o3, %o1 /* IEU1 Group */ + be,pn %xcc, 23f /* CTI */ + add %o0, 1, %o0 /* IEU0 */ + cmp %o0, %o2 /* IEU1 Group */ + + bne,a,pt %XCC, 22b /* CTI */ + ldub [%o0], %o3 /* Load */ + retl /* CTI+IEU1 Group */ + clr %o0 /* IEU0 */ + +23: retl /* CTI+IEU1 Group */ + add %o0, -1, %o0 /* IEU0 */ +END(__memchr) + +weak_alias (__memchr, memchr) +libc_hidden_builtin_def (memchr) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/memcmp.S b/REORG.TODO/sysdeps/sparc/sparc64/memcmp.S new file mode 100644 index 0000000000..00ff2eec6b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/memcmp.S @@ -0,0 +1,142 @@ +/* Compare two memory blocks for differences in the first COUNT bytes. + For SPARC v9. + Copyright (C) 1998-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jan Vondrak <jvon4518@ss1000.ms.mff.cuni.cz> and + Jakub Jelinek <jj@ultra.linux.cz>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <asm/asi.h> +#ifndef XCC +#define XCC xcc +#define USE_BPR + .register %g2, #scratch + .register %g3, #scratch +#endif + + .text + .align 32 +ENTRY(memcmp) +#ifdef USE_BPR + brz,pn %o2, 3f /* CTI+IEU1 Group */ +#else + tst %o2 /* IEU1 Group */ + be,pn %XCC, 3f /* CTI */ +#endif + andcc %o0, 7, %g0 /* IEU1 Group */ + bne,pn %icc, 8f /* CTI */ +1: andcc %o1, 7, %g1 /* IEU1 Group */ + + bne,pn %icc, 10f /* CTI */ + mov 64, %g3 /* IEU0 */ + ldx [%o0], %g1 /* Load Group */ + sub %o1, %o0, %o1 /* IEU0 */ + + ldx [%o0 + %o1], %g2 /* Load Group */ + add %o0, 8, %o0 /* IEU0 */ +2: mov %g1, %o3 /* IEU0 Group */ + subcc %o2, 8, %o2 /* IEU1 */ + + bcs,pn %XCC, 5f /* CTI */ + ldxa [%o0] ASI_PNF, %g1 /* Load Group */ + mov %g2, %o4 /* IEU0 */ + ldxa [%o0 + %o1] ASI_PNF, %g2 /* Load Group */ + + cmp %o3, %o4 /* IEU1 */ + be,pt %xcc, 2b /* CTI */ + add %o0, 8, %o0 /* IEU0 */ +7: mov -1, %o0 /* IEU1 */ + + retl /* CTI+IEU1 Group */ + movgu %xcc, 1, %o0 /* Single Group */ +3: retl /* CTI+IEU1 Group */ + clr %o0 /* IEU0 */ + + .align 16 +5: mov %g2, %o4 /* IEU0 */ +6: cmp %o2, -8 /* IEU1 */ + be,pn %XCC, 3b /* CTI */ + sub %g0, %o2, %o2 /* IEU0 Group */ + + sllx %o2, 3, %o2 /* IEU0 Group */ + srlx %o3, %o2, %o3 /* IEU0 Group */ + srlx %o4, %o2, %o4 /* IEU0 Group */ + clr %o0 /* IEU1 */ + + cmp %o3, %o4 /* IEU1 Group */ + movgu %xcc, 1, %o0 /* Single Group */ + retl /* CTI+IEU1 Group */ + movlu %xcc, -1, %o0 /* Single Group */ + +8: ldub [%o0], %o3 /* Load */ + add %o0, 1, %o0 /* IEU0 */ + ldub [%o1], %o4 /* Load Group */ + add %o1, 1, %o1 /* IEU0 */ + +9: cmp %o3, %o4 /* IEU1 Group */ + bne,pn %xcc, 12f /* CTI */ + subcc %o2, 1, %o2 /* IEU1 Group */ + be,pn %XCC, 3b /* CTI */ + + lduba [%o0] ASI_PNF, %o3 /* Load */ + andcc %o0, 7, %g0 /* IEU1 Group */ + be,pn %icc, 1b /* CTI */ + lduba [%o1] ASI_PNF, %o4 /* Load */ + + add %o0, 1, %o0 /* IEU0 Group */ + ba,pt %xcc, 9b /* CTI */ + add %o1, 1, %o1 /* IEU1 */ + + .align 16 +12: mov -1, %o0 /* IEU0 Group */ + cmp %o3, %o4 /* IEU1 */ + retl /* CTI+IEU1 Group */ + movgu %xcc, 1, %o0 /* Single Group */ + + .align 16 + nop /* Stub */ +10: sllx %g1, 3, %g2 /* IEU0 Group */ + sub %o1, %g1, %o1 /* IEU1 */ + sub %g3, %g2, %g3 /* IEU0 Group */ + + ldxa [%o0] ASI_PNF, %g5 /* Load */ + sub %o1, %o0, %o1 /* IEU1 */ + ldxa [%o0 + %o1] ASI_PNF, %g4 /* Load Group */ + add %o0, 8, %o0 /* IEU0 */ + +11: sllx %g4, %g2, %o4 /* IEU0 Group */ + ldxa [%o0 + %o1] ASI_PNF, %g4 /* Load */ + srlx %g4, %g3, %o5 /* IEU0 Group */ + mov %g5, %o3 /* IEU1 */ + + ldxa [%o0] ASI_PNF, %g5 /* Load */ + subcc %o2, 8, %o2 /* IEU1 Group */ + bcs,pn %XCC, 6b /* CTI */ + or %o4, %o5, %o4 /* IEU0 */ + + cmp %o3, %o4 /* IEU1 Group */ + be,pt %xcc, 11b /* CTI */ + add %o0, 8, %o0 /* IEU0 */ + mov -1, %o0 /* IEU0 */ + + retl /* CTI+IEU1 Group */ + movgu %xcc, 1, %o0 /* Single Group */ +END(memcmp) + +#undef bcmp +weak_alias (memcmp, bcmp) +libc_hidden_builtin_def (memcmp) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/memcpy.S b/REORG.TODO/sysdeps/sparc/sparc64/memcpy.S new file mode 100644 index 0000000000..c1c0bf64d1 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/memcpy.S @@ -0,0 +1,580 @@ +/* Copy SIZE bytes from SRC to DEST. + For UltraSPARC. + Copyright (C) 1996-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller (davem@caip.rutgers.edu) and + Jakub Jelinek (jakub@redhat.com). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <asm/asi.h> +#ifndef XCC +#define USE_BPR + .register %g2, #scratch + .register %g3, #scratch + .register %g6, #scratch +#define XCC xcc +#endif +#define FPRS_FEF 4 + +#define FREG_FROB(f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + faligndata %f1, %f2, %f48; \ + faligndata %f2, %f3, %f50; \ + faligndata %f3, %f4, %f52; \ + faligndata %f4, %f5, %f54; \ + faligndata %f5, %f6, %f56; \ + faligndata %f6, %f7, %f58; \ + faligndata %f7, %f8, %f60; \ + faligndata %f8, %f9, %f62; + +#define MAIN_LOOP_CHUNK(src, dest, fdest, fsrc, len, jmptgt) \ + ldda [%src] %asi, %fdest; \ + add %src, 0x40, %src; \ + add %dest, 0x40, %dest; \ + subcc %len, 0x40, %len; \ + be,pn %xcc, jmptgt; \ + stda %fsrc, [%dest - 0x40] %asi; + +#define LOOP_CHUNK1(src, dest, len, branch_dest) \ + MAIN_LOOP_CHUNK(src, dest, f0, f48, len, branch_dest) +#define LOOP_CHUNK2(src, dest, len, branch_dest) \ + MAIN_LOOP_CHUNK(src, dest, f16, f48, len, branch_dest) +#define LOOP_CHUNK3(src, dest, len, branch_dest) \ + MAIN_LOOP_CHUNK(src, dest, f32, f48, len, branch_dest) + +#define STORE_SYNC(dest, fsrc) \ + stda %fsrc, [%dest] %asi; \ + add %dest, 0x40, %dest; + +#define STORE_JUMP(dest, fsrc, target) \ + stda %fsrc, [%dest] %asi; \ + add %dest, 0x40, %dest; \ + ba,pt %xcc, target; + +#define VISLOOP_PAD nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; + +#define FINISH_VISCHUNK(dest, f0, f1, left) \ + subcc %left, 8, %left; \ + bl,pn %xcc, 205f; \ + faligndata %f0, %f1, %f48; \ + std %f48, [%dest]; \ + add %dest, 8, %dest; + +#define UNEVEN_VISCHUNK(dest, f0, f1, left) \ + subcc %left, 8, %left; \ + bl,pn %xcc, 205f; \ + fsrc2 %f0, %f1; \ + ba,a,pt %xcc, 204f; + + /* Macros for non-VIS memcpy code. */ +#define MOVE_BIGCHUNK(src, dst, offset, t0, t1, t2, t3) \ + ldx [%src + offset + 0x00], %t0; \ + ldx [%src + offset + 0x08], %t1; \ + ldx [%src + offset + 0x10], %t2; \ + ldx [%src + offset + 0x18], %t3; \ + stw %t0, [%dst + offset + 0x04]; \ + srlx %t0, 32, %t0; \ + stw %t0, [%dst + offset + 0x00]; \ + stw %t1, [%dst + offset + 0x0c]; \ + srlx %t1, 32, %t1; \ + stw %t1, [%dst + offset + 0x08]; \ + stw %t2, [%dst + offset + 0x14]; \ + srlx %t2, 32, %t2; \ + stw %t2, [%dst + offset + 0x10]; \ + stw %t3, [%dst + offset + 0x1c]; \ + srlx %t3, 32, %t3; \ + stw %t3, [%dst + offset + 0x18]; + +#define MOVE_BIGALIGNCHUNK(src, dst, offset, t0, t1, t2, t3) \ + ldx [%src + offset + 0x00], %t0; \ + ldx [%src + offset + 0x08], %t1; \ + ldx [%src + offset + 0x10], %t2; \ + ldx [%src + offset + 0x18], %t3; \ + stx %t0, [%dst + offset + 0x00]; \ + stx %t1, [%dst + offset + 0x08]; \ + stx %t2, [%dst + offset + 0x10]; \ + stx %t3, [%dst + offset + 0x18]; \ + ldx [%src + offset + 0x20], %t0; \ + ldx [%src + offset + 0x28], %t1; \ + ldx [%src + offset + 0x30], %t2; \ + ldx [%src + offset + 0x38], %t3; \ + stx %t0, [%dst + offset + 0x20]; \ + stx %t1, [%dst + offset + 0x28]; \ + stx %t2, [%dst + offset + 0x30]; \ + stx %t3, [%dst + offset + 0x38]; + +#define MOVE_LASTCHUNK(src, dst, offset, t0, t1, t2, t3) \ + ldx [%src - offset - 0x10], %t0; \ + ldx [%src - offset - 0x08], %t1; \ + stw %t0, [%dst - offset - 0x0c]; \ + srlx %t0, 32, %t2; \ + stw %t2, [%dst - offset - 0x10]; \ + stw %t1, [%dst - offset - 0x04]; \ + srlx %t1, 32, %t3; \ + stw %t3, [%dst - offset - 0x08]; + +#define MOVE_LASTALIGNCHUNK(src, dst, offset, t0, t1) \ + ldx [%src - offset - 0x10], %t0; \ + ldx [%src - offset - 0x08], %t1; \ + stx %t0, [%dst - offset - 0x10]; \ + stx %t1, [%dst - offset - 0x08]; + + .text + .align 32 +ENTRY(__memcpy_large) +200: be,pt %xcc, 201f /* CTI */ + andcc %o0, 0x38, %g5 /* IEU1 Group */ + mov 8, %g1 /* IEU0 */ + sub %g1, %g2, %g2 /* IEU0 Group */ + andcc %o0, 1, %g0 /* IEU1 */ + be,pt %icc, 2f /* CTI */ + sub %o2, %g2, %o2 /* IEU0 Group */ +1: ldub [%o1], %o5 /* Load Group */ + add %o1, 1, %o1 /* IEU0 */ + add %o0, 1, %o0 /* IEU1 */ + subcc %g2, 1, %g2 /* IEU1 Group */ + be,pn %xcc, 3f /* CTI */ + stb %o5, [%o0 - 1] /* Store */ +2: ldub [%o1], %o5 /* Load Group */ + add %o0, 2, %o0 /* IEU0 */ + ldub [%o1 + 1], %g3 /* Load Group */ + subcc %g2, 2, %g2 /* IEU1 Group */ + stb %o5, [%o0 - 2] /* Store */ + add %o1, 2, %o1 /* IEU0 */ + bne,pt %xcc, 2b /* CTI Group */ + stb %g3, [%o0 - 1] /* Store */ +3: andcc %o0, 0x38, %g5 /* IEU1 Group */ +201: be,pt %icc, 202f /* CTI */ + mov 64, %g1 /* IEU0 */ + fsrc2 %f0, %f2 /* FPU */ + sub %g1, %g5, %g5 /* IEU0 Group */ + alignaddr %o1, %g0, %g1 /* GRU Group */ + ldd [%g1], %f4 /* Load Group */ + sub %o2, %g5, %o2 /* IEU0 */ +1: ldd [%g1 + 0x8], %f6 /* Load Group */ + add %g1, 0x8, %g1 /* IEU0 Group */ + subcc %g5, 8, %g5 /* IEU1 */ + faligndata %f4, %f6, %f0 /* GRU Group */ + std %f0, [%o0] /* Store */ + add %o1, 8, %o1 /* IEU0 Group */ + be,pn %xcc, 202f /* CTI */ + add %o0, 8, %o0 /* IEU1 */ + ldd [%g1 + 0x8], %f4 /* Load Group */ + add %g1, 8, %g1 /* IEU0 */ + subcc %g5, 8, %g5 /* IEU1 */ + faligndata %f6, %f4, %f0 /* GRU Group */ + std %f0, [%o0] /* Store */ + add %o1, 8, %o1 /* IEU0 */ + bne,pt %xcc, 1b /* CTI Group */ + add %o0, 8, %o0 /* IEU0 */ +202: membar #LoadStore | #StoreStore | #StoreLoad /* LSU Group */ + wr %g0, ASI_BLK_P, %asi /* LSU Group */ + subcc %o2, 0x40, %g6 /* IEU1 Group */ + mov %o1, %g1 /* IEU0 */ + andncc %g6, (0x40 - 1), %g6 /* IEU1 Group */ + srl %g1, 3, %g2 /* IEU0 */ + sub %o2, %g6, %g3 /* IEU0 Group */ + andn %o1, (0x40 - 1), %o1 /* IEU1 */ + and %g2, 7, %g2 /* IEU0 Group */ + andncc %g3, 0x7, %g3 /* IEU1 */ + fsrc2 %f0, %f2 /* FPU */ + sub %g3, 0x10, %g3 /* IEU0 Group */ + sub %o2, %g6, %o2 /* IEU1 */ + alignaddr %g1, %g0, %g0 /* GRU Group */ + add %g1, %g6, %g1 /* IEU0 Group */ + subcc %o2, %g3, %o2 /* IEU1 */ + ldda [%o1 + 0x00] %asi, %f0 /* LSU Group */ + add %g1, %g3, %g1 /* IEU0 */ + ldda [%o1 + 0x40] %asi, %f16 /* LSU Group */ + sub %g6, 0x80, %g6 /* IEU0 */ + ldda [%o1 + 0x80] %asi, %f32 /* LSU Group */ + /* Clk1 Group 8-( */ + /* Clk2 Group 8-( */ + /* Clk3 Group 8-( */ + /* Clk4 Group 8-( */ +203: rd %pc, %g5 /* PDU Group 8-( */ + addcc %g5, %lo(300f - 203b), %g5 /* IEU1 Group */ + sll %g2, 9, %g2 /* IEU0 */ + jmpl %g5 + %g2, %g0 /* CTI Group brk forced*/ + addcc %o1, 0xc0, %o1 /* IEU1 Group */ + + .align 512 /* OK, here comes the fun part... */ +300: FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16) LOOP_CHUNK1(o1, o0, g6, 301f) + FREG_FROB(f16,f18,f20,f22,f24,f26,f28,f30,f32) LOOP_CHUNK2(o1, o0, g6, 302f) + FREG_FROB(f32,f34,f36,f38,f40,f42,f44,f46,f0) LOOP_CHUNK3(o1, o0, g6, 303f) + b,pt %xcc, 300b+4; faligndata %f0, %f2, %f48 +301: FREG_FROB(f16,f18,f20,f22,f24,f26,f28,f30,f32) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f32,f34,f36,f38,f40,f42,f44,f46,f0) STORE_JUMP(o0, f48, 400f) membar #Sync +302: FREG_FROB(f32,f34,f36,f38,f40,f42,f44,f46,f0) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16) STORE_JUMP(o0, f48, 416f) membar #Sync +303: FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f16,f18,f20,f22,f24,f26,f28,f30,f32) STORE_JUMP(o0, f48, 432f) membar #Sync + VISLOOP_PAD +310: FREG_FROB(f2, f4, f6, f8, f10,f12,f14,f16,f18) LOOP_CHUNK1(o1, o0, g6, 311f) + FREG_FROB(f18,f20,f22,f24,f26,f28,f30,f32,f34) LOOP_CHUNK2(o1, o0, g6, 312f) + FREG_FROB(f34,f36,f38,f40,f42,f44,f46,f0, f2) LOOP_CHUNK3(o1, o0, g6, 313f) + b,pt %xcc, 310b+4; faligndata %f2, %f4, %f48 +311: FREG_FROB(f18,f20,f22,f24,f26,f28,f30,f32,f34) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f34,f36,f38,f40,f42,f44,f46,f0, f2) STORE_JUMP(o0, f48, 402f) membar #Sync +312: FREG_FROB(f34,f36,f38,f40,f42,f44,f46,f0, f2) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f2, f4, f6, f8, f10,f12,f14,f16,f18) STORE_JUMP(o0, f48, 418f) membar #Sync +313: FREG_FROB(f2, f4, f6, f8, f10,f12,f14,f16,f18) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f18,f20,f22,f24,f26,f28,f30,f32,f34) STORE_JUMP(o0, f48, 434f) membar #Sync + VISLOOP_PAD +320: FREG_FROB(f4, f6, f8, f10,f12,f14,f16,f18,f20) LOOP_CHUNK1(o1, o0, g6, 321f) + FREG_FROB(f20,f22,f24,f26,f28,f30,f32,f34,f36) LOOP_CHUNK2(o1, o0, g6, 322f) + FREG_FROB(f36,f38,f40,f42,f44,f46,f0, f2, f4) LOOP_CHUNK3(o1, o0, g6, 323f) + b,pt %xcc, 320b+4; faligndata %f4, %f6, %f48 +321: FREG_FROB(f20,f22,f24,f26,f28,f30,f32,f34,f36) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f36,f38,f40,f42,f44,f46,f0, f2, f4) STORE_JUMP(o0, f48, 404f) membar #Sync +322: FREG_FROB(f36,f38,f40,f42,f44,f46,f0, f2, f4) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f4, f6, f8, f10,f12,f14,f16,f18,f20) STORE_JUMP(o0, f48, 420f) membar #Sync +323: FREG_FROB(f4, f6, f8, f10,f12,f14,f16,f18,f20) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f20,f22,f24,f26,f28,f30,f32,f34,f36) STORE_JUMP(o0, f48, 436f) membar #Sync + VISLOOP_PAD +330: FREG_FROB(f6, f8, f10,f12,f14,f16,f18,f20,f22) LOOP_CHUNK1(o1, o0, g6, 331f) + FREG_FROB(f22,f24,f26,f28,f30,f32,f34,f36,f38) LOOP_CHUNK2(o1, o0, g6, 332f) + FREG_FROB(f38,f40,f42,f44,f46,f0, f2, f4, f6) LOOP_CHUNK3(o1, o0, g6, 333f) + b,pt %xcc, 330b+4; faligndata %f6, %f8, %f48 +331: FREG_FROB(f22,f24,f26,f28,f30,f32,f34,f36,f38) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f38,f40,f42,f44,f46,f0, f2, f4, f6) STORE_JUMP(o0, f48, 406f) membar #Sync +332: FREG_FROB(f38,f40,f42,f44,f46,f0, f2, f4, f6) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f6, f8, f10,f12,f14,f16,f18,f20,f22) STORE_JUMP(o0, f48, 422f) membar #Sync +333: FREG_FROB(f6, f8, f10,f12,f14,f16,f18,f20,f22) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f22,f24,f26,f28,f30,f32,f34,f36,f38) STORE_JUMP(o0, f48, 438f) membar #Sync + VISLOOP_PAD +340: FREG_FROB(f8, f10,f12,f14,f16,f18,f20,f22,f24) LOOP_CHUNK1(o1, o0, g6, 341f) + FREG_FROB(f24,f26,f28,f30,f32,f34,f36,f38,f40) LOOP_CHUNK2(o1, o0, g6, 342f) + FREG_FROB(f40,f42,f44,f46,f0, f2, f4, f6, f8) LOOP_CHUNK3(o1, o0, g6, 343f) + b,pt %xcc, 340b+4; faligndata %f8, %f10, %f48 +341: FREG_FROB(f24,f26,f28,f30,f32,f34,f36,f38,f40) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f40,f42,f44,f46,f0, f2, f4, f6, f8) STORE_JUMP(o0, f48, 408f) membar #Sync +342: FREG_FROB(f40,f42,f44,f46,f0, f2, f4, f6, f8) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f8, f10,f12,f14,f16,f18,f20,f22,f24) STORE_JUMP(o0, f48, 424f) membar #Sync +343: FREG_FROB(f8, f10,f12,f14,f16,f18,f20,f22,f24) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f24,f26,f28,f30,f32,f34,f36,f38,f40) STORE_JUMP(o0, f48, 440f) membar #Sync + VISLOOP_PAD +350: FREG_FROB(f10,f12,f14,f16,f18,f20,f22,f24,f26) LOOP_CHUNK1(o1, o0, g6, 351f) + FREG_FROB(f26,f28,f30,f32,f34,f36,f38,f40,f42) LOOP_CHUNK2(o1, o0, g6, 352f) + FREG_FROB(f42,f44,f46,f0, f2, f4, f6, f8, f10) LOOP_CHUNK3(o1, o0, g6, 353f) + b,pt %xcc, 350b+4; faligndata %f10, %f12, %f48 +351: FREG_FROB(f26,f28,f30,f32,f34,f36,f38,f40,f42) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f42,f44,f46,f0, f2, f4, f6, f8, f10) STORE_JUMP(o0, f48, 410f) membar #Sync +352: FREG_FROB(f42,f44,f46,f0, f2, f4, f6, f8, f10) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f10,f12,f14,f16,f18,f20,f22,f24,f26) STORE_JUMP(o0, f48, 426f) membar #Sync +353: FREG_FROB(f10,f12,f14,f16,f18,f20,f22,f24,f26) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f26,f28,f30,f32,f34,f36,f38,f40,f42) STORE_JUMP(o0, f48, 442f) membar #Sync + VISLOOP_PAD +360: FREG_FROB(f12,f14,f16,f18,f20,f22,f24,f26,f28) LOOP_CHUNK1(o1, o0, g6, 361f) + FREG_FROB(f28,f30,f32,f34,f36,f38,f40,f42,f44) LOOP_CHUNK2(o1, o0, g6, 362f) + FREG_FROB(f44,f46,f0, f2, f4, f6, f8, f10,f12) LOOP_CHUNK3(o1, o0, g6, 363f) + b,pt %xcc, 360b+4; faligndata %f12, %f14, %f48 +361: FREG_FROB(f28,f30,f32,f34,f36,f38,f40,f42,f44) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f44,f46,f0, f2, f4, f6, f8, f10,f12) STORE_JUMP(o0, f48, 412f) membar #Sync +362: FREG_FROB(f44,f46,f0, f2, f4, f6, f8, f10,f12) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f12,f14,f16,f18,f20,f22,f24,f26,f28) STORE_JUMP(o0, f48, 428f) membar #Sync +363: FREG_FROB(f12,f14,f16,f18,f20,f22,f24,f26,f28) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f28,f30,f32,f34,f36,f38,f40,f42,f44) STORE_JUMP(o0, f48, 444f) membar #Sync + VISLOOP_PAD +370: FREG_FROB(f14,f16,f18,f20,f22,f24,f26,f28,f30) LOOP_CHUNK1(o1, o0, g6, 371f) + FREG_FROB(f30,f32,f34,f36,f38,f40,f42,f44,f46) LOOP_CHUNK2(o1, o0, g6, 372f) + FREG_FROB(f46,f0, f2, f4, f6, f8, f10,f12,f14) LOOP_CHUNK3(o1, o0, g6, 373f) + b,pt %xcc, 370b+4; faligndata %f14, %f16, %f48 +371: FREG_FROB(f30,f32,f34,f36,f38,f40,f42,f44,f46) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f46,f0, f2, f4, f6, f8, f10,f12,f14) STORE_JUMP(o0, f48, 414f) membar #Sync +372: FREG_FROB(f46,f0, f2, f4, f6, f8, f10,f12,f14) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f14,f16,f18,f20,f22,f24,f26,f28,f30) STORE_JUMP(o0, f48, 430f) membar #Sync +373: FREG_FROB(f14,f16,f18,f20,f22,f24,f26,f28,f30) STORE_SYNC(o0, f48) membar #Sync + FREG_FROB(f30,f32,f34,f36,f38,f40,f42,f44,f46) STORE_JUMP(o0, f48, 446f) membar #Sync + VISLOOP_PAD +400: FINISH_VISCHUNK(o0, f0, f2, g3) +402: FINISH_VISCHUNK(o0, f2, f4, g3) +404: FINISH_VISCHUNK(o0, f4, f6, g3) +406: FINISH_VISCHUNK(o0, f6, f8, g3) +408: FINISH_VISCHUNK(o0, f8, f10, g3) +410: FINISH_VISCHUNK(o0, f10, f12, g3) +412: FINISH_VISCHUNK(o0, f12, f14, g3) +414: UNEVEN_VISCHUNK(o0, f14, f0, g3) +416: FINISH_VISCHUNK(o0, f16, f18, g3) +418: FINISH_VISCHUNK(o0, f18, f20, g3) +420: FINISH_VISCHUNK(o0, f20, f22, g3) +422: FINISH_VISCHUNK(o0, f22, f24, g3) +424: FINISH_VISCHUNK(o0, f24, f26, g3) +426: FINISH_VISCHUNK(o0, f26, f28, g3) +428: FINISH_VISCHUNK(o0, f28, f30, g3) +430: UNEVEN_VISCHUNK(o0, f30, f0, g3) +432: FINISH_VISCHUNK(o0, f32, f34, g3) +434: FINISH_VISCHUNK(o0, f34, f36, g3) +436: FINISH_VISCHUNK(o0, f36, f38, g3) +438: FINISH_VISCHUNK(o0, f38, f40, g3) +440: FINISH_VISCHUNK(o0, f40, f42, g3) +442: FINISH_VISCHUNK(o0, f42, f44, g3) +444: FINISH_VISCHUNK(o0, f44, f46, g3) +446: UNEVEN_VISCHUNK(o0, f46, f0, g3) +204: ldd [%o1], %f2 /* Load Group */ + add %o1, 8, %o1 /* IEU0 */ + subcc %g3, 8, %g3 /* IEU1 */ + faligndata %f0, %f2, %f8 /* GRU Group */ + std %f8, [%o0] /* Store */ + bl,pn %xcc, 205f /* CTI */ + add %o0, 8, %o0 /* IEU0 Group */ + ldd [%o1], %f0 /* Load Group */ + add %o1, 8, %o1 /* IEU0 */ + subcc %g3, 8, %g3 /* IEU1 */ + faligndata %f2, %f0, %f8 /* GRU Group */ + std %f8, [%o0] /* Store */ + bge,pt %xcc, 204b /* CTI */ + add %o0, 8, %o0 /* IEU0 Group */ +205: brz,pt %o2, 207f /* CTI Group */ + mov %g1, %o1 /* IEU0 */ +206: ldub [%o1], %g5 /* LOAD */ + add %o1, 1, %o1 /* IEU0 */ + add %o0, 1, %o0 /* IEU1 */ + subcc %o2, 1, %o2 /* IEU1 */ + bne,pt %xcc, 206b /* CTI */ + stb %g5, [%o0 - 1] /* Store Group */ +207: membar #StoreLoad | #StoreStore /* LSU Group */ + wr %g0, FPRS_FEF, %fprs + retl + mov %g4, %o0 + +208: andcc %o2, 1, %g0 /* IEU1 Group */ + be,pt %icc, 2f+4 /* CTI */ +1: ldub [%o1], %g5 /* LOAD Group */ + add %o1, 1, %o1 /* IEU0 */ + add %o0, 1, %o0 /* IEU1 */ + subcc %o2, 1, %o2 /* IEU1 Group */ + be,pn %xcc, 209f /* CTI */ + stb %g5, [%o0 - 1] /* Store */ +2: ldub [%o1], %g5 /* LOAD Group */ + add %o0, 2, %o0 /* IEU0 */ + ldub [%o1 + 1], %o5 /* LOAD Group */ + add %o1, 2, %o1 /* IEU0 */ + subcc %o2, 2, %o2 /* IEU1 Group */ + stb %g5, [%o0 - 2] /* Store */ + bne,pt %xcc, 2b /* CTI */ + stb %o5, [%o0 - 1] /* Store */ +209: retl + mov %g4, %o0 +END(__memcpy_large) + +ENTRY(__mempcpy) + ba,pt %xcc, 210f + add %o0, %o2, %g4 +END(__mempcpy) + + .align 32 +ENTRY(memcpy) + mov %o0, %g4 /* IEU0 Group */ +210: +#ifndef USE_BPR + srl %o2, 0, %o2 /* IEU1 */ +#endif + brz,pn %o2, 209b /* CTI Group */ +218: cmp %o2, 15 /* IEU1 */ + bleu,pn %xcc, 208b /* CTI Group */ + cmp %o2, (64 * 6) /* IEU1 */ + bgeu,pn %xcc, 200b /* CTI Group */ + andcc %o0, 7, %g2 /* IEU1 */ + sub %o0, %o1, %g5 /* IEU0 */ + andcc %g5, 3, %o5 /* IEU1 Group */ + bne,pn %xcc, 212f /* CTI */ + andcc %o1, 3, %g0 /* IEU1 Group */ + be,a,pt %xcc, 216f /* CTI */ + andcc %o1, 4, %g0 /* IEU1 Group */ + andcc %o1, 1, %g0 /* IEU1 Group */ + be,pn %xcc, 4f /* CTI */ + andcc %o1, 2, %g0 /* IEU1 Group */ + ldub [%o1], %g2 /* Load Group */ + add %o1, 1, %o1 /* IEU0 */ + add %o0, 1, %o0 /* IEU1 */ + sub %o2, 1, %o2 /* IEU0 Group */ + bne,pn %xcc, 5f /* CTI Group */ + stb %g2, [%o0 - 1] /* Store */ +4: lduh [%o1], %g2 /* Load Group */ + add %o1, 2, %o1 /* IEU0 */ + add %o0, 2, %o0 /* IEU1 */ + sub %o2, 2, %o2 /* IEU0 */ + sth %g2, [%o0 - 2] /* Store Group + bubble */ +5: andcc %o1, 4, %g0 /* IEU1 */ +216: be,a,pn %xcc, 2f /* CTI */ + andcc %o2, -128, %g6 /* IEU1 Group */ + lduw [%o1], %g5 /* Load Group */ + add %o1, 4, %o1 /* IEU0 */ + add %o0, 4, %o0 /* IEU1 */ + sub %o2, 4, %o2 /* IEU0 Group */ + stw %g5, [%o0 - 4] /* Store */ + andcc %o2, -128, %g6 /* IEU1 Group */ +2: be,pn %xcc, 215f /* CTI */ + andcc %o0, 4, %g0 /* IEU1 Group */ + be,pn %xcc, 82f + 4 /* CTI Group */ +5: MOVE_BIGCHUNK(o1, o0, 0x00, g1, g3, g5, o5) + MOVE_BIGCHUNK(o1, o0, 0x20, g1, g3, g5, o5) + MOVE_BIGCHUNK(o1, o0, 0x40, g1, g3, g5, o5) + MOVE_BIGCHUNK(o1, o0, 0x60, g1, g3, g5, o5) +35: subcc %g6, 128, %g6 /* IEU1 Group */ + add %o1, 128, %o1 /* IEU0 */ + bne,pt %xcc, 5b /* CTI */ + add %o0, 128, %o0 /* IEU0 Group */ +215: andcc %o2, 0x70, %g6 /* IEU1 Group */ +41: be,pn %xcc, 80f /* CTI */ + andcc %o2, 8, %g0 /* IEU1 Group */ + /* Clk1 8-( */ + /* Clk2 8-( */ + /* Clk3 8-( */ + /* Clk4 8-( */ +79: rd %pc, %o5 /* PDU Group */ + sll %g6, 1, %g5 /* IEU0 Group */ + add %o1, %g6, %o1 /* IEU1 */ + sub %o5, %g5, %o5 /* IEU0 Group */ + jmpl %o5 + %lo(80f - 79b), %g0 /* CTI Group brk forced*/ + add %o0, %g6, %o0 /* IEU0 Group */ +36: MOVE_LASTCHUNK(o1, o0, 0x60, g2, g3, g5, o5) + MOVE_LASTCHUNK(o1, o0, 0x50, g2, g3, g5, o5) + MOVE_LASTCHUNK(o1, o0, 0x40, g2, g3, g5, o5) + MOVE_LASTCHUNK(o1, o0, 0x30, g2, g3, g5, o5) + MOVE_LASTCHUNK(o1, o0, 0x20, g2, g3, g5, o5) + MOVE_LASTCHUNK(o1, o0, 0x10, g2, g3, g5, o5) + MOVE_LASTCHUNK(o1, o0, 0x00, g2, g3, g5, o5) +80: be,pt %xcc, 81f /* CTI */ + andcc %o2, 4, %g0 /* IEU1 */ + ldx [%o1], %g2 /* Load Group */ + add %o0, 8, %o0 /* IEU0 */ + stw %g2, [%o0 - 0x4] /* Store Group */ + add %o1, 8, %o1 /* IEU1 */ + srlx %g2, 32, %g2 /* IEU0 Group */ + stw %g2, [%o0 - 0x8] /* Store */ +81: be,pt %xcc, 1f /* CTI */ + andcc %o2, 2, %g0 /* IEU1 Group */ + lduw [%o1], %g2 /* Load Group */ + add %o1, 4, %o1 /* IEU0 */ + stw %g2, [%o0] /* Store Group */ + add %o0, 4, %o0 /* IEU0 */ +1: be,pt %xcc, 1f /* CTI */ + andcc %o2, 1, %g0 /* IEU1 Group */ + lduh [%o1], %g2 /* Load Group */ + add %o1, 2, %o1 /* IEU0 */ + sth %g2, [%o0] /* Store Group */ + add %o0, 2, %o0 /* IEU0 */ +1: be,pt %xcc, 211f /* CTI */ + nop /* IEU1 */ + ldub [%o1], %g2 /* Load Group */ + stb %g2, [%o0] /* Store Group + bubble */ +211: retl + mov %g4, %o0 + +82: MOVE_BIGALIGNCHUNK(o1, o0, 0x00, g1, g3, g5, o5) + MOVE_BIGALIGNCHUNK(o1, o0, 0x40, g1, g3, g5, o5) +37: subcc %g6, 128, %g6 /* IEU1 Group */ + add %o1, 128, %o1 /* IEU0 */ + bne,pt %xcc, 82b /* CTI */ + add %o0, 128, %o0 /* IEU0 Group */ + andcc %o2, 0x70, %g6 /* IEU1 */ + be,pn %xcc, 84f /* CTI */ + andcc %o2, 8, %g0 /* IEU1 Group */ + /* Clk1 8-( */ + /* Clk2 8-( */ + /* Clk3 8-( */ + /* Clk4 8-( */ +83: rd %pc, %o5 /* PDU Group */ + add %o1, %g6, %o1 /* IEU0 Group */ + sub %o5, %g6, %o5 /* IEU1 */ + jmpl %o5 + %lo(84f - 83b), %g0 /* CTI Group brk forced*/ + add %o0, %g6, %o0 /* IEU0 Group */ +38: MOVE_LASTALIGNCHUNK(o1, o0, 0x60, g2, g3) + MOVE_LASTALIGNCHUNK(o1, o0, 0x50, g2, g3) + MOVE_LASTALIGNCHUNK(o1, o0, 0x40, g2, g3) + MOVE_LASTALIGNCHUNK(o1, o0, 0x30, g2, g3) + MOVE_LASTALIGNCHUNK(o1, o0, 0x20, g2, g3) + MOVE_LASTALIGNCHUNK(o1, o0, 0x10, g2, g3) + MOVE_LASTALIGNCHUNK(o1, o0, 0x00, g2, g3) +84: be,pt %xcc, 85f /* CTI Group */ + andcc %o2, 4, %g0 /* IEU1 */ + ldx [%o1], %g2 /* Load Group */ + add %o0, 8, %o0 /* IEU0 */ + add %o1, 8, %o1 /* IEU0 Group */ + stx %g2, [%o0 - 0x8] /* Store */ +85: be,pt %xcc, 1f /* CTI */ + andcc %o2, 2, %g0 /* IEU1 Group */ + lduw [%o1], %g2 /* Load Group */ + add %o0, 4, %o0 /* IEU0 */ + add %o1, 4, %o1 /* IEU0 Group */ + stw %g2, [%o0 - 0x4] /* Store */ +1: be,pt %xcc, 1f /* CTI */ + andcc %o2, 1, %g0 /* IEU1 Group */ + lduh [%o1], %g2 /* Load Group */ + add %o0, 2, %o0 /* IEU0 */ + add %o1, 2, %o1 /* IEU0 Group */ + sth %g2, [%o0 - 0x2] /* Store */ +1: be,pt %xcc, 1f /* CTI */ + nop /* IEU0 Group */ + ldub [%o1], %g2 /* Load Group */ + stb %g2, [%o0] /* Store Group + bubble */ +1: retl + mov %g4, %o0 + +212: brz,pt %g2, 2f /* CTI Group */ + mov 8, %g1 /* IEU0 */ + sub %g1, %g2, %g2 /* IEU0 Group */ + sub %o2, %g2, %o2 /* IEU0 Group */ +1: ldub [%o1], %g5 /* Load Group */ + add %o1, 1, %o1 /* IEU0 */ + add %o0, 1, %o0 /* IEU1 */ + subcc %g2, 1, %g2 /* IEU1 Group */ + bne,pt %xcc, 1b /* CTI */ + stb %g5, [%o0 - 1] /* Store */ +2: andn %o2, 7, %g5 /* IEU0 Group */ + and %o2, 7, %o2 /* IEU1 */ + fsrc2 %f0, %f2 /* FPU */ + alignaddr %o1, %g0, %g1 /* GRU Group */ + ldd [%g1], %f4 /* Load Group */ +1: ldd [%g1 + 0x8], %f6 /* Load Group */ + add %g1, 0x8, %g1 /* IEU0 Group */ + subcc %g5, 8, %g5 /* IEU1 */ + faligndata %f4, %f6, %f0 /* GRU Group */ + std %f0, [%o0] /* Store */ + add %o1, 8, %o1 /* IEU0 Group */ + be,pn %xcc, 213f /* CTI */ + add %o0, 8, %o0 /* IEU1 */ + ldd [%g1 + 0x8], %f4 /* Load Group */ + add %g1, 8, %g1 /* IEU0 */ + subcc %g5, 8, %g5 /* IEU1 */ + faligndata %f6, %f4, %f0 /* GRU Group */ + std %f0, [%o0] /* Store */ + add %o1, 8, %o1 /* IEU0 */ + bne,pn %xcc, 1b /* CTI Group */ + add %o0, 8, %o0 /* IEU0 */ +213: brz,pn %o2, 214f /* CTI Group */ + nop /* IEU0 */ + ldub [%o1], %g5 /* LOAD */ + add %o1, 1, %o1 /* IEU0 */ + add %o0, 1, %o0 /* IEU1 */ + subcc %o2, 1, %o2 /* IEU1 */ + bne,pt %xcc, 206b /* CTI */ + stb %g5, [%o0 - 1] /* Store Group */ +214: wr %g0, FPRS_FEF, %fprs + retl + mov %g4, %o0 +END(memcpy) + +libc_hidden_builtin_def (memcpy) + +libc_hidden_def (__mempcpy) +weak_alias (__mempcpy, mempcpy) +libc_hidden_builtin_def (mempcpy) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/memset.S b/REORG.TODO/sysdeps/sparc/sparc64/memset.S new file mode 100644 index 0000000000..5664436a51 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/memset.S @@ -0,0 +1,314 @@ +/* Set a block of memory to some byte value. + For UltraSPARC. + Copyright (C) 1996-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller (davem@caip.rutgers.edu) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <asm/asi.h> +#ifndef XCC +#define XCC xcc +#define USE_BPR +#endif +#define FPRS_FEF 4 + +#define SET_BLOCKS(base, offset, source) \ + stx source, [base - offset - 0x18]; \ + stx source, [base - offset - 0x10]; \ + stx source, [base - offset - 0x08]; \ + stx source, [base - offset - 0x00]; + + /* Well, memset is a lot easier to get right than bcopy... */ + .text + .align 32 +ENTRY(memset) + andcc %o1, 0xff, %o1 + mov %o0, %o5 + be,a,pt %icc, 50f +#ifndef USE_BPR + srl %o2, 0, %o1 +#else + mov %o2, %o1 +#endif + cmp %o2, 7 +#ifndef USE_BPR + srl %o2, 0, %o2 +#endif + bleu,pn %XCC, 17f + andcc %o0, 3, %g5 + be,pt %xcc, 4f + and %o1, 0xff, %o1 + cmp %g5, 3 + be,pn %xcc, 2f + stb %o1, [%o0 + 0x00] + cmp %g5, 2 + be,pt %xcc, 2f + stb %o1, [%o0 + 0x01] + stb %o1, [%o0 + 0x02] +2: sub %g5, 4, %g5 + sub %o0, %g5, %o0 + add %o2, %g5, %o2 +4: sllx %o1, 8, %g1 + andcc %o0, 4, %g0 + or %o1, %g1, %o1 + sllx %o1, 16, %g1 + or %o1, %g1, %o1 + be,pt %xcc, 2f + sllx %o1, 32, %g1 + stw %o1, [%o0] + sub %o2, 4, %o2 + add %o0, 4, %o0 +2: cmp %o2, 128 + or %o1, %g1, %o1 + blu,pn %xcc, 9f + andcc %o0, 0x38, %g5 + be,pn %icc, 6f + mov 64, %o4 + andcc %o0, 8, %g0 + be,pn %icc, 1f + sub %o4, %g5, %o4 + stx %o1, [%o0] + add %o0, 8, %o0 +1: andcc %o4, 16, %g0 + be,pn %icc, 1f + sub %o2, %o4, %o2 + stx %o1, [%o0] + stx %o1, [%o0 + 8] + add %o0, 16, %o0 +1: andcc %o4, 32, %g0 + be,pn %icc, 7f + andncc %o2, 0x3f, %o3 + stw %o1, [%o0] + stw %o1, [%o0 + 4] + stw %o1, [%o0 + 8] + stw %o1, [%o0 + 12] + stw %o1, [%o0 + 16] + stw %o1, [%o0 + 20] + stw %o1, [%o0 + 24] + stw %o1, [%o0 + 28] + add %o0, 32, %o0 +7: be,pn %xcc, 9f + nop + ldd [%o0 - 8], %f0 +18: wr %g0, ASI_BLK_P, %asi + membar #StoreStore | #LoadStore + andcc %o3, 0xc0, %g5 + and %o2, 0x3f, %o2 + fsrc2 %f0, %f2 + fsrc2 %f0, %f4 + andn %o3, 0xff, %o3 + fsrc2 %f0, %f6 + cmp %g5, 64 + fsrc2 %f0, %f8 + fsrc2 %f0, %f10 + fsrc2 %f0, %f12 + brz,pn %g5, 10f + fsrc2 %f0, %f14 + be,pn %icc, 2f + stda %f0, [%o0 + 0x00] %asi + cmp %g5, 128 + be,pn %icc, 2f + stda %f0, [%o0 + 0x40] %asi + stda %f0, [%o0 + 0x80] %asi +2: brz,pn %o3, 12f + add %o0, %g5, %o0 +10: stda %f0, [%o0 + 0x00] %asi + stda %f0, [%o0 + 0x40] %asi + stda %f0, [%o0 + 0x80] %asi + stda %f0, [%o0 + 0xc0] %asi +11: subcc %o3, 256, %o3 + bne,pt %xcc, 10b + add %o0, 256, %o0 +12: wr %g0, FPRS_FEF, %fprs + membar #StoreLoad | #StoreStore +9: andcc %o2, 0x78, %g5 + be,pn %xcc, 13f + andcc %o2, 7, %o2 +14: rd %pc, %o4 + srl %g5, 1, %o3 + sub %o4, %o3, %o4 + jmpl %o4 + (13f - 14b), %g0 + add %o0, %g5, %o0 +12: SET_BLOCKS (%o0, 0x68, %o1) + SET_BLOCKS (%o0, 0x48, %o1) + SET_BLOCKS (%o0, 0x28, %o1) + SET_BLOCKS (%o0, 0x08, %o1) +13: be,pn %xcc, 8f + andcc %o2, 4, %g0 + be,pn %xcc, 1f + andcc %o2, 2, %g0 + stw %o1, [%o0] + add %o0, 4, %o0 +1: be,pn %xcc, 1f + andcc %o2, 1, %g0 + sth %o1, [%o0] + add %o0, 2, %o0 +1: bne,a,pn %xcc, 8f + stb %o1, [%o0] +8: retl + mov %o5, %o0 +17: brz,pn %o2, 0f +8: add %o0, 1, %o0 + subcc %o2, 1, %o2 + bne,pt %xcc, 8b + stb %o1, [%o0 - 1] +0: retl + mov %o5, %o0 + +6: stx %o1, [%o0] + andncc %o2, 0x3f, %o3 + be,pn %xcc, 9b + nop + ba,pt %xcc, 18b + ldd [%o0], %f0 +END(memset) +libc_hidden_builtin_def (memset) + +#define ZERO_BLOCKS(base, offset, source) \ + stx source, [base - offset - 0x38]; \ + stx source, [base - offset - 0x30]; \ + stx source, [base - offset - 0x28]; \ + stx source, [base - offset - 0x20]; \ + stx source, [base - offset - 0x18]; \ + stx source, [base - offset - 0x10]; \ + stx source, [base - offset - 0x08]; \ + stx source, [base - offset - 0x00]; + + .text + .align 32 +ENTRY(__bzero) +#ifndef USE_BPR + srl %o1, 0, %o1 +#endif + mov %o0, %o5 +50: cmp %o1, 7 + bleu,pn %xcc, 17f + andcc %o0, 3, %o2 + be,a,pt %xcc, 4f + andcc %o0, 4, %g0 + cmp %o2, 3 + be,pn %xcc, 2f + stb %g0, [%o0 + 0x00] + cmp %o2, 2 + be,pt %xcc, 2f + stb %g0, [%o0 + 0x01] + stb %g0, [%o0 + 0x02] +2: sub %o2, 4, %o2 + sub %o0, %o2, %o0 + add %o1, %o2, %o1 + andcc %o0, 4, %g0 +4: be,pt %xcc, 2f + cmp %o1, 128 + stw %g0, [%o0] + sub %o1, 4, %o1 + add %o0, 4, %o0 +2: blu,pn %xcc, 9f + andcc %o0, 0x38, %o2 + be,pn %icc, 6f + mov 64, %o4 + andcc %o0, 8, %g0 + be,pn %icc, 1f + sub %o4, %o2, %o4 + stx %g0, [%o0] + add %o0, 8, %o0 +1: andcc %o4, 16, %g0 + be,pn %icc, 1f + sub %o1, %o4, %o1 + stx %g0, [%o0] + stx %g0, [%o0 + 8] + add %o0, 16, %o0 +1: andcc %o4, 32, %g0 + be,pn %icc, 7f + andncc %o1, 0x3f, %o3 + stx %g0, [%o0] + stx %g0, [%o0 + 8] + stx %g0, [%o0 + 16] + stx %g0, [%o0 + 24] + add %o0, 32, %o0 +6: andncc %o1, 0x3f, %o3 +7: be,pn %xcc, 9f + wr %g0, ASI_BLK_P, %asi + membar #StoreLoad | #StoreStore | #LoadStore + fzero %f0 + andcc %o3, 0xc0, %o2 + and %o1, 0x3f, %o1 + fzero %f2 + andn %o3, 0xff, %o3 + faddd %f0, %f2, %f4 + fmuld %f0, %f2, %f6 + cmp %o2, 64 + faddd %f0, %f2, %f8 + fmuld %f0, %f2, %f10 + faddd %f0, %f2, %f12 + brz,pn %o2, 10f + fmuld %f0, %f2, %f14 + be,pn %icc, 2f + stda %f0, [%o0 + 0x00] %asi + cmp %o2, 128 + be,pn %icc, 2f + stda %f0, [%o0 + 0x40] %asi + stda %f0, [%o0 + 0x80] %asi +2: brz,pn %o3, 12f + add %o0, %o2, %o0 +10: stda %f0, [%o0 + 0x00] %asi + stda %f0, [%o0 + 0x40] %asi + stda %f0, [%o0 + 0x80] %asi + stda %f0, [%o0 + 0xc0] %asi +11: subcc %o3, 256, %o3 + bne,pt %xcc, 10b + add %o0, 256, %o0 +12: wr %g0, FPRS_FEF, %fprs + membar #StoreLoad | #StoreStore +9: andcc %o1, 0xf8, %o2 + be,pn %xcc, 13f + andcc %o1, 7, %o1 +14: rd %pc, %o4 + srl %o2, 1, %o3 + sub %o4, %o3, %o4 + jmpl %o4 + (13f - 14b), %g0 + add %o0, %o2, %o0 +12: ZERO_BLOCKS (%o0, 0xc8, %g0) + ZERO_BLOCKS (%o0, 0x88, %g0) + ZERO_BLOCKS (%o0, 0x48, %g0) + ZERO_BLOCKS (%o0, 0x08, %g0) +13: be,pn %xcc, 8f + andcc %o1, 4, %g0 + be,pn %xcc, 1f + andcc %o1, 2, %g0 + stw %g0, [%o0] + add %o0, 4, %o0 +1: be,pn %xcc, 1f + andcc %o1, 1, %g0 + sth %g0, [%o0] + add %o0, 2, %o0 +1: bne,a,pn %xcc, 8f + stb %g0, [%o0] +8: retl + mov %o5, %o0 +17: be,pn %xcc, 13b + orcc %o1, 0, %g0 + be,pn %xcc, 0f +8: add %o0, 1, %o0 + subcc %o1, 1, %o1 + bne,pt %xcc, 8b + stb %g0, [%o0 - 1] +0: retl + mov %o5, %o0 +END(__bzero) + +weak_alias (__bzero, bzero) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/mul_1.S b/REORG.TODO/sysdeps/sparc/sparc64/mul_1.S new file mode 100644 index 0000000000..0a32882c1c --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/mul_1.S @@ -0,0 +1,82 @@ +/* SPARC v9 __mpn_mul_1 -- Multiply a limb vector with a single limb and + store the product in a second limb vector. + + Copyright (C) 1995-2017 Free Software Foundation, Inc. + + This file is part of the GNU MP Library. + + The GNU MP Library is free software; you can redistribute it and/or modify + it under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation; either version 2.1 of the License, or (at your + option) any later version. + + The GNU MP Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with the GNU MP Library; see the file COPYING.LIB. If not, + see <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + +/* INPUT PARAMETERS + res_ptr o0 + s1_ptr o1 + size o2 + s2_limb o3 */ + +ENTRY(__mpn_mul_1) + !#PROLOGUE# 0 + save %sp,-192,%sp + !#PROLOGUE# 1 + + sub %g0,%i2,%o7 + sllx %o7,3,%g5 + sub %i1,%g5,%o3 + sub %i0,%g5,%o4 + mov 0,%o0 ! zero cy_limb + + srl %i3,0,%o1 ! extract low 32 bits of s2_limb + srlx %i3,32,%i3 ! extract high 32 bits of s2_limb + mov 1,%o2 + sllx %o2,32,%o2 ! o2 = 0x100000000 + + ! hi ! + ! mid-1 ! + ! mid-2 ! + ! lo ! +.Loop: + sllx %o7,3,%g1 + ldx [%o3+%g1],%g5 + srl %g5,0,%i0 ! zero hi bits + srlx %g5,32,%g5 + mulx %o1,%i0,%i4 ! lo product + mulx %i3,%i0,%i1 ! mid-1 product + mulx %o1,%g5,%l2 ! mid-2 product + mulx %i3,%g5,%i5 ! hi product + srlx %i4,32,%i0 ! extract high 32 bits of lo product... + add %i1,%i0,%i1 ! ...and add it to the mid-1 product + addcc %i1,%l2,%i1 ! add mid products + mov 0,%l0 ! we need the carry from that add... + movcs %xcc,%o2,%l0 ! ...compute it and... + add %i5,%l0,%i5 ! ...add to bit 32 of the hi product + sllx %i1,32,%i0 ! align low bits of mid product + srl %i4,0,%g5 ! zero high 32 bits of lo product + add %i0,%g5,%i0 ! combine into low 64 bits of result + srlx %i1,32,%i1 ! extract high bits of mid product... + add %i5,%i1,%i1 ! ...and add them to the high result + addcc %i0,%o0,%i0 ! add cy_limb to low 64 bits of result + mov 0,%g5 + movcs %xcc,1,%g5 + addcc %o7,1,%o7 + stx %i0,[%o4+%g1] + bne,pt %xcc,.Loop + add %i1,%g5,%o0 ! compute new cy_limb + + jmpl %i7+8,%g0 + restore %o0,%g0,%o0 + +END(__mpn_mul_1) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/Makefile b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/Makefile new file mode 100644 index 0000000000..55b757f9ad --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/Makefile @@ -0,0 +1,21 @@ +ifeq ($(subdir),crypt) +libcrypt-sysdep_routines += md5-crop sha256-crop sha512-crop +endif + +ifeq ($(subdir),locale) +localedef-aux += md5-crop +endif + +ifeq ($(subdir),string) +sysdep_routines += memcpy-ultra3 memcpy-niagara1 memcpy-niagara2 \ + memset-niagara1 memcpy-niagara4 memset-niagara4 +endif + +ifeq ($(subdir),stdlib) +sysdep_routines += mul_1-vis3 addmul_1-vis3 submul_1-vis3 add_n-vis3 sub_n-vis3 +endif + +ifeq ($(subdir),math) +gmp-sysdep_routines = mul_1-vis3 addmul_1-vis3 submul_1-vis3 add_n-vis3 \ + sub_n-vis3 +endif diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/add_n-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/add_n-vis3.S new file mode 100644 index 0000000000..c038bcbd6e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/add_n-vis3.S @@ -0,0 +1,67 @@ +! SPARC v9 64-bit VIS3 __mpn_add_n -- Add two limb vectors of the same length > 0 and +! store sum in a third limb vector. +! +! Copyright (C) 2013-2017 Free Software Foundation, Inc. +! This file is part of the GNU C Library. +! Contributed by David S. Miller <davem@davemloft.net> +! +! The GNU C Library is free software; you can redistribute it and/or +! modify it under the terms of the GNU Lesser General Public +! License as published by the Free Software Foundation; either +! version 2.1 of the License, or (at your option) any later version. +! +! The GNU C Library is distributed in the hope that it will be useful, +! but WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! Lesser General Public License for more details. +! +! You should have received a copy of the GNU Lesser General Public +! License along with the GNU C Library; if not, see +! <http://www.gnu.org/licenses/>. + +#include <sysdep.h> + +#define res_ptr %o0 +#define s1_ptr %o1 +#define s2_ptr %o2 +#define sz %o3 +#define tmp1 %g1 +#define tmp2 %g2 +#define tmp3 %g3 +#define tmp4 %o4 + + .register %g2,#scratch + .register %g3,#scratch +ENTRY(__mpn_add_n_vis3) + subcc sz, 1, sz + be .Lfinal_limb + cmp %g0, 0 + +.Lloop: + ldx [s2_ptr + 0x00], tmp1 + add s2_ptr, 0x10, s2_ptr + ldx [s1_ptr + 0x00], tmp2 + add s1_ptr, 0x10, s1_ptr + ldx [s2_ptr - 0x08], tmp3 + add res_ptr, 0x10, res_ptr + ldx [s1_ptr - 0x08], tmp4 + sub sz, 2, sz + addxccc tmp1, tmp2, tmp1 + stx tmp1, [res_ptr - 0x10] + addxccc tmp3, tmp4, tmp3 + brgz sz, .Lloop + stx tmp3, [res_ptr - 0x08] + + brlz,pt sz, .Lfinish + nop + +.Lfinal_limb: + ldx [s2_ptr + 0x00], tmp1 + ldx [s1_ptr + 0x00], tmp2 + addxccc tmp1, tmp2, tmp1 + stx tmp1, [res_ptr + 0x00] + +.Lfinish: + retl + addxc %g0, %g0, %o0 +END(__mpn_add_n_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/add_n.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/add_n.S new file mode 100644 index 0000000000..9ffaf7865b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/add_n.S @@ -0,0 +1,56 @@ +/* Multiple versions of add_n + + Copyright (C) 2013-2017 Free Software Foundation, Inc. + Contributed by David S. Miller (davem@davemloft.net) + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__mpn_add_n) + .type __mpn_add_n, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 1f + nop +# ifdef SHARED + sethi %gdop_hix22(__mpn_add_n_vis3), %o1 + xor %o1, %gdop_lox10(__mpn_add_n_vis3), %o1 +# else + set __mpn_add_n_vis3, %o1 +# endif + ba 10f + nop +1: +# ifdef SHARED + sethi %gdop_hix22(__mpn_add_n_generic), %o1 + xor %o1, %gdop_lox10(__mpn_add_n_generic), %o1 +# else + set __mpn_add_n_generic, %o1 +# endif +10: +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__mpn_add_n) + +#define __mpn_add_n __mpn_add_n_generic +#include "../add_n.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/addmul_1-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/addmul_1-vis3.S new file mode 100644 index 0000000000..64671f5079 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/addmul_1-vis3.S @@ -0,0 +1,87 @@ +! SPARC v9 64-bit VIS3 __mpn_addmul_1 -- Multiply a limb vector with a +! limb and add the result to a second limb vector. +! +! Copyright (C) 2013-2017 Free Software Foundation, Inc. +! This file is part of the GNU C Library. +! Contributed by David S. Miller <davem@davemloft.net> +! +! The GNU C Library is free software; you can redistribute it and/or +! modify it under the terms of the GNU Lesser General Public +! License as published by the Free Software Foundation; either +! version 2.1 of the License, or (at your option) any later version. +! +! The GNU C Library is distributed in the hope that it will be useful, +! but WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! Lesser General Public License for more details. +! +! You should have received a copy of the GNU Lesser General Public +! License along with the GNU C Library; if not, see +! <http://www.gnu.org/licenses/>. + +#include <sysdep.h> + +#define res_ptr %i0 +#define s1_ptr %i1 +#define sz %i2 +#define s2_limb %i3 +#define carry %o5 +#define tmp1 %g1 +#define tmp2 %g2 +#define tmp3 %g3 +#define tmp4 %o4 +#define tmp5 %l0 +#define tmp6 %l1 +#define tmp7 %l2 +#define tmp8 %l3 + + .register %g2,#scratch + .register %g3,#scratch +ENTRY(__mpn_addmul_1_vis3) + save %sp, -176, %sp + subcc sz, 1, sz + be .Lfinal_limb + clr carry + +.Lloop: + ldx [s1_ptr + 0x00], tmp1 + ldx [res_ptr + 0x00], tmp3 + ldx [s1_ptr + 0x08], tmp2 + ldx [res_ptr + 0x08], tmp4 + mulx tmp1, s2_limb, tmp5 + add s1_ptr, 0x10, s1_ptr + umulxhi tmp1, s2_limb, tmp6 + add res_ptr, 0x10, res_ptr + mulx tmp2, s2_limb, tmp7 + sub sz, 2, sz + umulxhi tmp2, s2_limb, tmp8 + addcc carry, tmp5, tmp5 + addxc %g0, tmp6, carry + addcc tmp3, tmp5, tmp5 + addxc %g0, carry, carry + stx tmp5, [res_ptr - 0x10] + addcc carry, tmp7, tmp7 + addxc %g0, tmp8, carry + addcc tmp4, tmp7, tmp7 + addxc %g0, carry, carry + brgz sz, .Lloop + stx tmp7, [res_ptr - 0x08] + + brlz,pt sz, .Lfinish + nop + +.Lfinal_limb: + ldx [s1_ptr + 0x00], tmp1 + ldx [res_ptr + 0x00], tmp3 + mulx tmp1, s2_limb, tmp5 + umulxhi tmp1, s2_limb, tmp6 + addcc carry, tmp5, tmp5 + addxc %g0, tmp6, carry + addcc tmp3, tmp5, tmp5 + addxc %g0, carry, carry + stx tmp5, [res_ptr + 0x00] + +.Lfinish: + jmpl %i7 + 8, %g0 + restore carry, 0, %o0 +END(__mpn_addmul_1_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/addmul_1.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/addmul_1.S new file mode 100644 index 0000000000..dcb1da184c --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/addmul_1.S @@ -0,0 +1,56 @@ +/* Multiple versions of addmul_1 + + Copyright (C) 2013-2017 Free Software Foundation, Inc. + Contributed by David S. Miller (davem@davemloft.net) + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__mpn_addmul_1) + .type __mpn_addmul_1, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 1f + nop +# ifdef SHARED + sethi %gdop_hix22(__mpn_addmul_1_vis3), %o1 + xor %o1, %gdop_lox10(__mpn_addmul_1_vis3), %o1 +# else + set __mpn_addmul_1_vis3, %o1 +# endif + ba 10f + nop +1: +# ifdef SHARED + sethi %gdop_hix22(__mpn_addmul_1_generic), %o1 + xor %o1, %gdop_lox10(__mpn_addmul_1_generic), %o1 +# else + set __mpn_addmul_1_generic, %o1 +# endif +10: +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__mpn_addmul_1) + +#define __mpn_addmul_1 __mpn_addmul_1_generic +#include "../addmul_1.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/ifunc-impl-list.c b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/ifunc-impl-list.c new file mode 100644 index 0000000000..a97bc455a8 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/ifunc-impl-list.c @@ -0,0 +1,75 @@ +/* Enumerate available IFUNC implementations of a function. sparc version. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <assert.h> +#include <string.h> +#include <wchar.h> +#include <ldsodefs.h> +#include <sysdep.h> +#include <ifunc-impl-list.h> + +/* Fill ARRAY of MAX elements with IFUNC implementations for function + NAME and return the number of valid entries. */ + +size_t +__libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, + size_t max) +{ + size_t i = 0; + int hwcap; + + hwcap = GLRO(dl_hwcap); + + IFUNC_IMPL (i, name, memcpy, + IFUNC_IMPL_ADD (array, i, memcpy, hwcap & HWCAP_SPARC_CRYPTO, + __memcpy_niagara4) + IFUNC_IMPL_ADD (array, i, memcpy, hwcap & HWCAP_SPARC_N2, + __memcpy_niagara2) + IFUNC_IMPL_ADD (array, i, memcpy, hwcap & HWCAP_SPARC_BLKINIT, + __memcpy_niagara1) + IFUNC_IMPL_ADD (array, i, memcpy, hwcap & HWCAP_SPARC_ULTRA3, + __memcpy_ultra3) + IFUNC_IMPL_ADD (array, i, memcpy, 1, __memcpy_ultra1)); + + IFUNC_IMPL (i, name, mempcpy, + IFUNC_IMPL_ADD (array, i, mempcpy, hwcap & HWCAP_SPARC_CRYPTO, + __mempcpy_niagara4) + IFUNC_IMPL_ADD (array, i, mempcpy, hwcap & HWCAP_SPARC_N2, + __mempcpy_niagara2) + IFUNC_IMPL_ADD (array, i, mempcpy, hwcap & HWCAP_SPARC_BLKINIT, + __mempcpy_niagara1) + IFUNC_IMPL_ADD (array, i, mempcpy, hwcap & HWCAP_SPARC_ULTRA3, + __mempcpy_ultra3) + IFUNC_IMPL_ADD (array, i, mempcpy, 1, __mempcpy_ultra1)); + + IFUNC_IMPL (i, name, bzero, + IFUNC_IMPL_ADD (array, i, bzero, hwcap & HWCAP_SPARC_CRYPTO, + __bzero_niagara4) + IFUNC_IMPL_ADD (array, i, bzero, hwcap & HWCAP_SPARC_BLKINIT, + __bzero_niagara1) + IFUNC_IMPL_ADD (array, i, bzero, 1, __bzero_ultra1)); + + IFUNC_IMPL (i, name, memset, + IFUNC_IMPL_ADD (array, i, memset, hwcap & HWCAP_SPARC_CRYPTO, + __memset_niagara4) + IFUNC_IMPL_ADD (array, i, memset, hwcap & HWCAP_SPARC_BLKINIT, + __memset_niagara1) + IFUNC_IMPL_ADD (array, i, memset, 1, __memset_ultra1)); + + return i; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/md5-block.c b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/md5-block.c new file mode 100644 index 0000000000..7c1a3a368f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/md5-block.c @@ -0,0 +1,29 @@ +#include <sparc-ifunc.h> + +#define __md5_process_block __md5_process_block_generic +extern void __md5_process_block_generic (const void *buffer, size_t len, + struct md5_ctx *ctx); + +#include <crypt/md5-block.c> + +#undef __md5_process_block + +extern void __md5_process_block_crop (const void *buffer, size_t len, + struct md5_ctx *ctx); +static bool cpu_supports_md5(int hwcap) +{ + unsigned long cfr; + + if (!(hwcap & HWCAP_SPARC_CRYPTO)) + return false; + + __asm__ ("rd %%asr26, %0" : "=r" (cfr)); + if (cfr & (1 << 4)) + return true; + + return false; +} + +extern void __md5_process_block (const void *buffer, size_t len, + struct md5_ctx *ctx); +sparc_libc_ifunc(__md5_process_block, cpu_supports_md5(hwcap) ? __md5_process_block_crop : __md5_process_block_generic); diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/md5-crop.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/md5-crop.S new file mode 100644 index 0000000000..e8810da83e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/md5-crop.S @@ -0,0 +1,110 @@ +/* MD5 using sparc crypto opcodes. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller (davem@davemloft.net) + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +#define ASI_PL 0x88 + +#define MD5 \ + .word 0x81b02800; + + .text + .align 32 +ENTRY(__md5_process_block_crop) + /* %o0=buffer, %o1=len, %o2=CTX */ + ld [%o2 + 0x10], %g1 + add %g1, %o1, %o4 + st %o4, [%o2 + 0x10] + clr %o5 + cmp %o4, %g1 + movlu %icc, 1, %o5 +#ifdef __arch64__ + srlx %o1, 32, %o4 + add %o5, %o4, %o5 +#endif + ld [%o2 + 0x14], %o4 + add %o4, %o5, %o4 + st %o4, [%o2 + 0x14] + lda [%o2] ASI_PL, %f0 + add %o2, 0x4, %g1 + lda [%g1] ASI_PL, %f1 + add %o2, 0x8, %g1 + andcc %o0, 0x7, %g0 + lda [%g1] ASI_PL, %f2 + add %o2, 0xc, %g1 + bne,pn %xcc, 10f + lda [%g1] ASI_PL, %f3 + +1: + ldd [%o0 + 0x00], %f8 + ldd [%o0 + 0x08], %f10 + ldd [%o0 + 0x10], %f12 + ldd [%o0 + 0x18], %f14 + ldd [%o0 + 0x20], %f16 + ldd [%o0 + 0x28], %f18 + ldd [%o0 + 0x30], %f20 + ldd [%o0 + 0x38], %f22 + + MD5 + + subcc %o1, 64, %o1 + bne,pt %xcc, 1b + add %o0, 0x40, %o0 + +5: + sta %f0, [%o2] ASI_PL + add %o2, 0x4, %g1 + sta %f1, [%g1] ASI_PL + add %o2, 0x8, %g1 + sta %f2, [%g1] ASI_PL + add %o2, 0xc, %g1 + retl + sta %f3, [%g1] ASI_PL +10: + alignaddr %o0, %g0, %o0 + + ldd [%o0 + 0x00], %f10 +1: + ldd [%o0 + 0x08], %f12 + ldd [%o0 + 0x10], %f14 + ldd [%o0 + 0x18], %f16 + ldd [%o0 + 0x20], %f18 + ldd [%o0 + 0x28], %f20 + ldd [%o0 + 0x30], %f22 + ldd [%o0 + 0x38], %f24 + ldd [%o0 + 0x40], %f26 + + faligndata %f10, %f12, %f8 + faligndata %f12, %f14, %f10 + faligndata %f14, %f16, %f12 + faligndata %f16, %f18, %f14 + faligndata %f18, %f20, %f16 + faligndata %f20, %f22, %f18 + faligndata %f22, %f24, %f20 + faligndata %f24, %f26, %f22 + + MD5 + + subcc %o1, 64, %o1 + fsrc2 %f26, %f10 + bne,pt %xcc, 1b + add %o0, 0x40, %o0 + + ba,a,pt %xcc, 5b +END(__md5_process_block_crop) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memcpy-niagara1.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memcpy-niagara1.S new file mode 100644 index 0000000000..ccf42446e8 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memcpy-niagara1.S @@ -0,0 +1,347 @@ +/* Copy SIZE bytes from SRC to DEST. For SUN4V Niagara. + Copyright (C) 2006-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller (davem@davemloft.net) + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +#define ASI_BLK_INIT_QUAD_LDD_P 0xe2 +#define ASI_P 0x80 +#define ASI_PNF 0x82 + +#define LOAD(type,addr,dest) type##a [addr] ASI_P, dest +#define LOAD_TWIN(addr_reg,dest0,dest1) \ + ldda [addr_reg] ASI_BLK_INIT_QUAD_LDD_P, dest0 + +#define STORE(type,src,addr) type src, [addr] +#define STORE_INIT(src,addr) stxa src, [addr] %asi + +#ifndef XCC +#define USE_BPR +#define XCC xcc +#endif + +#if IS_IN (libc) + + .register %g2,#scratch + .register %g3,#scratch + .register %g6,#scratch + + .text + +ENTRY(__mempcpy_niagara1) + ba,pt %XCC, 101f + add %o0, %o2, %g5 +END(__mempcpy_niagara1) + + .align 32 +ENTRY(__memcpy_niagara1) +100: /* %o0=dst, %o1=src, %o2=len */ + mov %o0, %g5 +101: +# ifndef USE_BPR + srl %o2, 0, %o2 +# endif + cmp %o2, 0 + be,pn %XCC, 85f +218: or %o0, %o1, %o3 + cmp %o2, 16 + blu,a,pn %XCC, 80f + or %o3, %o2, %o3 + + /* 2 blocks (128 bytes) is the minimum we can do the block + * copy with. We need to ensure that we'll iterate at least + * once in the block copy loop. At worst we'll need to align + * the destination to a 64-byte boundary which can chew up + * to (64 - 1) bytes from the length before we perform the + * block copy loop. + */ + cmp %o2, (2 * 64) + blu,pt %XCC, 70f + andcc %o3, 0x7, %g0 + + /* %o0: dst + * %o1: src + * %o2: len (known to be >= 128) + * + * The block copy loops will use %o4/%o5,%g2/%g3 as + * temporaries while copying the data. + */ + + LOAD(prefetch, %o1, #one_read) + wr %g0, ASI_BLK_INIT_QUAD_LDD_P, %asi + + /* Align destination on 64-byte boundary. */ + andcc %o0, (64 - 1), %o4 + be,pt %XCC, 2f + sub %o4, 64, %o4 + sub %g0, %o4, %o4 ! bytes to align dst + sub %o2, %o4, %o2 +1: subcc %o4, 1, %o4 + LOAD(ldub, %o1, %g1) + STORE(stb, %g1, %o0) + add %o1, 1, %o1 + bne,pt %XCC, 1b + add %o0, 1, %o0 + + /* If the source is on a 16-byte boundary we can do + * the direct block copy loop. If it is 8-byte aligned + * we can do the 16-byte loads offset by -8 bytes and the + * init stores offset by one register. + * + * If the source is not even 8-byte aligned, we need to do + * shifting and masking (basically integer faligndata). + * + * The careful bit with init stores is that if we store + * to any part of the cache line we have to store the whole + * cacheline else we can end up with corrupt L2 cache line + * contents. Since the loop works on 64-bytes of 64-byte + * aligned store data at a time, this is easy to ensure. + */ +2: + andcc %o1, (16 - 1), %o4 + andn %o2, (64 - 1), %g1 ! block copy loop iterator + sub %o2, %g1, %o2 ! final sub-block copy bytes + be,pt %XCC, 50f + cmp %o4, 8 + be,a,pt %XCC, 10f + sub %o1, 0x8, %o1 + + /* Neither 8-byte nor 16-byte aligned, shift and mask. */ + mov %g1, %o4 + and %o1, 0x7, %g1 + sll %g1, 3, %g1 + mov 64, %o3 + andn %o1, 0x7, %o1 + LOAD(ldx, %o1, %g2) + sub %o3, %g1, %o3 + sllx %g2, %g1, %g2 + +#define SWIVEL_ONE_DWORD(SRC, TMP1, TMP2, PRE_VAL, PRE_SHIFT, POST_SHIFT, DST)\ + LOAD(ldx, SRC, TMP1); \ + srlx TMP1, PRE_SHIFT, TMP2; \ + or TMP2, PRE_VAL, TMP2; \ + STORE_INIT(TMP2, DST); \ + sllx TMP1, POST_SHIFT, PRE_VAL; + +1: add %o1, 0x8, %o1 + SWIVEL_ONE_DWORD(%o1, %g3, %o5, %g2, %o3, %g1, %o0 + 0x00) + add %o1, 0x8, %o1 + SWIVEL_ONE_DWORD(%o1, %g3, %o5, %g2, %o3, %g1, %o0 + 0x08) + add %o1, 0x8, %o1 + SWIVEL_ONE_DWORD(%o1, %g3, %o5, %g2, %o3, %g1, %o0 + 0x10) + add %o1, 0x8, %o1 + SWIVEL_ONE_DWORD(%o1, %g3, %o5, %g2, %o3, %g1, %o0 + 0x18) + add %o1, 32, %o1 + LOAD(prefetch, %o1, #one_read) + sub %o1, 32 - 8, %o1 + SWIVEL_ONE_DWORD(%o1, %g3, %o5, %g2, %o3, %g1, %o0 + 0x20) + add %o1, 8, %o1 + SWIVEL_ONE_DWORD(%o1, %g3, %o5, %g2, %o3, %g1, %o0 + 0x28) + add %o1, 8, %o1 + SWIVEL_ONE_DWORD(%o1, %g3, %o5, %g2, %o3, %g1, %o0 + 0x30) + add %o1, 8, %o1 + SWIVEL_ONE_DWORD(%o1, %g3, %o5, %g2, %o3, %g1, %o0 + 0x38) + subcc %o4, 64, %o4 + bne,pt %XCC, 1b + add %o0, 64, %o0 + +#undef SWIVEL_ONE_DWORD + + srl %g1, 3, %g1 + ba,pt %XCC, 60f + add %o1, %g1, %o1 + +10: /* Destination is 64-byte aligned, source was only 8-byte + * aligned but it has been subtracted by 8 and we perform + * one twin load ahead, then add 8 back into source when + * we finish the loop. + */ + LOAD_TWIN(%o1, %o4, %o5) +1: add %o1, 16, %o1 + LOAD_TWIN(%o1, %g2, %g3) + add %o1, 16 + 32, %o1 + LOAD(prefetch, %o1, #one_read) + sub %o1, 32, %o1 + STORE_INIT(%o5, %o0 + 0x00) ! initializes cache line + STORE_INIT(%g2, %o0 + 0x08) + LOAD_TWIN(%o1, %o4, %o5) + add %o1, 16, %o1 + STORE_INIT(%g3, %o0 + 0x10) + STORE_INIT(%o4, %o0 + 0x18) + LOAD_TWIN(%o1, %g2, %g3) + add %o1, 16, %o1 + STORE_INIT(%o5, %o0 + 0x20) + STORE_INIT(%g2, %o0 + 0x28) + LOAD_TWIN(%o1, %o4, %o5) + STORE_INIT(%g3, %o0 + 0x30) + STORE_INIT(%o4, %o0 + 0x38) + subcc %g1, 64, %g1 + bne,pt %XCC, 1b + add %o0, 64, %o0 + + ba,pt %XCC, 60f + add %o1, 0x8, %o1 + +50: /* Destination is 64-byte aligned, and source is 16-byte + * aligned. + */ +1: LOAD_TWIN(%o1, %o4, %o5) + add %o1, 16, %o1 + LOAD_TWIN(%o1, %g2, %g3) + add %o1, 16 + 32, %o1 + LOAD(prefetch, %o1, #one_read) + sub %o1, 32, %o1 + STORE_INIT(%o4, %o0 + 0x00) ! initializes cache line + STORE_INIT(%o5, %o0 + 0x08) + LOAD_TWIN(%o1, %o4, %o5) + add %o1, 16, %o1 + STORE_INIT(%g2, %o0 + 0x10) + STORE_INIT(%g3, %o0 + 0x18) + LOAD_TWIN(%o1, %g2, %g3) + add %o1, 16, %o1 + STORE_INIT(%o4, %o0 + 0x20) + STORE_INIT(%o5, %o0 + 0x28) + STORE_INIT(%g2, %o0 + 0x30) + STORE_INIT(%g3, %o0 + 0x38) + subcc %g1, 64, %g1 + bne,pt %XCC, 1b + add %o0, 64, %o0 + /* fall through */ + +60: + /* %o2 contains any final bytes still needed to be copied + * over. If anything is left, we copy it one byte at a time. + */ + wr %g0, ASI_PNF, %asi + brz,pt %o2, 85f + sub %o0, %o1, %o3 + ba,a,pt %XCC, 90f + + .align 64 +70: /* 16 < len <= 64 */ + bne,pn %XCC, 75f + sub %o0, %o1, %o3 + +72: + andn %o2, 0xf, %o4 + and %o2, 0xf, %o2 +1: subcc %o4, 0x10, %o4 + LOAD(ldx, %o1, %o5) + add %o1, 0x08, %o1 + LOAD(ldx, %o1, %g1) + sub %o1, 0x08, %o1 + STORE(stx, %o5, %o1 + %o3) + add %o1, 0x8, %o1 + STORE(stx, %g1, %o1 + %o3) + bgu,pt %XCC, 1b + add %o1, 0x8, %o1 +73: andcc %o2, 0x8, %g0 + be,pt %XCC, 1f + nop + sub %o2, 0x8, %o2 + LOAD(ldx, %o1, %o5) + STORE(stx, %o5, %o1 + %o3) + add %o1, 0x8, %o1 +1: andcc %o2, 0x4, %g0 + be,pt %XCC, 1f + nop + sub %o2, 0x4, %o2 + LOAD(lduw, %o1, %o5) + STORE(stw, %o5, %o1 + %o3) + add %o1, 0x4, %o1 +1: cmp %o2, 0 + be,pt %XCC, 85f + nop + ba,pt %XCC, 90f + nop + +75: + andcc %o0, 0x7, %g1 + sub %g1, 0x8, %g1 + be,pn %icc, 2f + sub %g0, %g1, %g1 + sub %o2, %g1, %o2 + +1: subcc %g1, 1, %g1 + LOAD(ldub, %o1, %o5) + STORE(stb, %o5, %o1 + %o3) + bgu,pt %icc, 1b + add %o1, 1, %o1 + +2: add %o1, %o3, %o0 + andcc %o1, 0x7, %g1 + bne,pt %icc, 8f + sll %g1, 3, %g1 + + cmp %o2, 16 + bgeu,pt %icc, 72b + nop + ba,a,pt %XCC, 73b + +8: mov 64, %o3 + andn %o1, 0x7, %o1 + LOAD(ldx, %o1, %g2) + sub %o3, %g1, %o3 + andn %o2, 0x7, %o4 + sllx %g2, %g1, %g2 +1: add %o1, 0x8, %o1 + LOAD(ldx, %o1, %g3) + subcc %o4, 0x8, %o4 + srlx %g3, %o3, %o5 + or %o5, %g2, %o5 + STORE(stx, %o5, %o0) + add %o0, 0x8, %o0 + bgu,pt %icc, 1b + sllx %g3, %g1, %g2 + + srl %g1, 3, %g1 + andcc %o2, 0x7, %o2 + be,pn %icc, 85f + add %o1, %g1, %o1 + ba,pt %XCC, 90f + sub %o0, %o1, %o3 + + .align 64 +80: /* 0 < len <= 16 */ + andcc %o3, 0x3, %g0 + bne,pn %XCC, 90f + sub %o0, %o1, %o3 + +1: + subcc %o2, 4, %o2 + LOAD(lduw, %o1, %g1) + STORE(stw, %g1, %o1 + %o3) + bgu,pt %XCC, 1b + add %o1, 4, %o1 + +85: retl + mov %g5, %o0 + + .align 32 +90: + subcc %o2, 1, %o2 + LOAD(ldub, %o1, %g1) + STORE(stb, %g1, %o1 + %o3) + bgu,pt %XCC, 90b + add %o1, 1, %o1 + retl + mov %g5, %o0 + +END(__memcpy_niagara1) + +#endif diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memcpy-niagara2.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memcpy-niagara2.S new file mode 100644 index 0000000000..798b3c80fe --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memcpy-niagara2.S @@ -0,0 +1,498 @@ +/* Copy SIZE bytes from SRC to DEST. For SUN4V Niagara-2. + Copyright (C) 2007-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller (davem@davemloft.net) + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +#define ASI_BLK_INIT_QUAD_LDD_P 0xe2 +#define ASI_BLK_P 0xf0 +#define ASI_P 0x80 +#define ASI_PNF 0x82 + +#define FPRS_FEF 0x04 + +#define VISEntryHalf \ + rd %fprs, %o5; \ + wr %g0, FPRS_FEF, %fprs + +#define VISExitHalf \ + and %o5, FPRS_FEF, %o5; \ + wr %o5, 0x0, %fprs + +#define STORE_ASI ASI_BLK_INIT_QUAD_LDD_P + +#define LOAD(type,addr,dest) type [addr], dest +#define LOAD_BLK(addr,dest) ldda [addr] ASI_BLK_P, dest +#define STORE(type,src,addr) type src, [addr] +#define STORE_BLK(src,addr) stda src, [addr] ASI_BLK_P +#define STORE_INIT(src,addr) stxa src, [addr] STORE_ASI + +#ifndef XCC +#define USE_BPR +#define XCC xcc +#endif + +#define FREG_FROB(x0, x1, x2, x3, x4, x5, x6, x7, x8) \ + faligndata %x0, %x1, %f0; \ + faligndata %x1, %x2, %f2; \ + faligndata %x2, %x3, %f4; \ + faligndata %x3, %x4, %f6; \ + faligndata %x4, %x5, %f8; \ + faligndata %x5, %x6, %f10; \ + faligndata %x6, %x7, %f12; \ + faligndata %x7, %x8, %f14; + +#define FREG_MOVE_1(x0) \ + fsrc2 %x0, %f0; +#define FREG_MOVE_2(x0, x1) \ + fsrc2 %x0, %f0; \ + fsrc2 %x1, %f2; +#define FREG_MOVE_3(x0, x1, x2) \ + fsrc2 %x0, %f0; \ + fsrc2 %x1, %f2; \ + fsrc2 %x2, %f4; +#define FREG_MOVE_4(x0, x1, x2, x3) \ + fsrc2 %x0, %f0; \ + fsrc2 %x1, %f2; \ + fsrc2 %x2, %f4; \ + fsrc2 %x3, %f6; +#define FREG_MOVE_5(x0, x1, x2, x3, x4) \ + fsrc2 %x0, %f0; \ + fsrc2 %x1, %f2; \ + fsrc2 %x2, %f4; \ + fsrc2 %x3, %f6; \ + fsrc2 %x4, %f8; +#define FREG_MOVE_6(x0, x1, x2, x3, x4, x5) \ + fsrc2 %x0, %f0; \ + fsrc2 %x1, %f2; \ + fsrc2 %x2, %f4; \ + fsrc2 %x3, %f6; \ + fsrc2 %x4, %f8; \ + fsrc2 %x5, %f10; +#define FREG_MOVE_7(x0, x1, x2, x3, x4, x5, x6) \ + fsrc2 %x0, %f0; \ + fsrc2 %x1, %f2; \ + fsrc2 %x2, %f4; \ + fsrc2 %x3, %f6; \ + fsrc2 %x4, %f8; \ + fsrc2 %x5, %f10; \ + fsrc2 %x6, %f12; +#define FREG_MOVE_8(x0, x1, x2, x3, x4, x5, x6, x7) \ + fsrc2 %x0, %f0; \ + fsrc2 %x1, %f2; \ + fsrc2 %x2, %f4; \ + fsrc2 %x3, %f6; \ + fsrc2 %x4, %f8; \ + fsrc2 %x5, %f10; \ + fsrc2 %x6, %f12; \ + fsrc2 %x7, %f14; +#define FREG_LOAD_1(base, x0) \ + LOAD(ldd, base + 0x00, %x0) +#define FREG_LOAD_2(base, x0, x1) \ + LOAD(ldd, base + 0x00, %x0); \ + LOAD(ldd, base + 0x08, %x1); +#define FREG_LOAD_3(base, x0, x1, x2) \ + LOAD(ldd, base + 0x00, %x0); \ + LOAD(ldd, base + 0x08, %x1); \ + LOAD(ldd, base + 0x10, %x2); +#define FREG_LOAD_4(base, x0, x1, x2, x3) \ + LOAD(ldd, base + 0x00, %x0); \ + LOAD(ldd, base + 0x08, %x1); \ + LOAD(ldd, base + 0x10, %x2); \ + LOAD(ldd, base + 0x18, %x3); +#define FREG_LOAD_5(base, x0, x1, x2, x3, x4) \ + LOAD(ldd, base + 0x00, %x0); \ + LOAD(ldd, base + 0x08, %x1); \ + LOAD(ldd, base + 0x10, %x2); \ + LOAD(ldd, base + 0x18, %x3); \ + LOAD(ldd, base + 0x20, %x4); +#define FREG_LOAD_6(base, x0, x1, x2, x3, x4, x5) \ + LOAD(ldd, base + 0x00, %x0); \ + LOAD(ldd, base + 0x08, %x1); \ + LOAD(ldd, base + 0x10, %x2); \ + LOAD(ldd, base + 0x18, %x3); \ + LOAD(ldd, base + 0x20, %x4); \ + LOAD(ldd, base + 0x28, %x5); +#define FREG_LOAD_7(base, x0, x1, x2, x3, x4, x5, x6) \ + LOAD(ldd, base + 0x00, %x0); \ + LOAD(ldd, base + 0x08, %x1); \ + LOAD(ldd, base + 0x10, %x2); \ + LOAD(ldd, base + 0x18, %x3); \ + LOAD(ldd, base + 0x20, %x4); \ + LOAD(ldd, base + 0x28, %x5); \ + LOAD(ldd, base + 0x30, %x6); + +#if IS_IN (libc) + + .register %g2,#scratch + .register %g3,#scratch + .register %g6,#scratch + + .text + +ENTRY(__mempcpy_niagara2) + ba,pt %XCC, 101f + add %o0, %o2, %g5 +END(__mempcpy_niagara2) + + .align 32 +ENTRY(__memcpy_niagara2) +100: /* %o0=dst, %o1=src, %o2=len */ + mov %o0, %g5 +101: +# ifndef USE_BPR + srl %o2, 0, %o2 +# endif + cmp %o2, 0 + be,pn %XCC, 85f +218: or %o0, %o1, %o3 + cmp %o2, 16 + blu,a,pn %XCC, 80f + or %o3, %o2, %o3 + + /* 2 blocks (128 bytes) is the minimum we can do the block + * copy with. We need to ensure that we'll iterate at least + * once in the block copy loop. At worst we'll need to align + * the destination to a 64-byte boundary which can chew up + * to (64 - 1) bytes from the length before we perform the + * block copy loop. + * + * However, the cut-off point, performance wise, is around + * 4 64-byte blocks. + */ + cmp %o2, (4 * 64) + blu,pt %XCC, 75f + andcc %o3, 0x7, %g0 + + /* %o0: dst + * %o1: src + * %o2: len (known to be >= 128) + * + * The block copy loops can use %o4, %g2, %g3 as + * temporaries while copying the data. %o5 must + * be preserved between VISEntryHalf and VISExitHalf + */ + + LOAD(prefetch, %o1 + 0x000, #one_read) + LOAD(prefetch, %o1 + 0x040, #one_read) + LOAD(prefetch, %o1 + 0x080, #one_read) + + /* Align destination on 64-byte boundary. */ + andcc %o0, (64 - 1), %o4 + be,pt %XCC, 2f + sub %o4, 64, %o4 + sub %g0, %o4, %o4 ! bytes to align dst + sub %o2, %o4, %o2 +1: subcc %o4, 1, %o4 + LOAD(ldub, %o1, %g1) + STORE(stb, %g1, %o0) + add %o1, 1, %o1 + bne,pt %XCC, 1b + add %o0, 1, %o0 + +2: + /* Clobbers o5/g1/g2/g3/g7/icc/xcc. We must preserve + * o5 from here until we hit VISExitHalf. + */ + VISEntryHalf + + membar #Sync + alignaddr %o1, %g0, %g0 + + add %o1, (64 - 1), %o4 + andn %o4, (64 - 1), %o4 + andn %o2, (64 - 1), %g1 + sub %o2, %g1, %o2 + + and %o1, (64 - 1), %g2 + add %o1, %g1, %o1 + sub %o0, %o4, %g3 + brz,pt %g2, 190f + cmp %g2, 32 + blu,a 5f + cmp %g2, 16 + cmp %g2, 48 + blu,a 4f + cmp %g2, 40 + cmp %g2, 56 + blu 170f + nop + ba,a,pt %xcc, 180f + +4: /* 32 <= low bits < 48 */ + blu 150f + nop + ba,a,pt %xcc, 160f +5: /* 0 < low bits < 32 */ + blu,a 6f + cmp %g2, 8 + cmp %g2, 24 + blu 130f + nop + ba,a,pt %xcc, 140f +6: /* 0 < low bits < 16 */ + bgeu 120f + nop + /* fall through for 0 < low bits < 8 */ +110: sub %o4, 64, %g2 + LOAD_BLK(%g2, %f0) +1: STORE_INIT(%g0, %o4 + %g3) + LOAD_BLK(%o4, %f16) + FREG_FROB(f0, f2, f4, f6, f8, f10, f12, f14, f16) + STORE_BLK(%f0, %o4 + %g3) + FREG_MOVE_8(f16, f18, f20, f22, f24, f26, f28, f30) + subcc %g1, 64, %g1 + add %o4, 64, %o4 + bne,pt %XCC, 1b + LOAD(prefetch, %o4 + 64, #one_read) + ba,pt %xcc, 195f + nop + +120: sub %o4, 56, %g2 + FREG_LOAD_7(%g2, f0, f2, f4, f6, f8, f10, f12) +1: STORE_INIT(%g0, %o4 + %g3) + LOAD_BLK(%o4, %f16) + FREG_FROB(f0, f2, f4, f6, f8, f10, f12, f16, f18) + STORE_BLK(%f0, %o4 + %g3) + FREG_MOVE_7(f18, f20, f22, f24, f26, f28, f30) + subcc %g1, 64, %g1 + add %o4, 64, %o4 + bne,pt %XCC, 1b + LOAD(prefetch, %o4 + 64, #one_read) + ba,pt %xcc, 195f + nop + +130: sub %o4, 48, %g2 + FREG_LOAD_6(%g2, f0, f2, f4, f6, f8, f10) +1: STORE_INIT(%g0, %o4 + %g3) + LOAD_BLK(%o4, %f16) + FREG_FROB(f0, f2, f4, f6, f8, f10, f16, f18, f20) + STORE_BLK(%f0, %o4 + %g3) + FREG_MOVE_6(f20, f22, f24, f26, f28, f30) + subcc %g1, 64, %g1 + add %o4, 64, %o4 + bne,pt %XCC, 1b + LOAD(prefetch, %o4 + 64, #one_read) + ba,pt %xcc, 195f + nop + +140: sub %o4, 40, %g2 + FREG_LOAD_5(%g2, f0, f2, f4, f6, f8) +1: STORE_INIT(%g0, %o4 + %g3) + LOAD_BLK(%o4, %f16) + FREG_FROB(f0, f2, f4, f6, f8, f16, f18, f20, f22) + STORE_BLK(%f0, %o4 + %g3) + FREG_MOVE_5(f22, f24, f26, f28, f30) + subcc %g1, 64, %g1 + add %o4, 64, %o4 + bne,pt %XCC, 1b + LOAD(prefetch, %o4 + 64, #one_read) + ba,pt %xcc, 195f + nop + +150: sub %o4, 32, %g2 + FREG_LOAD_4(%g2, f0, f2, f4, f6) +1: STORE_INIT(%g0, %o4 + %g3) + LOAD_BLK(%o4, %f16) + FREG_FROB(f0, f2, f4, f6, f16, f18, f20, f22, f24) + STORE_BLK(%f0, %o4 + %g3) + FREG_MOVE_4(f24, f26, f28, f30) + subcc %g1, 64, %g1 + add %o4, 64, %o4 + bne,pt %XCC, 1b + LOAD(prefetch, %o4 + 64, #one_read) + ba,pt %xcc, 195f + nop + +160: sub %o4, 24, %g2 + FREG_LOAD_3(%g2, f0, f2, f4) +1: STORE_INIT(%g0, %o4 + %g3) + LOAD_BLK(%o4, %f16) + FREG_FROB(f0, f2, f4, f16, f18, f20, f22, f24, f26) + STORE_BLK(%f0, %o4 + %g3) + FREG_MOVE_3(f26, f28, f30) + subcc %g1, 64, %g1 + add %o4, 64, %o4 + bne,pt %XCC, 1b + LOAD(prefetch, %o4 + 64, #one_read) + ba,pt %xcc, 195f + nop + +170: sub %o4, 16, %g2 + FREG_LOAD_2(%g2, f0, f2) +1: STORE_INIT(%g0, %o4 + %g3) + LOAD_BLK(%o4, %f16) + FREG_FROB(f0, f2, f16, f18, f20, f22, f24, f26, f28) + STORE_BLK(%f0, %o4 + %g3) + FREG_MOVE_2(f28, f30) + subcc %g1, 64, %g1 + add %o4, 64, %o4 + bne,pt %XCC, 1b + LOAD(prefetch, %o4 + 64, #one_read) + ba,pt %xcc, 195f + nop + +180: sub %o4, 8, %g2 + FREG_LOAD_1(%g2, f0) +1: STORE_INIT(%g0, %o4 + %g3) + LOAD_BLK(%o4, %f16) + FREG_FROB(f0, f16, f18, f20, f22, f24, f26, f28, f30) + STORE_BLK(%f0, %o4 + %g3) + FREG_MOVE_1(f30) + subcc %g1, 64, %g1 + add %o4, 64, %o4 + bne,pt %XCC, 1b + LOAD(prefetch, %o4 + 64, #one_read) + ba,pt %xcc, 195f + nop + +190: +1: STORE_INIT(%g0, %o4 + %g3) + subcc %g1, 64, %g1 + LOAD_BLK(%o4, %f0) + STORE_BLK(%f0, %o4 + %g3) + add %o4, 64, %o4 + bne,pt %XCC, 1b + LOAD(prefetch, %o4 + 64, #one_read) + +195: + add %o4, %g3, %o0 + membar #Sync + + VISExitHalf + + /* %o2 contains any final bytes still needed to be copied + * over. If anything is left, we copy it one byte at a time. + */ + brz,pt %o2, 85f + sub %o0, %o1, %o3 + ba,a,pt %XCC, 90f + + .align 64 +75: /* 16 < len <= 64 */ + bne,pn %XCC, 75f + sub %o0, %o1, %o3 + +72: + andn %o2, 0xf, %o4 + and %o2, 0xf, %o2 +1: subcc %o4, 0x10, %o4 + LOAD(ldx, %o1, %o5) + add %o1, 0x08, %o1 + LOAD(ldx, %o1, %g1) + sub %o1, 0x08, %o1 + STORE(stx, %o5, %o1 + %o3) + add %o1, 0x8, %o1 + STORE(stx, %g1, %o1 + %o3) + bgu,pt %XCC, 1b + add %o1, 0x8, %o1 +73: andcc %o2, 0x8, %g0 + be,pt %XCC, 1f + nop + sub %o2, 0x8, %o2 + LOAD(ldx, %o1, %o5) + STORE(stx, %o5, %o1 + %o3) + add %o1, 0x8, %o1 +1: andcc %o2, 0x4, %g0 + be,pt %XCC, 1f + nop + sub %o2, 0x4, %o2 + LOAD(lduw, %o1, %o5) + STORE(stw, %o5, %o1 + %o3) + add %o1, 0x4, %o1 +1: cmp %o2, 0 + be,pt %XCC, 85f + nop + ba,pt %xcc, 90f + nop + +75: + andcc %o0, 0x7, %g1 + sub %g1, 0x8, %g1 + be,pn %icc, 2f + sub %g0, %g1, %g1 + sub %o2, %g1, %o2 + +1: subcc %g1, 1, %g1 + LOAD(ldub, %o1, %o5) + STORE(stb, %o5, %o1 + %o3) + bgu,pt %icc, 1b + add %o1, 1, %o1 + +2: add %o1, %o3, %o0 + andcc %o1, 0x7, %g1 + bne,pt %icc, 8f + sll %g1, 3, %g1 + + cmp %o2, 16 + bgeu,pt %icc, 72b + nop + ba,a,pt %xcc, 73b + +8: mov 64, %o3 + andn %o1, 0x7, %o1 + LOAD(ldx, %o1, %g2) + sub %o3, %g1, %o3 + andn %o2, 0x7, %o4 + sllx %g2, %g1, %g2 +1: add %o1, 0x8, %o1 + LOAD(ldx, %o1, %g3) + subcc %o4, 0x8, %o4 + srlx %g3, %o3, %o5 + or %o5, %g2, %o5 + STORE(stx, %o5, %o0) + add %o0, 0x8, %o0 + bgu,pt %icc, 1b + sllx %g3, %g1, %g2 + + srl %g1, 3, %g1 + andcc %o2, 0x7, %o2 + be,pn %icc, 85f + add %o1, %g1, %o1 + ba,pt %xcc, 90f + sub %o0, %o1, %o3 + + .align 64 +80: /* 0 < len <= 16 */ + andcc %o3, 0x3, %g0 + bne,pn %XCC, 90f + sub %o0, %o1, %o3 + +1: + subcc %o2, 4, %o2 + LOAD(lduw, %o1, %g1) + STORE(stw, %g1, %o1 + %o3) + bgu,pt %XCC, 1b + add %o1, 4, %o1 + +85: retl + mov %g5, %o0 + + .align 32 +90: + subcc %o2, 1, %o2 + LOAD(ldub, %o1, %g1) + STORE(stb, %g1, %o1 + %o3) + bgu,pt %XCC, 90b + add %o1, 1, %o1 + retl + mov %g5, %o0 + +END(__memcpy_niagara2) + +#endif diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memcpy-niagara4.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memcpy-niagara4.S new file mode 100644 index 0000000000..709b398364 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memcpy-niagara4.S @@ -0,0 +1,332 @@ +/* Copy SIZE bytes from SRC to DEST. For SUN4V Niagara-4. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller (davem@davemloft.net) + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +#define ASI_BLK_INIT_QUAD_LDD_P 0xe2 + +#define FPRS_FEF 0x04 + +/* On T4 it is very expensive to access ASRs like %fprs and + * %asi, avoiding a read or a write can save ~50 cycles. + */ +#define FPU_ENTER \ + rd %fprs, %o5; \ + andcc %o5, FPRS_FEF, %g0; \ + be,a,pn %icc, 999f; \ + wr %g0, FPRS_FEF, %fprs; \ + 999: + +#define VISEntryHalf FPU_ENTER +#define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs + +#define GLOBAL_SPARE %g5 + +#define STORE_ASI ASI_BLK_INIT_QUAD_LDD_P +#define EX_LD(x) x +#define EX_ST(x) x +#define EX_RETVAL(x) x +#define LOAD(type,addr,dest) type [addr], dest +#define STORE(type,src,addr) type src, [addr] +#define STORE_INIT(src,addr) stxa src, [addr] STORE_ASI + +#if IS_IN (libc) + + .register %g2,#scratch + .register %g3,#scratch + .register %g6,#scratch + + .text + +ENTRY(__mempcpy_niagara4) + ba,pt %icc, 101f + add %o0, %o2, %o3 +END(__mempcpy_niagara4) + + .align 32 +ENTRY(__memcpy_niagara4) +100: /* %o0=dst, %o1=src, %o2=len */ + mov %o0, %o3 +101: +#ifndef __arch64__ + srl %o2, 0, %o2 +#endif + brz,pn %o2, .Lexit + cmp %o2, 3 + ble,pn %icc, .Ltiny + cmp %o2, 19 + ble,pn %icc, .Lsmall + or %o0, %o1, %g2 + cmp %o2, 128 + bl,pn %icc, .Lmedium + nop + +.Llarge:/* len >= 0x80 */ + /* First get dest 8 byte aligned. */ + sub %g0, %o0, %g1 + and %g1, 0x7, %g1 + brz,pt %g1, 51f + sub %o2, %g1, %o2 + +1: EX_LD(LOAD(ldub, %o1 + 0x00, %g2)) + add %o1, 1, %o1 + subcc %g1, 1, %g1 + add %o0, 1, %o0 + bne,pt %icc, 1b + EX_ST(STORE(stb, %g2, %o0 - 0x01)) + +51: LOAD(prefetch, %o1 + 0x040, #n_reads_strong) + LOAD(prefetch, %o1 + 0x080, #n_reads_strong) + LOAD(prefetch, %o1 + 0x0c0, #n_reads_strong) + LOAD(prefetch, %o1 + 0x100, #n_reads_strong) + LOAD(prefetch, %o1 + 0x140, #n_reads_strong) + LOAD(prefetch, %o1 + 0x180, #n_reads_strong) + LOAD(prefetch, %o1 + 0x1c0, #n_reads_strong) + LOAD(prefetch, %o1 + 0x200, #n_reads_strong) + + /* Check if we can use the straight fully aligned + * loop, or we require the alignaddr/faligndata variant. + */ + andcc %o1, 0x7, %o5 + bne,pn %icc, .Llarge_src_unaligned + sub %g0, %o0, %g1 + + /* Legitimize the use of initializing stores by getting dest + * to be 64-byte aligned. + */ + and %g1, 0x3f, %g1 + brz,pt %g1, .Llarge_aligned + sub %o2, %g1, %o2 + +1: EX_LD(LOAD(ldx, %o1 + 0x00, %g2)) + add %o1, 8, %o1 + subcc %g1, 8, %g1 + add %o0, 8, %o0 + bne,pt %icc, 1b + EX_ST(STORE(stx, %g2, %o0 - 0x08)) + +.Llarge_aligned: + /* len >= 0x80 && src 8-byte aligned && dest 8-byte aligned */ + andn %o2, 0x3f, %o4 + sub %o2, %o4, %o2 + +1: EX_LD(LOAD(ldx, %o1 + 0x00, %g1)) + add %o1, 0x40, %o1 + EX_LD(LOAD(ldx, %o1 - 0x38, %g2)) + subcc %o4, 0x40, %o4 + EX_LD(LOAD(ldx, %o1 - 0x30, %g3)) + EX_LD(LOAD(ldx, %o1 - 0x28, GLOBAL_SPARE)) + EX_LD(LOAD(ldx, %o1 - 0x20, %o5)) + EX_ST(STORE_INIT(%g1, %o0)) + add %o0, 0x08, %o0 + EX_ST(STORE_INIT(%g2, %o0)) + add %o0, 0x08, %o0 + EX_LD(LOAD(ldx, %o1 - 0x18, %g2)) + EX_ST(STORE_INIT(%g3, %o0)) + add %o0, 0x08, %o0 + EX_LD(LOAD(ldx, %o1 - 0x10, %g3)) + EX_ST(STORE_INIT(GLOBAL_SPARE, %o0)) + add %o0, 0x08, %o0 + EX_LD(LOAD(ldx, %o1 - 0x08, GLOBAL_SPARE)) + EX_ST(STORE_INIT(%o5, %o0)) + add %o0, 0x08, %o0 + EX_ST(STORE_INIT(%g2, %o0)) + add %o0, 0x08, %o0 + EX_ST(STORE_INIT(%g3, %o0)) + add %o0, 0x08, %o0 + EX_ST(STORE_INIT(GLOBAL_SPARE, %o0)) + add %o0, 0x08, %o0 + bne,pt %icc, 1b + LOAD(prefetch, %o1 + 0x200, #n_reads_strong) + + membar #StoreLoad | #StoreStore + + brz,pn %o2, .Lexit + cmp %o2, 19 + ble,pn %icc, .Lsmall_unaligned + nop + ba,a,pt %icc, .Lmedium_noprefetch + +.Lexit: retl + mov EX_RETVAL(%o3), %o0 + +.Llarge_src_unaligned: + andn %o2, 0x3f, %o4 + sub %o2, %o4, %o2 + VISEntryHalf + alignaddr %o1, %g0, %g1 + add %o1, %o4, %o1 + EX_LD(LOAD(ldd, %g1 + 0x00, %f0)) +1: EX_LD(LOAD(ldd, %g1 + 0x08, %f2)) + subcc %o4, 0x40, %o4 + EX_LD(LOAD(ldd, %g1 + 0x10, %f4)) + EX_LD(LOAD(ldd, %g1 + 0x18, %f6)) + EX_LD(LOAD(ldd, %g1 + 0x20, %f8)) + EX_LD(LOAD(ldd, %g1 + 0x28, %f10)) + EX_LD(LOAD(ldd, %g1 + 0x30, %f12)) + EX_LD(LOAD(ldd, %g1 + 0x38, %f14)) + faligndata %f0, %f2, %f16 + EX_LD(LOAD(ldd, %g1 + 0x40, %f0)) + faligndata %f2, %f4, %f18 + add %g1, 0x40, %g1 + faligndata %f4, %f6, %f20 + faligndata %f6, %f8, %f22 + faligndata %f8, %f10, %f24 + faligndata %f10, %f12, %f26 + faligndata %f12, %f14, %f28 + faligndata %f14, %f0, %f30 + EX_ST(STORE(std, %f16, %o0 + 0x00)) + EX_ST(STORE(std, %f18, %o0 + 0x08)) + EX_ST(STORE(std, %f20, %o0 + 0x10)) + EX_ST(STORE(std, %f22, %o0 + 0x18)) + EX_ST(STORE(std, %f24, %o0 + 0x20)) + EX_ST(STORE(std, %f26, %o0 + 0x28)) + EX_ST(STORE(std, %f28, %o0 + 0x30)) + EX_ST(STORE(std, %f30, %o0 + 0x38)) + add %o0, 0x40, %o0 + bne,pt %icc, 1b + LOAD(prefetch, %g1 + 0x200, #n_reads_strong) + VISExitHalf + + brz,pn %o2, .Lexit + cmp %o2, 19 + ble,pn %icc, .Lsmall_unaligned + nop + ba,a,pt %icc, .Lmedium_unaligned + +.Lmedium: + LOAD(prefetch, %o1 + 0x40, #n_reads_strong) + andcc %g2, 0x7, %g0 + bne,pn %icc, .Lmedium_unaligned + nop +.Lmedium_noprefetch: + andncc %o2, 0x20 - 1, %o5 + be,pn %icc, 2f + sub %o2, %o5, %o2 +1: EX_LD(LOAD(ldx, %o1 + 0x00, %g1)) + EX_LD(LOAD(ldx, %o1 + 0x08, %g2)) + EX_LD(LOAD(ldx, %o1 + 0x10, GLOBAL_SPARE)) + EX_LD(LOAD(ldx, %o1 + 0x18, %o4)) + add %o1, 0x20, %o1 + subcc %o5, 0x20, %o5 + EX_ST(STORE(stx, %g1, %o0 + 0x00)) + EX_ST(STORE(stx, %g2, %o0 + 0x08)) + EX_ST(STORE(stx, GLOBAL_SPARE, %o0 + 0x10)) + EX_ST(STORE(stx, %o4, %o0 + 0x18)) + bne,pt %icc, 1b + add %o0, 0x20, %o0 +2: andcc %o2, 0x18, %o5 + be,pt %icc, 3f + sub %o2, %o5, %o2 +1: EX_LD(LOAD(ldx, %o1 + 0x00, %g1)) + add %o1, 0x08, %o1 + add %o0, 0x08, %o0 + subcc %o5, 0x08, %o5 + bne,pt %icc, 1b + EX_ST(STORE(stx, %g1, %o0 - 0x08)) +3: brz,pt %o2, .Lexit + cmp %o2, 0x04 + bl,pn %icc, .Ltiny + nop + EX_LD(LOAD(lduw, %o1 + 0x00, %g1)) + add %o1, 0x04, %o1 + add %o0, 0x04, %o0 + subcc %o2, 0x04, %o2 + bne,pn %icc, .Ltiny + EX_ST(STORE(stw, %g1, %o0 - 0x04)) + ba,a,pt %icc, .Lexit +.Lmedium_unaligned: + /* First get dest 8 byte aligned. */ + sub %g0, %o0, %g1 + and %g1, 0x7, %g1 + brz,pt %g1, 2f + sub %o2, %g1, %o2 + +1: EX_LD(LOAD(ldub, %o1 + 0x00, %g2)) + add %o1, 1, %o1 + subcc %g1, 1, %g1 + add %o0, 1, %o0 + bne,pt %icc, 1b + EX_ST(STORE(stb, %g2, %o0 - 0x01)) +2: + and %o1, 0x7, %g1 + brz,pn %g1, .Lmedium_noprefetch + sll %g1, 3, %g1 + mov 64, %g2 + sub %g2, %g1, %g2 + andn %o1, 0x7, %o1 + EX_LD(LOAD(ldx, %o1 + 0x00, %o4)) + sllx %o4, %g1, %o4 + andn %o2, 0x08 - 1, %o5 + sub %o2, %o5, %o2 +1: EX_LD(LOAD(ldx, %o1 + 0x08, %g3)) + add %o1, 0x08, %o1 + subcc %o5, 0x08, %o5 + srlx %g3, %g2, GLOBAL_SPARE + or GLOBAL_SPARE, %o4, GLOBAL_SPARE + EX_ST(STORE(stx, GLOBAL_SPARE, %o0 + 0x00)) + add %o0, 0x08, %o0 + bne,pt %icc, 1b + sllx %g3, %g1, %o4 + srl %g1, 3, %g1 + add %o1, %g1, %o1 + brz,pn %o2, .Lexit + nop + ba,pt %icc, .Lsmall_unaligned + +.Ltiny: + EX_LD(LOAD(ldub, %o1 + 0x00, %g1)) + subcc %o2, 1, %o2 + be,pn %icc, .Lexit + EX_ST(STORE(stb, %g1, %o0 + 0x00)) + EX_LD(LOAD(ldub, %o1 + 0x01, %g1)) + subcc %o2, 1, %o2 + be,pn %icc, .Lexit + EX_ST(STORE(stb, %g1, %o0 + 0x01)) + EX_LD(LOAD(ldub, %o1 + 0x02, %g1)) + ba,pt %icc, .Lexit + EX_ST(STORE(stb, %g1, %o0 + 0x02)) + +.Lsmall: + andcc %g2, 0x3, %g0 + bne,pn %icc, .Lsmall_unaligned + andn %o2, 0x4 - 1, %o5 + sub %o2, %o5, %o2 +1: + EX_LD(LOAD(lduw, %o1 + 0x00, %g1)) + add %o1, 0x04, %o1 + subcc %o5, 0x04, %o5 + add %o0, 0x04, %o0 + bne,pt %icc, 1b + EX_ST(STORE(stw, %g1, %o0 - 0x04)) + brz,pt %o2, .Lexit + nop + ba,a,pt %icc, .Ltiny + +.Lsmall_unaligned: +1: EX_LD(LOAD(ldub, %o1 + 0x00, %g1)) + add %o1, 1, %o1 + add %o0, 1, %o0 + subcc %o2, 1, %o2 + bne,pt %icc, 1b + EX_ST(STORE(stb, %g1, %o0 - 0x01)) + ba,a,pt %icc, .Lexit +END(__memcpy_niagara4) + +#endif diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memcpy-ultra3.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memcpy-ultra3.S new file mode 100644 index 0000000000..b8f5c3cb8f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memcpy-ultra3.S @@ -0,0 +1,325 @@ +/* Copy SIZE bytes from SRC to DEST. + For UltraSPARC-III. + Copyright (C) 2001-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller (davem@redhat.com) + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +#define ASI_BLK_P 0xf0 +#define FPRS_FEF 0x04 +#define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs +#define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs + +#ifndef XCC +#define USE_BPR +#define XCC xcc +#endif + +#if IS_IN (libc) + + .register %g2,#scratch + .register %g3,#scratch + .register %g6,#scratch + + .text + +ENTRY(__mempcpy_ultra3) + ba,pt %XCC, 101f + add %o0, %o2, %g5 +END(__mempcpy_ultra3) + + /* Special/non-trivial issues of this code: + * + * 1) %o5 is preserved from VISEntryHalf to VISExitHalf + * 2) Only low 32 FPU registers are used so that only the + * lower half of the FPU register set is dirtied by this + * code. This is especially important in the kernel. + * 3) This code never prefetches cachelines past the end + * of the source buffer. + * + * The cheetah's flexible spine, oversized liver, enlarged heart, + * slender muscular body, and claws make it the swiftest hunter + * in Africa and the fastest animal on land. Can reach speeds + * of up to 2.4GB per second. + */ + .align 32 +ENTRY(__memcpy_ultra3) + +100: /* %o0=dst, %o1=src, %o2=len */ + mov %o0, %g5 +101: + cmp %o2, 0 + be,pn %XCC, out +218: or %o0, %o1, %o3 + cmp %o2, 16 + bleu,a,pn %XCC, small_copy + or %o3, %o2, %o3 + + cmp %o2, 256 + blu,pt %XCC, medium_copy + andcc %o3, 0x7, %g0 + + ba,pt %xcc, enter + andcc %o0, 0x3f, %g2 + + /* Here len >= 256 and condition codes reflect execution + * of "andcc %o0, 0x7, %g2", done by caller. + */ + .align 64 +enter: + /* Is 'dst' already aligned on an 64-byte boundary? */ + be,pt %XCC, 2f + + /* Compute abs((dst & 0x3f) - 0x40) into %g2. This is the number + * of bytes to copy to make 'dst' 64-byte aligned. We pre- + * subtract this from 'len'. + */ + sub %g2, 0x40, %g2 + sub %g0, %g2, %g2 + sub %o2, %g2, %o2 + + /* Copy %g2 bytes from src to dst, one byte at a time. */ +1: ldub [%o1 + 0x00], %o3 + add %o1, 0x1, %o1 + add %o0, 0x1, %o0 + subcc %g2, 0x1, %g2 + + bg,pt %XCC, 1b + stb %o3, [%o0 + -1] + +2: VISEntryHalf + and %o1, 0x7, %g1 + ba,pt %xcc, begin + alignaddr %o1, %g0, %o1 + + .align 64 +begin: + prefetch [%o1 + 0x000], #one_read + prefetch [%o1 + 0x040], #one_read + andn %o2, (0x40 - 1), %o4 + prefetch [%o1 + 0x080], #one_read + prefetch [%o1 + 0x0c0], #one_read + ldd [%o1 + 0x000], %f0 + prefetch [%o1 + 0x100], #one_read + ldd [%o1 + 0x008], %f2 + prefetch [%o1 + 0x140], #one_read + ldd [%o1 + 0x010], %f4 + prefetch [%o1 + 0x180], #one_read + faligndata %f0, %f2, %f16 + ldd [%o1 + 0x018], %f6 + faligndata %f2, %f4, %f18 + ldd [%o1 + 0x020], %f8 + faligndata %f4, %f6, %f20 + ldd [%o1 + 0x028], %f10 + faligndata %f6, %f8, %f22 + + ldd [%o1 + 0x030], %f12 + faligndata %f8, %f10, %f24 + ldd [%o1 + 0x038], %f14 + faligndata %f10, %f12, %f26 + ldd [%o1 + 0x040], %f0 + + sub %o4, 0x80, %o4 + add %o1, 0x40, %o1 + ba,pt %xcc, loop + srl %o4, 6, %o3 + + .align 64 +loop: + ldd [%o1 + 0x008], %f2 + faligndata %f12, %f14, %f28 + ldd [%o1 + 0x010], %f4 + faligndata %f14, %f0, %f30 + stda %f16, [%o0] ASI_BLK_P + ldd [%o1 + 0x018], %f6 + faligndata %f0, %f2, %f16 + + ldd [%o1 + 0x020], %f8 + faligndata %f2, %f4, %f18 + ldd [%o1 + 0x028], %f10 + faligndata %f4, %f6, %f20 + ldd [%o1 + 0x030], %f12 + faligndata %f6, %f8, %f22 + ldd [%o1 + 0x038], %f14 + faligndata %f8, %f10, %f24 + + ldd [%o1 + 0x040], %f0 + prefetch [%o1 + 0x180], #one_read + faligndata %f10, %f12, %f26 + subcc %o3, 0x01, %o3 + add %o1, 0x40, %o1 + bg,pt %XCC, loop + add %o0, 0x40, %o0 + + /* Finally we copy the last full 64-byte block. */ +loopfini: + ldd [%o1 + 0x008], %f2 + faligndata %f12, %f14, %f28 + ldd [%o1 + 0x010], %f4 + faligndata %f14, %f0, %f30 + stda %f16, [%o0] ASI_BLK_P + ldd [%o1 + 0x018], %f6 + faligndata %f0, %f2, %f16 + ldd [%o1 + 0x020], %f8 + faligndata %f2, %f4, %f18 + ldd [%o1 + 0x028], %f10 + faligndata %f4, %f6, %f20 + ldd [%o1 + 0x030], %f12 + faligndata %f6, %f8, %f22 + ldd [%o1 + 0x038], %f14 + faligndata %f8, %f10, %f24 + cmp %g1, 0 + be,pt %XCC, 1f + add %o0, 0x40, %o0 + ldd [%o1 + 0x040], %f0 +1: faligndata %f10, %f12, %f26 + faligndata %f12, %f14, %f28 + faligndata %f14, %f0, %f30 + stda %f16, [%o0] ASI_BLK_P + add %o0, 0x40, %o0 + add %o1, 0x40, %o1 + membar #Sync + + /* Now we copy the (len modulo 64) bytes at the end. + * Note how we borrow the %f0 loaded above. + * + * Also notice how this code is careful not to perform a + * load past the end of the src buffer. + */ +loopend: + and %o2, 0x3f, %o2 + andcc %o2, 0x38, %g2 + be,pn %XCC, endcruft + subcc %g2, 0x8, %g2 + be,pn %XCC, endcruft + cmp %g1, 0 + + be,a,pt %XCC, 1f + ldd [%o1 + 0x00], %f0 + +1: ldd [%o1 + 0x08], %f2 + add %o1, 0x8, %o1 + sub %o2, 0x8, %o2 + subcc %g2, 0x8, %g2 + faligndata %f0, %f2, %f8 + std %f8, [%o0 + 0x00] + be,pn %XCC, endcruft + add %o0, 0x8, %o0 + ldd [%o1 + 0x08], %f0 + add %o1, 0x8, %o1 + sub %o2, 0x8, %o2 + subcc %g2, 0x8, %g2 + faligndata %f2, %f0, %f8 + std %f8, [%o0 + 0x00] + bne,pn %XCC, 1b + add %o0, 0x8, %o0 + + /* If anything is left, we copy it one byte at a time. + * Note that %g1 is (src & 0x3) saved above before the + * alignaddr was performed. + */ +endcruft: + cmp %o2, 0 + add %o1, %g1, %o1 + VISExitHalf + be,pn %XCC, out + sub %o0, %o1, %o3 + + andcc %g1, 0x7, %g0 + bne,pn %icc, small_copy_unaligned + andcc %o2, 0x8, %g0 + be,pt %icc, 1f + nop + ldx [%o1], %o5 + stx %o5, [%o1 + %o3] + add %o1, 0x8, %o1 + +1: andcc %o2, 0x4, %g0 + be,pt %icc, 1f + nop + lduw [%o1], %o5 + stw %o5, [%o1 + %o3] + add %o1, 0x4, %o1 + +1: andcc %o2, 0x2, %g0 + be,pt %icc, 1f + nop + lduh [%o1], %o5 + sth %o5, [%o1 + %o3] + add %o1, 0x2, %o1 + +1: andcc %o2, 0x1, %g0 + be,pt %icc, out + nop + ldub [%o1], %o5 + ba,pt %xcc, out + stb %o5, [%o1 + %o3] + +medium_copy: /* 16 < len <= 64 */ + bne,pn %XCC, small_copy_unaligned + sub %o0, %o1, %o3 + +medium_copy_aligned: + andn %o2, 0x7, %o4 + and %o2, 0x7, %o2 +1: subcc %o4, 0x8, %o4 + ldx [%o1], %o5 + stx %o5, [%o1 + %o3] + bgu,pt %XCC, 1b + add %o1, 0x8, %o1 + andcc %o2, 0x4, %g0 + be,pt %XCC, 1f + nop + sub %o2, 0x4, %o2 + lduw [%o1], %o5 + stw %o5, [%o1 + %o3] + add %o1, 0x4, %o1 +1: cmp %o2, 0 + be,pt %XCC, out + nop + ba,pt %xcc, small_copy_unaligned + nop + +small_copy: /* 0 < len <= 16 */ + andcc %o3, 0x3, %g0 + bne,pn %XCC, small_copy_unaligned + sub %o0, %o1, %o3 + +small_copy_aligned: + subcc %o2, 4, %o2 + lduw [%o1], %g1 + stw %g1, [%o1 + %o3] + bgu,pt %XCC, small_copy_aligned + add %o1, 4, %o1 + +out: retl + mov %g5, %o0 + + .align 32 +small_copy_unaligned: + subcc %o2, 1, %o2 + ldub [%o1], %g1 + stb %g1, [%o1 + %o3] + bgu,pt %XCC, small_copy_unaligned + add %o1, 1, %o1 + retl + mov %g5, %o0 + +END(__memcpy_ultra3) + +#endif
\ No newline at end of file diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memcpy.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memcpy.S new file mode 100644 index 0000000000..b6396eeae5 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memcpy.S @@ -0,0 +1,167 @@ +/* Multiple versions of memcpy + All versions must be listed in ifunc-impl-list.c. + Copyright (C) 2010-2017 Free Software Foundation, Inc. + Contributed by David S. Miller (davem@davemloft.net) + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +#if IS_IN (libc) + .text +ENTRY(memcpy) + .type memcpy, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif + set HWCAP_SPARC_CRYPTO, %o1 + andcc %o0, %o1, %g0 + be 1f + andcc %o0, HWCAP_SPARC_N2, %g0 +# ifdef SHARED + sethi %gdop_hix22(__memcpy_niagara4), %o1 + xor %o1, %gdop_lox10(__memcpy_niagara4), %o1 +# else + set __memcpy_niagara4, %o1 +# endif + ba 10f + nop +1: be 1f + andcc %o0, HWCAP_SPARC_BLKINIT, %g0 +# ifdef SHARED + sethi %gdop_hix22(__memcpy_niagara2), %o1 + xor %o1, %gdop_lox10(__memcpy_niagara2), %o1 +# else + set __memcpy_niagara2, %o1 +# endif + ba 10f + nop +1: be 1f + andcc %o0, HWCAP_SPARC_ULTRA3, %g0 +# ifdef SHARED + sethi %gdop_hix22(__memcpy_niagara1), %o1 + xor %o1, %gdop_lox10(__memcpy_niagara1), %o1 +# else + set __memcpy_niagara1, %o1 +# endif + ba 10f + nop +1: be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__memcpy_ultra3), %o1 + xor %o1, %gdop_lox10(__memcpy_ultra3), %o1 +# else + set __memcpy_ultra3, %o1 +# endif + ba 10f + nop +9: +# ifdef SHARED + sethi %gdop_hix22(__memcpy_ultra1), %o1 + xor %o1, %gdop_lox10(__memcpy_ultra1), %o1 +# else + set __memcpy_ultra1, %o1 +# endif +10: +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(memcpy) + +ENTRY(__mempcpy) + .type __mempcpy, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif + set HWCAP_SPARC_CRYPTO, %o1 + andcc %o0, %o1, %g0 + be 1f + andcc %o0, HWCAP_SPARC_N2, %g0 +# ifdef SHARED + sethi %gdop_hix22(__mempcpy_niagara4), %o1 + xor %o1, %gdop_lox10(__mempcpy_niagara4), %o1 +# else + set __mempcpy_niagara4, %o1 +# endif + ba 10f + nop +1: be 1f + andcc %o0, HWCAP_SPARC_BLKINIT, %g0 +# ifdef SHARED + sethi %gdop_hix22(__mempcpy_niagara2), %o1 + xor %o1, %gdop_lox10(__mempcpy_niagara2), %o1 +# else + set __mempcpy_niagara2, %o1 +# endif + ba 10f + nop +1: be 1f + andcc %o0, HWCAP_SPARC_ULTRA3, %g0 +# ifdef SHARED + sethi %gdop_hix22(__mempcpy_niagara1), %o1 + xor %o1, %gdop_lox10(__mempcpy_niagara1), %o1 +# else + set __mempcpy_niagara1, %o1 +# endif + ba 10f + nop +1: be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__mempcpy_ultra3), %o1 + xor %o1, %gdop_lox10(__mempcpy_ultra3), %o1 +# else + set __mempcpy_ultra3, %o1 +# endif + ba 10f + nop +9: +# ifdef SHARED + sethi %gdop_hix22(__mempcpy_ultra1), %o1 + xor %o1, %gdop_lox10(__mempcpy_ultra1), %o1 +# else + set __mempcpy_ultra1, %o1 +# endif +10: +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__mempcpy) + +libc_hidden_builtin_def (memcpy) + +libc_hidden_def (__mempcpy) +weak_alias (__mempcpy, mempcpy) +libc_hidden_builtin_def (mempcpy) + +#undef libc_hidden_builtin_def +#define libc_hidden_builtin_def(name) +#undef weak_alias +#define weak_alias(x, y) +#undef libc_hidden_def +#define libc_hidden_def(name) + +#define memcpy __memcpy_ultra1 +#define __mempcpy __mempcpy_ultra1 + +#endif + +#include "../memcpy.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memset-niagara1.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memset-niagara1.S new file mode 100644 index 0000000000..45b2251691 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memset-niagara1.S @@ -0,0 +1,177 @@ +/* Set a block of memory to some byte value. For SUN4V Niagara. + Copyright (C) 2006-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller (davem@davemloft.net) + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +#define ASI_BLK_INIT_QUAD_LDD_P 0xe2 +#define ASI_P 0x80 +#define ASI_PNF 0x82 + +#ifndef XCC +#define USE_BPR +#define XCC xcc +#endif + +#if IS_IN (libc) + + .register %g2,#scratch + + .text + .align 32 + +ENTRY(__memset_niagara1) + /* %o0=buf, %o1=pat, %o2=len */ + and %o1, 0xff, %o3 + mov %o2, %o1 + sllx %o3, 8, %g1 + or %g1, %o3, %o2 + sllx %o2, 16, %g1 + or %g1, %o2, %o2 + sllx %o2, 32, %g1 + ba,pt %XCC, 1f + or %g1, %o2, %o2 +END(__memset_niagara1) + +ENTRY(__bzero_niagara1) + clr %o2 +1: +# ifndef USE_BRP + srl %o1, 0, %o1 +# endif + brz,pn %o1, 90f + mov %o0, %o3 + + wr %g0, ASI_P, %asi + + cmp %o1, 15 + blu,pn %XCC, 70f + andcc %o0, 0x7, %g1 + be,pt %XCC, 2f + mov 8, %g2 + sub %g2, %g1, %g1 + sub %o1, %g1, %o1 +1: stba %o2, [%o0 + 0x00] %asi + subcc %g1, 1, %g1 + bne,pt %XCC, 1b + add %o0, 1, %o0 +2: cmp %o1, 128 + blu,pn %XCC, 60f + andcc %o0, (64 - 1), %g1 + be,pt %XCC, 40f + mov 64, %g2 + sub %g2, %g1, %g1 + sub %o1, %g1, %o1 +1: stxa %o2, [%o0 + 0x00] %asi + subcc %g1, 8, %g1 + bne,pt %XCC, 1b + add %o0, 8, %o0 + +40: + wr %g0, ASI_BLK_INIT_QUAD_LDD_P, %asi + andn %o1, (64 - 1), %g1 + sub %o1, %g1, %o1 + + andn %g1, (256 - 1), %g2 + brz,pt %g2, 50f + and %g1, (256 - 1), %g1 + +45: + stxa %o2, [%o0 + 0x00] %asi + stxa %o2, [%o0 + 0x08] %asi + stxa %o2, [%o0 + 0x10] %asi + stxa %o2, [%o0 + 0x18] %asi + stxa %o2, [%o0 + 0x20] %asi + stxa %o2, [%o0 + 0x28] %asi + stxa %o2, [%o0 + 0x30] %asi + stxa %o2, [%o0 + 0x38] %asi + stxa %o2, [%o0 + 0x40] %asi + stxa %o2, [%o0 + 0x48] %asi + stxa %o2, [%o0 + 0x50] %asi + stxa %o2, [%o0 + 0x58] %asi + stxa %o2, [%o0 + 0x60] %asi + stxa %o2, [%o0 + 0x68] %asi + stxa %o2, [%o0 + 0x70] %asi + stxa %o2, [%o0 + 0x78] %asi + stxa %o2, [%o0 + 0x80] %asi + stxa %o2, [%o0 + 0x88] %asi + stxa %o2, [%o0 + 0x90] %asi + stxa %o2, [%o0 + 0x98] %asi + stxa %o2, [%o0 + 0xa0] %asi + stxa %o2, [%o0 + 0xa8] %asi + stxa %o2, [%o0 + 0xb0] %asi + stxa %o2, [%o0 + 0xb8] %asi + stxa %o2, [%o0 + 0xc0] %asi + stxa %o2, [%o0 + 0xc8] %asi + stxa %o2, [%o0 + 0xd0] %asi + stxa %o2, [%o0 + 0xd8] %asi + stxa %o2, [%o0 + 0xe0] %asi + stxa %o2, [%o0 + 0xe8] %asi + stxa %o2, [%o0 + 0xf0] %asi + stxa %o2, [%o0 + 0xf8] %asi + subcc %g2, 256, %g2 + bne,pt %XCC, 45b + add %o0, 256, %o0 + + brz,pn %g1, 55f + nop + +50: + stxa %o2, [%o0 + 0x00] %asi + stxa %o2, [%o0 + 0x08] %asi + stxa %o2, [%o0 + 0x10] %asi + stxa %o2, [%o0 + 0x18] %asi + stxa %o2, [%o0 + 0x20] %asi + stxa %o2, [%o0 + 0x28] %asi + stxa %o2, [%o0 + 0x30] %asi + stxa %o2, [%o0 + 0x38] %asi + subcc %g1, 64, %g1 + bne,pt %XCC, 50b + add %o0, 64, %o0 + +55: + wr %g0, ASI_P, %asi + brz,pn %o1, 80f +60: + andncc %o1, 0x7, %g1 + be,pn %XCC, 2f + sub %o1, %g1, %o1 +1: stxa %o2, [%o0 + 0x00] %asi + subcc %g1, 8, %g1 + bne,pt %XCC, 1b + add %o0, 8, %o0 +2: brz,pt %o1, 80f + nop + +70: +1: stba %o2, [%o0 + 0x00] %asi + subcc %o1, 1, %o1 + bne,pt %XCC, 1b + add %o0, 1, %o0 + + /* fallthrough */ + +80: + wr %g0, ASI_PNF, %asi + +90: + retl + mov %o3, %o0 +END(__bzero_niagara1) + +#endif diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memset-niagara4.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memset-niagara4.S new file mode 100644 index 0000000000..c04a07a7f9 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memset-niagara4.S @@ -0,0 +1,124 @@ +/* Set a block of memory to some byte value. For SUN4V Niagara-4. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller (davem@davemloft.net) + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +#define ASI_BLK_INIT_QUAD_LDD_P 0xe2 + +#if IS_IN (libc) + + .register %g2, #scratch + .register %g3, #scratch + + .text + .align 32 + +ENTRY(__memset_niagara4) + andcc %o1, 0xff, %o4 + be,pt %icc, 1f + mov %o2, %o1 + sllx %o4, 8, %g1 + or %g1, %o4, %o2 + sllx %o2, 16, %g1 + or %g1, %o2, %o2 + sllx %o2, 32, %g1 + ba,pt %icc, 1f + or %g1, %o2, %o4 +END(__memset_niagara4) + + .align 32 +ENTRY(__bzero_niagara4) + clr %o4 +1: cmp %o1, 16 + ble %icc, .Ltiny + mov %o0, %o3 + sub %g0, %o0, %g1 + and %g1, 0x7, %g1 + brz,pt %g1, .Laligned8 + sub %o1, %g1, %o1 +1: stb %o4, [%o0 + 0x00] + subcc %g1, 1, %g1 + bne,pt %icc, 1b + add %o0, 1, %o0 +.Laligned8: + cmp %o1, 64 + (64 - 8) + ble .Lmedium + sub %g0, %o0, %g1 + andcc %g1, (64 - 1), %g1 + brz,pn %g1, .Laligned64 + sub %o1, %g1, %o1 +1: stx %o4, [%o0 + 0x00] + subcc %g1, 8, %g1 + bne,pt %icc, 1b + add %o0, 0x8, %o0 +.Laligned64: + andn %o1, 64 - 1, %g1 + sub %o1, %g1, %o1 + brnz,pn %o4, .Lnon_bzero_loop + mov 0x20, %g2 +1: stxa %o4, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P + subcc %g1, 0x40, %g1 + stxa %o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P + bne,pt %icc, 1b + add %o0, 0x40, %o0 +.Lpostloop: + cmp %o1, 8 + bl,pn %icc, .Ltiny + membar #StoreStore|#StoreLoad +.Lmedium: + andn %o1, 0x7, %g1 + sub %o1, %g1, %o1 +1: stx %o4, [%o0 + 0x00] + subcc %g1, 0x8, %g1 + bne,pt %icc, 1b + add %o0, 0x08, %o0 + andcc %o1, 0x4, %g1 + be,pt %icc, .Ltiny + sub %o1, %g1, %o1 + stw %o4, [%o0 + 0x00] + add %o0, 0x4, %o0 +.Ltiny: + cmp %o1, 0 + be,pn %icc, .Lexit +1: subcc %o1, 1, %o1 + stb %o4, [%o0 + 0x00] + bne,pt %icc, 1b + add %o0, 1, %o0 +.Lexit: + retl + mov %o3, %o0 +.Lnon_bzero_loop: + mov 0x08, %g3 + mov 0x28, %o5 +1: stxa %o4, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P + subcc %g1, 0x40, %g1 + stxa %o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P + stxa %o4, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P + stxa %o4, [%o0 + %o5] ASI_BLK_INIT_QUAD_LDD_P + add %o0, 0x10, %o0 + stxa %o4, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P + stxa %o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P + stxa %o4, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P + stxa %o4, [%o0 + %o5] ASI_BLK_INIT_QUAD_LDD_P + bne,pt %icc, 1b + add %o0, 0x30, %o0 + ba,a,pt %icc, .Lpostloop +END(__bzero_niagara4) + +#endif diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memset.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memset.S new file mode 100644 index 0000000000..9469d5e7ce --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/memset.S @@ -0,0 +1,124 @@ +/* Multiple versions of memset and bzero + All versions must be listed in ifunc-impl-list.c. + Copyright (C) 2010-2017 Free Software Foundation, Inc. + Contributed by David S. Miller (davem@davemloft.net) + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +#if IS_IN (libc) + .text +ENTRY(memset) + .type memset, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif + set HWCAP_SPARC_CRYPTO, %o1 + andcc %o0, %o1, %g0 + be 1f + andcc %o0, HWCAP_SPARC_BLKINIT, %g0 +# ifdef SHARED + sethi %gdop_hix22(__memset_niagara4), %o1 + xor %o1, %gdop_lox10(__memset_niagara4), %o1 +# else + set __memset_niagara4, %o1 +# endif + ba 10f + nop +1: be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__memset_niagara1), %o1 + xor %o1, %gdop_lox10(__memset_niagara1), %o1 +# else + set __memset_niagara1, %o1 +# endif + ba 10f + nop +9: +# ifdef SHARED + sethi %gdop_hix22(__memset_ultra1), %o1 + xor %o1, %gdop_lox10(__memset_ultra1), %o1 +# else + set __memset_ultra1, %o1 +# endif +10: +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(memset) + +ENTRY(__bzero) + .type bzero, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif + set HWCAP_SPARC_CRYPTO, %o1 + andcc %o0, %o1, %g0 + be 1f + andcc %o0, HWCAP_SPARC_BLKINIT, %g0 +# ifdef SHARED + sethi %gdop_hix22(__bzero_niagara4), %o1 + xor %o1, %gdop_lox10(__bzero_niagara4), %o1 +# else + set __bzero_niagara4, %o1 +# endif + ba 10f + nop +1: be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__bzero_niagara1), %o1 + xor %o1, %gdop_lox10(__bzero_niagara1), %o1 +# else + set __bzero_niagara1, %o1 +# endif + ba 10f + nop +9: +# ifdef SHARED + sethi %gdop_hix22(__bzero_ultra1), %o1 + xor %o1, %gdop_lox10(__bzero_ultra1), %o1 +# else + set __bzero_ultra1, %o1 +# endif +10: +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__bzero) + +weak_alias (__bzero, bzero) + +# undef weak_alias +# define weak_alias(a, b) + +libc_hidden_builtin_def (memset) + +#undef libc_hidden_builtin_def +#define libc_hidden_builtin_def(name) + +#define memset __memset_ultra1 +#define __bzero __bzero_ultra1 + +#endif + +#include "../memset.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/mul_1-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/mul_1-vis3.S new file mode 100644 index 0000000000..7c4fa49ce4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/mul_1-vis3.S @@ -0,0 +1,73 @@ +! SPARC v9 64-bit VIS3 __mpn_mul_1 -- Multiply a limb vector with a single +! limb and store the product in a second limb vector. +! +! Copyright (C) 2013-2017 Free Software Foundation, Inc. +! This file is part of the GNU C Library. +! Contributed by David S. Miller <davem@davemloft.net> +! +! The GNU C Library is free software; you can redistribute it and/or +! modify it under the terms of the GNU Lesser General Public +! License as published by the Free Software Foundation; either +! version 2.1 of the License, or (at your option) any later version. +! +! The GNU C Library is distributed in the hope that it will be useful, +! but WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! Lesser General Public License for more details. +! +! You should have received a copy of the GNU Lesser General Public +! License along with the GNU C Library; if not, see +! <http://www.gnu.org/licenses/>. + +#include <sysdep.h> + +#define res_ptr %o0 +#define s1_ptr %o1 +#define sz %o2 +#define s2_limb %o3 +#define carry %o5 +#define tmp1 %g1 +#define tmp2 %g2 +#define tmp3 %g3 +#define tmp4 %o4 + + .register %g2,#scratch + .register %g3,#scratch +ENTRY(__mpn_mul_1_vis3) + subcc sz, 1, sz + be .Lfinal_limb + clr carry + +.Lloop: + ldx [s1_ptr + 0x00], tmp1 + ldx [s1_ptr + 0x08], tmp4 + mulx tmp1, s2_limb, tmp3 + add s1_ptr, 0x10, s1_ptr + umulxhi tmp1, s2_limb, tmp2 + sub sz, 2, sz + mulx tmp4, s2_limb, tmp1 + add res_ptr, 0x10, res_ptr + umulxhi tmp4, s2_limb, tmp4 + addcc carry, tmp3, tmp3 + stx tmp3, [res_ptr - 0x10] + addxc %g0, tmp2, carry + addcc carry, tmp1, tmp1 + addxc %g0, tmp4, carry + brgz sz, .Lloop + stx tmp1, [res_ptr - 0x08] + + brlz,pt sz, .Lfinish + nop + +.Lfinal_limb: + ldx [s1_ptr + 0x00], tmp1 + mulx tmp1, s2_limb, tmp3 + umulxhi tmp1, s2_limb, tmp2 + addcc carry, tmp3, tmp3 + addxc %g0, tmp2, carry + stx tmp3, [res_ptr + 0x00] + +.Lfinish: + retl + mov carry, %o0 +END(__mpn_mul_1_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/mul_1.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/mul_1.S new file mode 100644 index 0000000000..75fca932b7 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/mul_1.S @@ -0,0 +1,56 @@ +/* Multiple versions of mul_1 + + Copyright (C) 2013-2017 Free Software Foundation, Inc. + Contributed by David S. Miller (davem@davemloft.net) + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__mpn_mul_1) + .type __mpn_mul_1, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 1f + nop +# ifdef SHARED + sethi %gdop_hix22(__mpn_mul_1_vis3), %o1 + xor %o1, %gdop_lox10(__mpn_mul_1_vis3), %o1 +# else + set __mpn_mul_1_vis3, %o1 +# endif + ba 10f + nop +1: +# ifdef SHARED + sethi %gdop_hix22(__mpn_mul_1_generic), %o1 + xor %o1, %gdop_lox10(__mpn_mul_1_generic), %o1 +# else + set __mpn_mul_1_generic, %o1 +# endif +10: +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__mpn_mul_1) + +#define __mpn_mul_1 __mpn_mul_1_generic +#include "../mul_1.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/rtld-memcpy.c b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/rtld-memcpy.c new file mode 100644 index 0000000000..2452575343 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/rtld-memcpy.c @@ -0,0 +1 @@ +#include "../rtld-memcpy.c" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/rtld-memset.c b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/rtld-memset.c new file mode 100644 index 0000000000..c01eb0beb9 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/rtld-memset.c @@ -0,0 +1 @@ +#include "../rtld-memset.c" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/sha256-block.c b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/sha256-block.c new file mode 100644 index 0000000000..9d65315a5a --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/sha256-block.c @@ -0,0 +1,32 @@ +#include <sparc-ifunc.h> + +#define __sha256_process_block __sha256_process_block_generic +extern void __sha256_process_block_generic (const void *buffer, size_t len, + struct sha256_ctx *ctx); + +#include <crypt/sha256-block.c> + +#undef __sha256_process_block + +extern void __sha256_process_block_crop (const void *buffer, size_t len, + struct sha256_ctx *ctx); + +static bool cpu_supports_sha256(int hwcap) +{ + unsigned long cfr; + + if (!(hwcap & HWCAP_SPARC_CRYPTO)) + return false; + + __asm__ ("rd %%asr26, %0" : "=r" (cfr)); + if (cfr & (1 << 6)) + return true; + + return false; +} + +extern void __sha256_process_block (const void *buffer, size_t len, + struct sha256_ctx *ctx); +sparc_libc_ifunc (__sha256_process_block, + cpu_supports_sha256(hwcap) ? __sha256_process_block_crop + : __sha256_process_block_generic); diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/sha256-crop.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/sha256-crop.S new file mode 100644 index 0000000000..8f07e4245a --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/sha256-crop.S @@ -0,0 +1,101 @@ +/* SHA256 using sparc crypto opcodes. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller (davem@davemloft.net) + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +#define SHA256 \ + .word 0x81b02840; + + .text + .align 32 +ENTRY(__sha256_process_block_crop) + /* %o0=buffer, %o1=len, %o2=CTX */ + ldx [%o2 + 0x20], %g1 + add %g1, %o1, %g1 + stx %g1, [%o2 + 0x20] + + ld [%o2 + 0x00], %f0 + ld [%o2 + 0x04], %f1 + ld [%o2 + 0x08], %f2 + ld [%o2 + 0x0c], %f3 + ld [%o2 + 0x10], %f4 + ld [%o2 + 0x14], %f5 + andcc %o1, 0x7, %g0 + ld [%o2 + 0x18], %f6 + bne,pn %xcc, 10f + ld [%o2 + 0x1c], %f7 + +1: + ldd [%o0 + 0x00], %f8 + ldd [%o0 + 0x08], %f10 + ldd [%o0 + 0x10], %f12 + ldd [%o0 + 0x18], %f14 + ldd [%o0 + 0x20], %f16 + ldd [%o0 + 0x28], %f18 + ldd [%o0 + 0x30], %f20 + ldd [%o0 + 0x38], %f22 + + SHA256 + + subcc %o1, 0x40, %o1 + bne,pt %xcc, 1b + add %o0, 0x40, %o0 + +5: + st %f0, [%o2 + 0x00] + st %f1, [%o2 + 0x04] + st %f2, [%o2 + 0x08] + st %f3, [%o2 + 0x0c] + st %f4, [%o2 + 0x10] + st %f5, [%o2 + 0x14] + st %f6, [%o2 + 0x18] + retl + st %f7, [%o2 + 0x1c] +10: + alignaddr %o0, %g0, %o0 + + ldd [%o0 + 0x00], %f10 +1: + ldd [%o0 + 0x08], %f12 + ldd [%o0 + 0x10], %f14 + ldd [%o0 + 0x18], %f16 + ldd [%o0 + 0x20], %f18 + ldd [%o0 + 0x28], %f20 + ldd [%o0 + 0x30], %f22 + ldd [%o0 + 0x38], %f24 + ldd [%o0 + 0x40], %f26 + + faligndata %f10, %f12, %f8 + faligndata %f12, %f14, %f10 + faligndata %f14, %f16, %f12 + faligndata %f16, %f18, %f14 + faligndata %f18, %f20, %f16 + faligndata %f20, %f22, %f18 + faligndata %f22, %f24, %f20 + faligndata %f24, %f26, %f22 + + SHA256 + + subcc %o1, 0x40, %o1 + fsrc2 %f26, %f10 + bne,pt %xcc, 1b + add %o0, 0x40, %o0 + + ba,a,pt %xcc, 5b +END(__sha256_process_block_crop) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/sha512-block.c b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/sha512-block.c new file mode 100644 index 0000000000..2863e05d09 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/sha512-block.c @@ -0,0 +1,32 @@ +#include <sparc-ifunc.h> + +#define __sha512_process_block __sha512_process_block_generic +extern void __sha512_process_block_generic (const void *buffer, size_t len, + struct sha512_ctx *ctx); + +#include <crypt/sha512-block.c> + +#undef __sha512_process_block + +extern void __sha512_process_block_crop (const void *buffer, size_t len, + struct sha512_ctx *ctx); + +static bool cpu_supports_sha512(int hwcap) +{ + unsigned long cfr; + + if (!(hwcap & HWCAP_SPARC_CRYPTO)) + return false; + + __asm__ ("rd %%asr26, %0" : "=r" (cfr)); + if (cfr & (1 << 6)) + return true; + + return false; +} + +extern void __sha512_process_block (const void *buffer, size_t len, + struct sha512_ctx *ctx); +sparc_libc_ifunc (__sha512_process_block, + cpu_supports_sha512(hwcap) ? __sha512_process_block_crop + : __sha512_process_block_generic); diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/sha512-crop.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/sha512-crop.S new file mode 100644 index 0000000000..f78354c485 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/sha512-crop.S @@ -0,0 +1,131 @@ +/* SHA512 using sparc crypto opcodes. + Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller (davem@davemloft.net) + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +#define SHA512 \ + .word 0x81b02860; + + .text + .align 32 +ENTRY(__sha512_process_block_crop) + /* %o0=buffer, %o1=len, %o2=CTX */ + ldx [%o2 + 0x48], %g1 + add %g1, %o1, %o4 + stx %o4, [%o2 + 0x48] + cmp %o4, %g1 + bgeu,pt %xcc, 1f + nop + ldx [%o2 + 0x40], %g1 + add %g1, 1, %g1 + stx %g1, [%o2 + 0x40] + +1: ldd [%o2 + 0x00], %f0 + ldd [%o2 + 0x08], %f2 + ldd [%o2 + 0x10], %f4 + ldd [%o2 + 0x18], %f6 + ldd [%o2 + 0x20], %f8 + ldd [%o2 + 0x28], %f10 + andcc %o1, 0x7, %g0 + ldd [%o2 + 0x30], %f12 + bne,pn %xcc, 10f + ldd [%o2 + 0x38], %f14 + +1: + ldd [%o0 + 0x00], %f16 + ldd [%o0 + 0x08], %f18 + ldd [%o0 + 0x10], %f20 + ldd [%o0 + 0x18], %f22 + ldd [%o0 + 0x20], %f24 + ldd [%o0 + 0x28], %f26 + ldd [%o0 + 0x30], %f28 + ldd [%o0 + 0x38], %f30 + ldd [%o0 + 0x40], %f32 + ldd [%o0 + 0x48], %f34 + ldd [%o0 + 0x50], %f36 + ldd [%o0 + 0x58], %f38 + ldd [%o0 + 0x60], %f40 + ldd [%o0 + 0x68], %f42 + ldd [%o0 + 0x70], %f44 + ldd [%o0 + 0x78], %f46 + + SHA512 + + subcc %o1, 0x80, %o1 + bne,pt %xcc, 1b + add %o0, 0x80, %o0 + +5: + std %f0, [%o2 + 0x00] + std %f2, [%o2 + 0x08] + std %f4, [%o2 + 0x10] + std %f6, [%o2 + 0x18] + std %f8, [%o2 + 0x20] + std %f10, [%o2 + 0x28] + std %f12, [%o2 + 0x30] + retl + std %f14, [%o2 + 0x38] +10: + alignaddr %o0, %g0, %o0 + + ldd [%o0 + 0x00], %f18 +1: + ldd [%o0 + 0x08], %f20 + ldd [%o0 + 0x10], %f22 + ldd [%o0 + 0x18], %f24 + ldd [%o0 + 0x20], %f26 + ldd [%o0 + 0x28], %f28 + ldd [%o0 + 0x30], %f30 + ldd [%o0 + 0x38], %f32 + ldd [%o0 + 0x40], %f34 + ldd [%o0 + 0x48], %f36 + ldd [%o0 + 0x50], %f38 + ldd [%o0 + 0x58], %f40 + ldd [%o0 + 0x60], %f42 + ldd [%o0 + 0x68], %f44 + ldd [%o0 + 0x70], %f46 + ldd [%o0 + 0x78], %f48 + ldd [%o0 + 0x80], %f50 + + faligndata %f18, %f20, %f16 + faligndata %f20, %f22, %f18 + faligndata %f22, %f24, %f20 + faligndata %f24, %f26, %f22 + faligndata %f26, %f28, %f24 + faligndata %f28, %f30, %f26 + faligndata %f30, %f32, %f28 + faligndata %f32, %f34, %f30 + faligndata %f34, %f36, %f32 + faligndata %f36, %f38, %f34 + faligndata %f38, %f40, %f36 + faligndata %f40, %f42, %f38 + faligndata %f42, %f44, %f40 + faligndata %f44, %f46, %f42 + faligndata %f46, %f48, %f44 + faligndata %f48, %f50, %f46 + + SHA512 + + subcc %o1, 0x80, %o1 + fsrc2 %f50, %f18 + bne,pt %xcc, 1b + add %o0, 0x80, %o0 + + ba,a,pt %xcc, 5b +END(__sha512_process_block_crop) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/sub_n-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/sub_n-vis3.S new file mode 100644 index 0000000000..2d2a75dff8 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/sub_n-vis3.S @@ -0,0 +1,71 @@ +! SPARC v9 64-bit VIS3 __mpn_sub_n -- Subtract two limb vectors of the same length > 0 +! and store difference in a third limb vector. +! +! Copyright (C) 2013-2017 Free Software Foundation, Inc. +! This file is part of the GNU C Library. +! Contributed by David S. Miller <davem@davemloft.net> +! +! The GNU C Library is free software; you can redistribute it and/or +! modify it under the terms of the GNU Lesser General Public +! License as published by the Free Software Foundation; either +! version 2.1 of the License, or (at your option) any later version. +! +! The GNU C Library is distributed in the hope that it will be useful, +! but WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! Lesser General Public License for more details. +! +! You should have received a copy of the GNU Lesser General Public +! License along with the GNU C Library; if not, see +! <http://www.gnu.org/licenses/>. + +#include <sysdep.h> + +#define res_ptr %o0 +#define s1_ptr %o1 +#define s2_ptr %o2 +#define sz %o3 +#define tmp1 %g1 +#define tmp2 %g2 +#define tmp3 %g3 +#define tmp4 %o4 + + .register %g2,#scratch + .register %g3,#scratch +ENTRY(__mpn_sub_n_vis3) + subcc sz, 1, sz + be .Lfinal_limb + cmp %g0, 1 + +.Lloop: + ldx [s2_ptr + 0x00], tmp1 + add s2_ptr, 0x10, s2_ptr + ldx [s1_ptr + 0x00], tmp2 + add s1_ptr, 0x10, s1_ptr + ldx [s2_ptr - 0x08], tmp3 + add res_ptr, 0x10, res_ptr + ldx [s1_ptr - 0x08], tmp4 + sub sz, 2, sz + xnor tmp1, %g0, tmp1 + addxccc tmp1, tmp2, tmp1 + stx tmp1, [res_ptr - 0x10] + xnor tmp3, %g0, tmp3 + addxccc tmp3, tmp4, tmp3 + brgz sz, .Lloop + stx tmp3, [res_ptr - 0x08] + + brlz,pt sz, .Lfinish + nop + +.Lfinal_limb: + ldx [s2_ptr + 0x00], tmp1 + ldx [s1_ptr + 0x00], tmp2 + xnor tmp1, %g0, tmp1 + addxccc tmp1, tmp2, tmp1 + stx tmp1, [res_ptr + 0x00] + +.Lfinish: + clr %o0 + retl + movcc %xcc, 1, %o0 +END(__mpn_sub_n_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/sub_n.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/sub_n.S new file mode 100644 index 0000000000..d20a286df1 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/sub_n.S @@ -0,0 +1,56 @@ +/* Multiple versions of sub_n + + Copyright (C) 2013-2017 Free Software Foundation, Inc. + Contributed by David S. Miller (davem@davemloft.net) + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__mpn_sub_n) + .type __mpn_sub_n, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 1f + nop +# ifdef SHARED + sethi %gdop_hix22(__mpn_sub_n_vis3), %o1 + xor %o1, %gdop_lox10(__mpn_sub_n_vis3), %o1 +# else + set __mpn_sub_n_vis3, %o1 +# endif + ba 10f + nop +1: +# ifdef SHARED + sethi %gdop_hix22(__mpn_sub_n_generic), %o1 + xor %o1, %gdop_lox10(__mpn_sub_n_generic), %o1 +# else + set __mpn_sub_n_generic, %o1 +# endif +10: +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__mpn_sub_n) + +#define __mpn_sub_n __mpn_sub_n_generic +#include "../sub_n.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/submul_1-vis3.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/submul_1-vis3.S new file mode 100644 index 0000000000..99644491e7 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/submul_1-vis3.S @@ -0,0 +1,87 @@ +! SPARC v9 64-bit VIS3 __mpn_submul_1 -- Multiply a limb vector with a +! limb and subtract the result from a second limb vector. +! +! Copyright (C) 2013-2017 Free Software Foundation, Inc. +! This file is part of the GNU C Library. +! Contributed by David S. Miller <davem@davemloft.net> +! +! The GNU C Library is free software; you can redistribute it and/or +! modify it under the terms of the GNU Lesser General Public +! License as published by the Free Software Foundation; either +! version 2.1 of the License, or (at your option) any later version. +! +! The GNU C Library is distributed in the hope that it will be useful, +! but WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! Lesser General Public License for more details. +! +! You should have received a copy of the GNU Lesser General Public +! License along with the GNU C Library; if not, see +! <http://www.gnu.org/licenses/>. + +#include <sysdep.h> + +#define res_ptr %i0 +#define s1_ptr %i1 +#define sz %i2 +#define s2_limb %i3 +#define carry %o5 +#define tmp1 %g1 +#define tmp2 %g2 +#define tmp3 %g3 +#define tmp4 %o4 +#define tmp5 %l0 +#define tmp6 %l1 +#define tmp7 %l2 +#define tmp8 %l3 + + .register %g2,#scratch + .register %g3,#scratch +ENTRY(__mpn_submul_1_vis3) + save %sp, -176, %sp + subcc sz, 1, sz + be .Lfinal_limb + clr carry + +.Lloop: + ldx [s1_ptr + 0x00], tmp1 + ldx [res_ptr + 0x00], tmp3 + ldx [s1_ptr + 0x08], tmp2 + ldx [res_ptr + 0x08], tmp4 + mulx tmp1, s2_limb, tmp5 + add s1_ptr, 0x10, s1_ptr + umulxhi tmp1, s2_limb, tmp6 + add res_ptr, 0x10, res_ptr + mulx tmp2, s2_limb, tmp7 + sub sz, 2, sz + umulxhi tmp2, s2_limb, tmp8 + addcc carry, tmp5, tmp5 + addxc %g0, tmp6, carry + subcc tmp3, tmp5, tmp5 + addxc %g0, carry, carry + stx tmp5, [res_ptr - 0x10] + addcc carry, tmp7, tmp7 + addxc %g0, tmp8, carry + subcc tmp4, tmp7, tmp7 + addxc %g0, carry, carry + brgz sz, .Lloop + stx tmp7, [res_ptr - 0x08] + + brlz,pt sz, .Lfinish + nop + +.Lfinal_limb: + ldx [s1_ptr + 0x00], tmp1 + ldx [res_ptr + 0x00], tmp3 + mulx tmp1, s2_limb, tmp5 + umulxhi tmp1, s2_limb, tmp6 + addcc carry, tmp5, tmp5 + addxc %g0, tmp6, carry + subcc tmp3, tmp5, tmp5 + addxc %g0, carry, carry + stx tmp5, [res_ptr + 0x00] + +.Lfinish: + jmpl %i7 + 8, %g0 + restore carry, 0, %o0 +END(__mpn_submul_1_vis3) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/multiarch/submul_1.S b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/submul_1.S new file mode 100644 index 0000000000..3c297d989b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/multiarch/submul_1.S @@ -0,0 +1,56 @@ +/* Multiple versions of submul_1 + + Copyright (C) 2013-2017 Free Software Foundation, Inc. + Contributed by David S. Miller (davem@davemloft.net) + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__mpn_submul_1) + .type __mpn_submul_1, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 1f + nop +# ifdef SHARED + sethi %gdop_hix22(__mpn_submul_1_vis3), %o1 + xor %o1, %gdop_lox10(__mpn_submul_1_vis3), %o1 +# else + set __mpn_submul_1_vis3, %o1 +# endif + ba 10f + nop +1: +# ifdef SHARED + sethi %gdop_hix22(__mpn_submul_1_generic), %o1 + xor %o1, %gdop_lox10(__mpn_submul_1_generic), %o1 +# else + set __mpn_submul_1_generic, %o1 +# endif +10: +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__mpn_submul_1) + +#define __mpn_submul_1 __mpn_submul_1_generic +#include "../submul_1.S" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/pthread_spin_init.c b/REORG.TODO/sysdeps/sparc/sparc64/pthread_spin_init.c new file mode 100644 index 0000000000..58319ab62d --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/pthread_spin_init.c @@ -0,0 +1 @@ +/* pthread_spin_init is in pthread_spin_unlock.S */ diff --git a/REORG.TODO/sysdeps/sparc/sparc64/pthread_spin_lock.S b/REORG.TODO/sysdeps/sparc/sparc64/pthread_spin_lock.S new file mode 100644 index 0000000000..0f41ccf4d5 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/pthread_spin_lock.S @@ -0,0 +1,31 @@ +/* Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .text +ENTRY(pthread_spin_lock) +1: ldstub [%o0], %g1 + brnz,pn %g1, 2f + membar #StoreLoad | #StoreStore + retl + mov 0, %o0 +2: ldub [%o0], %g1 + brnz,pt %g1, 2b + membar #LoadLoad + ba,a,pt %xcc, 1b +END(pthread_spin_lock) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/pthread_spin_trylock.S b/REORG.TODO/sysdeps/sparc/sparc64/pthread_spin_trylock.S new file mode 100644 index 0000000000..fa05cf8fdb --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/pthread_spin_trylock.S @@ -0,0 +1,27 @@ +/* Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <pthread-errnos.h> + + .text +ENTRY(pthread_spin_trylock) + ldstub [%o0], %o0 + membar #StoreLoad | #StoreStore + retl + movrnz %o0, EBUSY, %o0 +END(pthread_spin_trylock) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/pthread_spin_unlock.S b/REORG.TODO/sysdeps/sparc/sparc64/pthread_spin_unlock.S new file mode 100644 index 0000000000..c82f05d538 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/pthread_spin_unlock.S @@ -0,0 +1,28 @@ +/* Copyright (C) 2012-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .text +ENTRY(pthread_spin_unlock) + membar #StoreStore | #LoadStore + stb %g0, [%o0] + retl + clr %o0 +END(pthread_spin_unlock) + +strong_alias (pthread_spin_unlock, pthread_spin_init) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/pthreaddef.h b/REORG.TODO/sysdeps/sparc/sparc64/pthreaddef.h new file mode 100644 index 0000000000..df81791a65 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/pthreaddef.h @@ -0,0 +1,33 @@ +/* Copyright (C) 2003-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +/* Default stack size. */ +#define ARCH_STACK_DEFAULT_SIZE (4 * 1024 * 1024) + +/* Required stack pointer alignment at beginning. */ +#define STACK_ALIGN 16 + +/* Minimal stack size after allocating thread descriptor and guard size. */ +#define MINIMAL_REST_STACK 4096 + +/* Alignment requirement for TCB. */ +#define TCB_ALIGNMENT 16 + + +/* Location of current stack frame. */ +#define CURRENT_STACK_FRAME (stack_pointer + (2 * 128)) +register char *stack_pointer __asm__("%sp"); diff --git a/REORG.TODO/sysdeps/sparc/sparc64/rawmemchr.S b/REORG.TODO/sysdeps/sparc/sparc64/rawmemchr.S new file mode 100644 index 0000000000..d3e7b5d4b4 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/rawmemchr.S @@ -0,0 +1,178 @@ +/* rawmemchr (str, ch) -- Return pointer to first occurrence of CH in STR. + For SPARC v9. + Copyright (C) 1999-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jj@ultra.linux.cz>. + This version is developed using the same algorithm as the fast C + version which carries the following introduction: + Based on strlen implementation by Torbjorn Granlund (tege@sics.se), + with help from Dan Sahlin (dan@sics.se) and + commentary by Jim Blandy (jimb@ai.mit.edu); + adaptation to memchr suggested by Dick Karpinski (dick@cca.ucsf.edu), + and implemented by Roland McGrath (roland@ai.mit.edu). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <asm/asi.h> +#ifndef XCC +#define XCC xcc +#define USE_BPR + .register %g2, #scratch + .register %g3, #scratch +#endif + + /* Normally, this uses + ((xword - 0x0101010101010101) & 0x8080808080808080) test + to find out if any byte in xword could be zero. This is fast, but + also gives false alarm for any byte in range 0x81-0xff. It does + not matter for correctness, as if this test tells us there could + be some zero byte, we check it byte by byte, but if bytes with + high bits set are common in the strings, then this will give poor + performance. You can #define EIGHTBIT_NOT_RARE and the algorithm + will use one tick slower, but more precise test + ((xword - 0x0101010101010101) & (~xword) & 0x8080808080808080), + which does not give any false alarms (but if some bits are set, + one cannot assume from it which bytes are zero and which are not). + It is yet to be measured, what is the correct default for glibc + in these days for an average user. + */ + + .text + .align 32 +ENTRY(__rawmemchr) + and %o1, 0xff, %o1 /* IEU0 Group */ + sethi %hi(0x01010101), %g1 /* IEU1 */ + ldub [%o0], %o3 /* Load */ + sll %o1, 8, %o4 /* IEU0 Group */ + + or %g1, %lo(0x01010101), %g1 /* IEU1 */ + sllx %g1, 32, %g2 /* IEU0 Group */ + or %o4, %o1, %o4 /* IEU1 */ + andcc %o0, 7, %g0 /* IEU1 Group */ + + sll %o4, 16, %g5 /* IEU0 */ + or %o4, %g5, %o4 /* IEU0 Group */ + or %g1, %g2, %g1 /* IEU1 */ + bne,pn %icc, 32f /* CTI */ + + sllx %o4, 32, %g5 /* IEU0 Group */ + cmp %o3, %o1 /* IEU1 */ + be,pn %icc, 30f /* CTI */ + sllx %g1, 7, %g2 /* IEU0 Group */ + +18: ldx [%o0], %o3 /* Load */ + or %o4, %g5, %o4 /* IEU1 */ + add %o0, 8, %o0 /* IEU0 Group */ +19: xor %o3, %o4, %o3 /* IEU0 Group */ + + sub %o3, %g1, %o2 /* IEU0 Group */ +#ifdef EIGHTBIT_NOT_RARE + andn %o2, %o3, %o5 /* IEU0 Group */ + ldxa [%o0] ASI_PNF, %o3 /* Load */ + andcc %o5, %g2, %g0 /* IEU1 Group */ +#else + ldxa [%o0] ASI_PNF, %o3 /* Load */ + andcc %o2, %g2, %g0 /* IEU1 Group */ +#endif + be,pt %xcc, 19b /* CTI */ + + add %o0, 8, %o0 /* IEU0 */ + addcc %o2, %g1, %g3 /* IEU1 Group */ + srlx %o2, 32, %o2 /* IEU0 */ +20: andcc %o2, %g2, %g0 /* IEU1 Group */ + + be,pn %xcc, 21f /* CTI */ + srlx %g3, 56, %o2 /* IEU0 */ + andcc %o2, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 29f /* CTI */ + + srlx %g3, 48, %o2 /* IEU0 */ + andcc %o2, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 28f /* CTI */ + srlx %g3, 40, %o2 /* IEU0 */ + + andcc %o2, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 27f /* CTI */ + srlx %g3, 32, %o2 /* IEU0 */ + andcc %o2, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 26f /* CTI */ +21: srlx %g3, 24, %o2 /* IEU0 */ + andcc %o2, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 25f /* CTI */ + + srlx %g3, 16, %o2 /* IEU0 */ + andcc %o2, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 24f /* CTI */ + srlx %g3, 8, %o2 /* IEU0 */ + + andcc %o2, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 23f /* CTI */ + xor %o3, %o4, %o3 /* IEU0 */ + andcc %g3, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 22f /* CTI */ + sub %o3, %g1, %o2 /* IEU0 */ + ldxa [%o0] ASI_PNF, %o3 /* Load */ + andcc %o2, %g2, %g0 /* IEU1 Group */ + + be,pt %xcc, 19b /* CTI */ + add %o0, 8, %o0 /* IEU0 */ + addcc %o2, %g1, %g3 /* IEU1 Group */ + ba,pt %xcc, 20b /* CTI */ + + srlx %o2, 32, %o2 /* IEU0 */ + + .align 16 +22: retl /* CTI+IEU1 Group */ + add %o0, -9, %o0 /* IEU0 */ +23: retl /* CTI+IEU1 Group */ + add %o0, -10, %o0 /* IEU0 */ + +24: retl /* CTI+IEU1 Group */ + add %o0, -11, %o0 /* IEU0 */ +25: retl /* CTI+IEU1 Group */ + add %o0, -12, %o0 /* IEU0 */ + +26: retl /* CTI+IEU1 Group */ + add %o0, -13, %o0 /* IEU0 */ +27: retl /* CTI+IEU1 Group */ + add %o0, -14, %o0 /* IEU0 */ + +28: retl /* CTI+IEU1 Group */ + add %o0, -15, %o0 /* IEU0 */ +29: retl /* CTI+IEU1 Group */ + add %o0, -16, %o0 /* IEU0 */ + +30: retl /* CTI+IEU1 Group */ + nop /* IEU0 */ + + .align 16 +32: andcc %o0, 7, %g0 /* IEU1 Group */ + be,a,pn %icc, 18b /* CTI */ + sllx %g1, 7, %g2 /* IEU0 */ + add %o0, 1, %o0 /* IEU0 Group */ + + cmp %o3, %o1 /* IEU1 */ + bne,a,pt %icc, 32b /* CTI */ + lduba [%o0] ASI_PNF, %o3 /* Load */ + retl /* CTI+IEU1 Group */ + + add %o0, -1, %o0 /* IEU0 */ +END(__rawmemchr) + +libc_hidden_def (__rawmemchr) +weak_alias (__rawmemchr, rawmemchr) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/rshift.S b/REORG.TODO/sysdeps/sparc/sparc64/rshift.S new file mode 100644 index 0000000000..f9319f2ec7 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/rshift.S @@ -0,0 +1,92 @@ +/* SPARC v9 __mpn_rshift -- + + Copyright (C) 1996-2017 Free Software Foundation, Inc. + + This file is part of the GNU MP Library. + + The GNU MP Library is free software; you can redistribute it and/or modify + it under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation; either version 2.1 of the License, or (at your + option) any later version. + + The GNU MP Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with the GNU MP Library; see the file COPYING.LIB. If not, + see <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +/* INPUT PARAMETERS + res_ptr %o0 + src_ptr %o1 + size %o2 + cnt %o3 */ + + .register %g2, #scratch + .register %g3, #scratch + +ENTRY(__mpn_rshift) + ldx [%o1],%g2 ! load first limb + sub %g0,%o3,%o5 ! negate shift count + add %o2,-1,%o2 + andcc %o2,4-1,%g4 ! number of limbs in first loop + sllx %g2,%o5,%g1 ! compute function result + be,pn %xcc,.L0 ! if multiple of 4 limbs, skip first loop + mov %g1,%g5 + + sub %o2,%g4,%o2 ! adjust count for main loop + +.Loop0: ldx [%o1+8],%g3 + add %o0,8,%o0 + add %o1,8,%o1 + srlx %g2,%o3,%o4 + addcc %g4,-1,%g4 + sllx %g3,%o5,%g1 + mov %g3,%g2 + or %o4,%g1,%o4 + bne,pt %xcc,.Loop0 + stx %o4,[%o0-8] + +.L0: brz,pn %o2,.Lend + nop + +.Loop: ldx [%o1+8],%g3 + add %o0,32,%o0 + srlx %g2,%o3,%o4 + addcc %o2,-4,%o2 + sllx %g3,%o5,%g1 + + ldx [%o1+16],%g2 + srlx %g3,%o3,%g4 + or %o4,%g1,%o4 + stx %o4,[%o0-32] + sllx %g2,%o5,%g1 + + ldx [%o1+24],%g3 + srlx %g2,%o3,%o4 + or %g4,%g1,%g4 + stx %g4,[%o0-24] + sllx %g3,%o5,%g1 + + ldx [%o1+32],%g2 + srlx %g3,%o3,%g4 + or %o4,%g1,%o4 + stx %o4,[%o0-16] + sllx %g2,%o5,%g1 + + add %o1,32,%o1 + or %g4,%g1,%g4 + bne,pt %xcc,.Loop + stx %g4,[%o0-8] + +.Lend: srlx %g2,%o3,%g2 + stx %g2,[%o0-0] + + jmpl %o7+8,%g0 + mov %g5,%o0 + +END(__mpn_rshift) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/rtld-memcpy.c b/REORG.TODO/sysdeps/sparc/sparc64/rtld-memcpy.c new file mode 100644 index 0000000000..52f8302f08 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/rtld-memcpy.c @@ -0,0 +1,3 @@ +#define NO_MEMPCPY_STPCPY_REDIRECT +#include <string/memcpy.c> +#include <string/mempcpy.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc64/rtld-memset.c b/REORG.TODO/sysdeps/sparc/sparc64/rtld-memset.c new file mode 100644 index 0000000000..55f3835790 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/rtld-memset.c @@ -0,0 +1 @@ +#include <string/memset.c> diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/Makefile b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/Makefile new file mode 100644 index 0000000000..b145df283b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/Makefile @@ -0,0 +1,33 @@ +# Software floating-point emulation. +# Makefile for SPARC v9 ABI mandated long double utility +# functions (_Qp_*). +# Copyright (C) 1999-2017 Free Software Foundation, Inc. +# This file is part of the GNU C Library. +# Contributed by Jakub Jelinek (jj@ultra.linux.cz). +# + +# The GNU C Library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. + +# The GNU C Library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. + +# You should have received a copy of the GNU Lesser General Public +# License along with the GNU C Library; if not, see +# <http://www.gnu.org/licenses/>. + +ifeq ($(subdir),soft-fp) +sparc64-quad-routines := qp_add qp_cmp qp_cmpe qp_div qp_dtoq qp_feq qp_fge \ + qp_fgt qp_fle qp_flt qp_fne qp_itoq qp_mul qp_neg qp_qtod qp_qtoi \ + qp_qtos qp_qtoui qp_qtoux qp_qtox qp_sqrt qp_stoq qp_sub qp_uitoq \ + qp_uxtoq qp_xtoq qp_util +sysdep_routines += $(sparc64-quad-routines) +endif + +ifeq ($(subdir),math) +CPPFLAGS += -I../soft-fp/ +endif diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/Versions b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/Versions new file mode 100644 index 0000000000..9e89c3c3ef --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/Versions @@ -0,0 +1,8 @@ +libc { + GLIBC_2.2 { + _Qp_add; _Qp_cmp; _Qp_cmpe; _Qp_div; _Qp_dtoq; _Qp_feq; _Qp_fge; _Qp_fgt; + _Qp_fle; _Qp_flt; _Qp_fne; _Qp_itoq; _Qp_mul; _Qp_neg; _Qp_qtod; _Qp_qtoi; + _Qp_qtos; _Qp_qtoui; _Qp_qtoux; _Qp_qtox; _Qp_sqrt; _Qp_stoq; _Qp_sub; + _Qp_uitoq; _Qp_uxtoq; _Qp_xtoq; + } +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/e_ilogbl.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/e_ilogbl.c new file mode 100644 index 0000000000..5b19d12a4e --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/e_ilogbl.c @@ -0,0 +1,79 @@ +/* Software floating-point emulation. + ilogbl(x, exp) + Copyright (C) 1999-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +/* ilogbl(long double x) + * return the binary exponent of non-zero x + * ilogbl(0) = 0x80000001 + * ilogbl(inf/NaN) = 0x7fffffff (no signal is raised) + */ + +#include "soft-fp.h" +#include "quad.h" +#include <math.h> + +int __ieee754_ilogbl (long double x) +{ + FP_DECL_EX; + FP_DECL_Q(X); + +/* + FP_UNPACK_Q(X, x); + switch (X_c) + { + case FP_CLS_ZERO: + return FP_ILOGB0; + case FP_CLS_NAN: + case FP_CLS_INF: + return FP_ILOGBNAN; + default: + return X_e; + } + */ + FP_UNPACK_RAW_Q(X, x); + switch (X_e) + { + default: + return X_e - _FP_EXPBIAS_Q; + case 0: +#if (2 * _FP_W_TYPE_SIZE) < _FP_FRACBITS_Q + if (_FP_FRAC_ZEROP_4(X)) + return FP_ILOGB0; + else + { + _FP_I_TYPE shift; + _FP_FRAC_CLZ_4(shift, X); + shift -= _FP_FRACXBITS_Q; + return X_e - _FP_EXPBIAS_Q - 1 + shift; + } +#else + if (_FP_FRAC_ZEROP_2(X)) + return FP_ILOGB0; + else + { + _FP_I_TYPE shift; + _FP_FRAC_CLZ_2(shift, X); + shift -= _FP_FRACXBITS_Q; + return X_e - _FP_EXPBIAS_Q - 1 + shift; + } +#endif + case _FP_EXPBIAS_Q: + return FP_ILOGBNAN; + } +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_add.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_add.c new file mode 100644 index 0000000000..a67deab315 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_add.c @@ -0,0 +1,44 @@ +/* Software floating-point emulation. + (*c) = (*a) + (*b) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +void _Qp_add(long double *c, const long double *a, const long double *b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); FP_DECL_Q(C); + + FP_INIT_ROUNDMODE; + FP_UNPACK_SEMIRAW_QP(A, a); + FP_UNPACK_SEMIRAW_QP(B, b); + FP_ADD_Q(C, A, B); + FP_PACK_SEMIRAW_QP(c, C); + QP_HANDLE_EXCEPTIONS(__asm ( +" ldd [%1], %%f52\n" +" ldd [%1+8], %%f54\n" +" ldd [%2], %%f56\n" +" ldd [%2+8], %%f58\n" +" faddq %%f52, %%f56, %%f60\n" +" std %%f60, [%0]\n" +" std %%f62, [%0+8]\n" +" " : : "r" (c), "r" (a), "r" (b) : QP_CLOBBER)); +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_cmp.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_cmp.c new file mode 100644 index 0000000000..5316157ec7 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_cmp.c @@ -0,0 +1,48 @@ +/* Software floating-point emulation. + Compare (*a) and (*b), return float condition code. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +int _Qp_cmp(const long double *a, const long double *b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); + int r; + + FP_INIT_ROUNDMODE; + FP_UNPACK_RAW_QP(A, a); + FP_UNPACK_RAW_QP(B, b); + FP_CMP_Q(r, B, A, 3, 1); + if (r == -1) r = 2; + QP_HANDLE_EXCEPTIONS( + __asm ( +" ldd [%0], %%f52\n" +" ldd [%0+8], %%f54\n" +" ldd [%1], %%f56\n" +" ldd [%1+8], %%f58\n" +" fcmpq %%fcc3, %%f52, %%f56\n" +" " : : "r" (a), "r" (b) : QP_CLOBBER_CC); + _FPU_GETCW(_fcw); + r = ((_fcw >> 36) & 3)); + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_cmpe.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_cmpe.c new file mode 100644 index 0000000000..e0a834c721 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_cmpe.c @@ -0,0 +1,49 @@ +/* Software floating-point emulation. + Compare (*a) and (*b), return float condition code. + Signal exception (unless masked) if unordered. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +int _Qp_cmpe(const long double *a, const long double *b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); + int r; + + FP_INIT_ROUNDMODE; + FP_UNPACK_RAW_QP(A, a); + FP_UNPACK_RAW_QP(B, b); + FP_CMP_Q(r, B, A, 3, 2); + if (r == -1) r = 2; + QP_HANDLE_EXCEPTIONS( + __asm ( +" ldd [%0], %%f52\n" +" ldd [%0+8], %%f54\n" +" ldd [%1], %%f56\n" +" ldd [%1+8], %%f58\n" +" fcmpeq %%fcc3, %%f52, %%f56\n" +" " : : "r" (a), "r" (b) : QP_CLOBBER_CC); + _FPU_GETCW(_fcw); + r = ((_fcw >> 36) & 3)); + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_div.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_div.c new file mode 100644 index 0000000000..27d08f94dc --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_div.c @@ -0,0 +1,44 @@ +/* Software floating-point emulation. + (*c) = (*a) / (*b) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +void _Qp_div(long double *c, const long double *a, const long double *b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); FP_DECL_Q(C); + + FP_INIT_ROUNDMODE; + FP_UNPACK_QP(A, a); + FP_UNPACK_QP(B, b); + FP_DIV_Q(C, A, B); + FP_PACK_QP(c, C); + QP_HANDLE_EXCEPTIONS(__asm ( +" ldd [%1], %%f52\n" +" ldd [%1+8], %%f54\n" +" ldd [%2], %%f56\n" +" ldd [%2+8], %%f58\n" +" fdivq %%f52, %%f56, %%f60\n" +" std %%f60, [%0]\n" +" std %%f62, [%0+8]\n" +" " : : "r" (c), "r" (a), "r" (b) : QP_CLOBBER)); +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_dtoq.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_dtoq.c new file mode 100644 index 0000000000..5a5c43b13c --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_dtoq.c @@ -0,0 +1,45 @@ +/* Software floating-point emulation. + (*c) = (long double)(a) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "double.h" +#include "quad.h" + +void _Qp_dtoq(long double *c, const double a) +{ + FP_DECL_EX; + FP_DECL_D(A); + FP_DECL_Q(C); + + FP_INIT_ROUNDMODE; + FP_UNPACK_RAW_D(A, a); +#if (2 * _FP_W_TYPE_SIZE) < _FP_FRACBITS_Q + FP_EXTEND(Q,D,4,2,C,A); +#else + FP_EXTEND(Q,D,2,1,C,A); +#endif + FP_PACK_RAW_QP(c, C); + QP_HANDLE_EXCEPTIONS(__asm ( +" fdtoq %1, %%f60\n" +" std %%f60, [%0]\n" +" std %%f62, [%0+8]\n" +" " : : "r" (c), "e" (a) : QP_CLOBBER)); +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_feq.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_feq.c new file mode 100644 index 0000000000..c7c6263782 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_feq.c @@ -0,0 +1,48 @@ +/* Software floating-point emulation. + Return 1 if (*a) == (*b) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +int _Qp_feq(const long double *a, const long double *b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); + int r; + + FP_INIT_ROUNDMODE; + FP_UNPACK_RAW_QP(A, a); + FP_UNPACK_RAW_QP(B, b); + FP_CMP_EQ_Q(r, A, B, 1); + + QP_HANDLE_EXCEPTIONS( + __asm ( +" ldd [%0], %%f52\n" +" ldd [%0+8], %%f54\n" +" ldd [%1], %%f56\n" +" ldd [%1+8], %%f58\n" +" fcmpq %%fcc3, %%f52, %%f56\n" +" " : : "r" (a), "r" (b) : QP_CLOBBER_CC); + _FPU_GETCW(_fcw); + r = ((_fcw >> 36) & 3)); + + return !r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_fge.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_fge.c new file mode 100644 index 0000000000..19cacbb342 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_fge.c @@ -0,0 +1,48 @@ +/* Software floating-point emulation. + Return 1 if (*a) >= (*b) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +int _Qp_fge(const long double *a, const long double *b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); + int r; + + FP_INIT_ROUNDMODE; + FP_UNPACK_RAW_QP(A, a); + FP_UNPACK_RAW_QP(B, b); + FP_CMP_Q(r, B, A, 3, 2); + + QP_HANDLE_EXCEPTIONS( + __asm ( +" ldd [%0], %%f52\n" +" ldd [%0+8], %%f54\n" +" ldd [%1], %%f56\n" +" ldd [%1+8], %%f58\n" +" fcmpeq %%fcc3, %%f52, %%f56\n" +" " : : "r" (a), "r" (b) : QP_CLOBBER_CC); + _FPU_GETCW(_fcw); + r = ((_fcw >> 36) & 1)); + + return (r <= 0); +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_fgt.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_fgt.c new file mode 100644 index 0000000000..70645d1cba --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_fgt.c @@ -0,0 +1,48 @@ +/* Software floating-point emulation. + Return 1 if (*a) > (*b) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +int _Qp_fgt(const long double *a, const long double *b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); + int r; + + FP_INIT_ROUNDMODE; + FP_UNPACK_RAW_QP(A, a); + FP_UNPACK_RAW_QP(B, b); + FP_CMP_Q(r, B, A, 3, 2); + + QP_HANDLE_EXCEPTIONS( + __asm ( +" ldd [%0], %%f52\n" +" ldd [%0+8], %%f54\n" +" ldd [%1], %%f56\n" +" ldd [%1+8], %%f58\n" +" fcmpeq %%fcc3, %%f52, %%f56\n" +" " : : "r" (a), "r" (b) : QP_CLOBBER_CC); + _FPU_GETCW(_fcw); + r = ((_fcw >> 36) & 3) - 3); + + return (r == -1); +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_fle.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_fle.c new file mode 100644 index 0000000000..6293fcbcda --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_fle.c @@ -0,0 +1,48 @@ +/* Software floating-point emulation. + Return 1 if (*a) <= (*b) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +int _Qp_fle(const long double *a, const long double *b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); + int r; + + FP_INIT_ROUNDMODE; + FP_UNPACK_RAW_QP(A, a); + FP_UNPACK_RAW_QP(B, b); + FP_CMP_Q(r, B, A, -2, 2); + + QP_HANDLE_EXCEPTIONS( + __asm ( +" ldd [%0], %%f52\n" +" ldd [%0+8], %%f54\n" +" ldd [%1], %%f56\n" +" ldd [%1+8], %%f58\n" +" fcmpeq %%fcc3, %%f52, %%f56\n" +" " : : "r" (a), "r" (b) : QP_CLOBBER_CC); + _FPU_GETCW(_fcw); + r = ((_fcw >> 36) & 2) ? -1 : 0); + + return (r >= 0); +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_flt.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_flt.c new file mode 100644 index 0000000000..7aa054697a --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_flt.c @@ -0,0 +1,48 @@ +/* Software floating-point emulation. + Return 1 if (*a) < (*b) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +int _Qp_flt(const long double *a, const long double *b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); + int r; + + FP_INIT_ROUNDMODE; + FP_UNPACK_RAW_QP(A, a); + FP_UNPACK_RAW_QP(B, b); + FP_CMP_Q(r, B, A, 3, 2); + + QP_HANDLE_EXCEPTIONS( + __asm ( +" ldd [%0], %%f52\n" +" ldd [%0+8], %%f54\n" +" ldd [%1], %%f56\n" +" ldd [%1+8], %%f58\n" +" fcmpeq %%fcc3, %%f52, %%f56\n" +" " : : "r" (a), "r" (b) : QP_CLOBBER_CC); + _FPU_GETCW(_fcw); + r = ((_fcw >> 36) & 3)); + + return (r == 1); +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_fne.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_fne.c new file mode 100644 index 0000000000..dd358eda0a --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_fne.c @@ -0,0 +1,49 @@ +/* Software floating-point emulation. + Return 1 if (*a) != (*b) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +int _Qp_fne(const long double *a, const long double *b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); + int r; + + FP_INIT_ROUNDMODE; + FP_UNPACK_RAW_QP(A, a); + FP_UNPACK_RAW_QP(B, b); + FP_CMP_EQ_Q(r, A, B, 1); + + QP_HANDLE_EXCEPTIONS( + __asm ( +" ldd [%0], %%f52\n" +" ldd [%0+8], %%f54\n" +" ldd [%1], %%f56\n" +" ldd [%1+8], %%f58\n" +" fcmpq %%fcc3, %%f52, %%f56\n" +" " : : "r" (a), "r" (b) : QP_CLOBBER_CC); + _FPU_GETCW(_fcw); + r = ((_fcw >> 36) & 3) != 0); + + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_itoq.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_itoq.c new file mode 100644 index 0000000000..230fde365f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_itoq.c @@ -0,0 +1,34 @@ +/* Software floating-point emulation. + (*c) = (long double)(a) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +void _Qp_itoq(long double *c, const int a) +{ + FP_DECL_EX; + FP_DECL_Q(C); + int b = a; + + FP_FROM_INT_Q(C, b, 32, unsigned int); + FP_PACK_RAW_QP(c, C); + QP_NO_EXCEPTIONS; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_mul.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_mul.c new file mode 100644 index 0000000000..49a290af93 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_mul.c @@ -0,0 +1,49 @@ +/* Software floating-point emulation. + (*c) = (*a) * (*b) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +/* As QP_HANDLE_EXCEPTIONS reloads FPU control word anyway, + avoid doing it twice. */ +#define _FP_MUL_MEAT_RESET_FE do {} while (0) +#include "soft-fp.h" +#include "quad.h" + +void _Qp_mul(long double *c, const long double *a, const long double *b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); FP_DECL_Q(C); + + FP_INIT_ROUNDMODE; + FP_UNPACK_QP(A, a); + FP_UNPACK_QP(B, b); + FP_MUL_Q(C, A, B); + FP_PACK_QP(c, C); + QP_HANDLE_EXCEPTIONS( + _FPU_SETCW(_fcw); + __asm ( +" ldd [%1], %%f52\n" +" ldd [%1+8], %%f54\n" +" ldd [%2], %%f56\n" +" ldd [%2+8], %%f58\n" +" fmulq %%f52, %%f56, %%f60\n" +" std %%f60, [%0]\n" +" std %%f62, [%0+8]\n" +" " : : "r" (c), "r" (a), "r" (b) : QP_CLOBBER)); +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_neg.S b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_neg.S new file mode 100644 index 0000000000..d2fd7f286f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_neg.S @@ -0,0 +1,30 @@ +/* Quad floating-point emulation. + (*c) = !(*a) + Copyright (C) 1999-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(_Qp_neg) + ldd [%o1], %f60 + ldd [%o1 + 8], %f62 + fnegd %f60, %f60 + std %f60, [%o0] + jmpl %o7 + 8, %g0 + std %f62, [%o0 + 8] +END(_Qp_neg) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_qtod.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_qtod.c new file mode 100644 index 0000000000..7c3889da97 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_qtod.c @@ -0,0 +1,48 @@ +/* Software floating-point emulation. + Return (double)(*a) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "double.h" +#include "quad.h" + +double _Qp_qtod(const long double *a) +{ + FP_DECL_EX; + FP_DECL_Q(A); + FP_DECL_D(R); + double r; + + FP_INIT_ROUNDMODE; + FP_UNPACK_SEMIRAW_QP(A, a); +#if (2 * _FP_W_TYPE_SIZE) < _FP_FRACBITS_Q + FP_TRUNC(D,Q,2,4,R,A); +#else + FP_TRUNC(D,Q,1,2,R,A); +#endif + FP_PACK_SEMIRAW_D(r, R); + QP_HANDLE_EXCEPTIONS(__asm ( +" ldd [%1], %%f52\n" +" ldd [%1+8], %%f54\n" +" fqtod %%f52, %0\n" +" " : "=&e" (r) : "r" (a) : QP_CLOBBER)); + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_qtoi.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_qtoi.c new file mode 100644 index 0000000000..99cd760acd --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_qtoi.c @@ -0,0 +1,46 @@ +/* Software floating-point emulation. + Return (int)(*a) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#define FP_ROUNDMODE FP_RND_ZERO +#include "soft-fp.h" +#include "quad.h" + +int _Qp_qtoi(const long double *a) +{ + FP_DECL_EX; + FP_DECL_Q(A); + unsigned int r; + + FP_INIT_ROUNDMODE; + FP_UNPACK_RAW_QP(A, a); + FP_TO_INT_Q(r, A, 32, 1); + QP_HANDLE_EXCEPTIONS( + int rx; + __asm ( +" ldd [%1], %%f52\n" +" ldd [%1+8], %%f54\n" +" fqtoi %%f52, %%f31\n" +" st %%f31, [%0]\n" +" " : : "r" (&rx), "r" (a) : QP_CLOBBER, "f31"); + r = rx); + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_qtos.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_qtos.c new file mode 100644 index 0000000000..dacd6c0620 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_qtos.c @@ -0,0 +1,49 @@ +/* Software floating-point emulation. + Return (float)(*a) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "single.h" +#include "quad.h" + +float _Qp_qtos(const long double *a) +{ + FP_DECL_EX; + FP_DECL_Q(A); + FP_DECL_S(R); + float r; + + FP_INIT_ROUNDMODE; + FP_UNPACK_SEMIRAW_QP(A, a); +#if (2 * _FP_W_TYPE_SIZE) < _FP_FRACBITS_Q + FP_TRUNC(S,Q,1,4,R,A); +#else + FP_TRUNC(S,Q,1,2,R,A); +#endif + FP_PACK_SEMIRAW_S(r, R); + + QP_HANDLE_EXCEPTIONS(__asm ( +" ldd [%1], %%f52\n" +" ldd [%1+8], %%f54\n" +" fqtos %%f52, %0\n" +" " : "=&f" (r) : "r" (a) : QP_CLOBBER)); + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_qtoui.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_qtoui.c new file mode 100644 index 0000000000..2d8fb52530 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_qtoui.c @@ -0,0 +1,46 @@ +/* Software floating-point emulation. + Return (unsigned int)(*a) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#define FP_ROUNDMODE FP_RND_ZERO +#include "soft-fp.h" +#include "quad.h" + +unsigned int _Qp_qtoui(const long double *a) +{ + FP_DECL_EX; + FP_DECL_Q(A); + unsigned int r; + + FP_INIT_ROUNDMODE; + FP_UNPACK_RAW_QP(A, a); + FP_TO_INT_Q(r, A, 32, -1); + QP_HANDLE_EXCEPTIONS( + int rx; + __asm ( +" ldd [%1], %%f52\n" +" ldd [%1+8], %%f54\n" +" fqtoi %%f52, %%f31\n" +" st %%f31, [%0]\n" +" " : : "r" (&rx), "r" (a) : QP_CLOBBER, "f31"); + r = rx); + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_qtoux.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_qtoux.c new file mode 100644 index 0000000000..2d74a6ee15 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_qtoux.c @@ -0,0 +1,46 @@ +/* Software floating-point emulation. + Return (unsigned long)(*a) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#define FP_ROUNDMODE FP_RND_ZERO +#include "soft-fp.h" +#include "quad.h" + +unsigned long _Qp_qtoux(const long double *a) +{ + FP_DECL_EX; + FP_DECL_Q(A); + unsigned long r; + + FP_INIT_ROUNDMODE; + FP_UNPACK_RAW_QP(A, a); + FP_TO_INT_Q(r, A, 64, -1); + QP_HANDLE_EXCEPTIONS( + unsigned long rx; + __asm ( +" ldd [%1], %%f52\n" +" ldd [%1+8], %%f54\n" +" fqtox %%f52, %%f60\n" +" std %%f60, [%0]\n" +" " : : "r" (&rx), "r" (a) : QP_CLOBBER); + r = rx); + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_qtox.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_qtox.c new file mode 100644 index 0000000000..abfc666cde --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_qtox.c @@ -0,0 +1,46 @@ +/* Software floating-point emulation. + Return (long)(*a) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#define FP_ROUNDMODE FP_RND_ZERO +#include "soft-fp.h" +#include "quad.h" + +long _Qp_qtox(const long double *a) +{ + FP_DECL_EX; + FP_DECL_Q(A); + unsigned long r; + + FP_INIT_ROUNDMODE; + FP_UNPACK_RAW_QP(A, a); + FP_TO_INT_Q(r, A, 64, 1); + QP_HANDLE_EXCEPTIONS( + long rx; + __asm ( +" ldd [%1], %%f52\n" +" ldd [%1+8], %%f54\n" +" fqtox %%f52, %%f60\n" +" std %%f60, [%0]\n" +" " : : "r" (&rx), "r" (a) : QP_CLOBBER); + r = rx); + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_sqrt.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_sqrt.c new file mode 100644 index 0000000000..3d78b1fdbb --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_sqrt.c @@ -0,0 +1,41 @@ +/* Software floating-point emulation. + (*c) = sqrtl(*a) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +void _Qp_sqrt(long double *c, const long double *a) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(C); + + FP_INIT_ROUNDMODE; + FP_UNPACK_QP(A, a); + FP_SQRT_Q(C, A); + FP_PACK_QP(c, C); + QP_HANDLE_EXCEPTIONS(__asm ( +" ldd [%1], %%f52\n" +" ldd [%1+8], %%f54\n" +" fsqrtq %%f52, %%f60\n" +" std %%f60, [%0]\n" +" std %%f62, [%0+8]\n" +" " : : "r" (c), "r" (a) : QP_CLOBBER)); +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_stoq.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_stoq.c new file mode 100644 index 0000000000..9202a7269b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_stoq.c @@ -0,0 +1,45 @@ +/* Software floating-point emulation. + (*c) = (long double)(a) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "single.h" +#include "quad.h" + +void _Qp_stoq(long double *c, const float a) +{ + FP_DECL_EX; + FP_DECL_S(A); + FP_DECL_Q(C); + + FP_INIT_ROUNDMODE; + FP_UNPACK_RAW_S(A, a); +#if (2 * _FP_W_TYPE_SIZE) < _FP_FRACBITS_Q + FP_EXTEND(Q,S,4,1,C,A); +#else + FP_EXTEND(Q,S,2,1,C,A); +#endif + FP_PACK_RAW_QP(c, C); + QP_HANDLE_EXCEPTIONS(__asm ( +" fstoq %1, %%f60\n" +" std %%f60, [%0]\n" +" std %%f62, [%0+8]\n" +" " : : "r" (c), "f" (a) : QP_CLOBBER)); +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_sub.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_sub.c new file mode 100644 index 0000000000..71b9890743 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_sub.c @@ -0,0 +1,44 @@ +/* Software floating-point emulation. + (*c) = (*a) - (*b) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +void _Qp_sub(long double *c, const long double *a, const long double *b) +{ + FP_DECL_EX; + FP_DECL_Q(A); FP_DECL_Q(B); FP_DECL_Q(C); + + FP_INIT_ROUNDMODE; + FP_UNPACK_SEMIRAW_QP(A, a); + FP_UNPACK_SEMIRAW_QP(B, b); + FP_SUB_Q(C, A, B); + FP_PACK_SEMIRAW_QP(c, C); + QP_HANDLE_EXCEPTIONS(__asm ( +" ldd [%1], %%f52\n" +" ldd [%1+8], %%f54\n" +" ldd [%2], %%f56\n" +" ldd [%2+8], %%f58\n" +" fsubq %%f52, %%f56, %%f60\n" +" std %%f60, [%0]\n" +" std %%f62, [%0+8]\n" +" " : : "r" (c), "r" (a), "r" (b) : QP_CLOBBER)); +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_uitoq.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_uitoq.c new file mode 100644 index 0000000000..cc8603ad41 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_uitoq.c @@ -0,0 +1,34 @@ +/* Software floating-point emulation. + (*c) = (long double)(a) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +void _Qp_uitoq(long double *c, const unsigned int a) +{ + FP_DECL_EX; + FP_DECL_Q(C); + unsigned int b = a; + + FP_FROM_INT_Q(C, b, 32, unsigned int); + FP_PACK_RAW_QP(c, C); + QP_NO_EXCEPTIONS; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_util.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_util.c new file mode 100644 index 0000000000..7e1f2511e2 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_util.c @@ -0,0 +1,60 @@ +/* Software floating-point emulation. + Helper routine for _Qp_* routines. + Simulate exceptions using double arithmetics. + Copyright (C) 1999-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <float.h> +#include <math.h> +#include <assert.h> +#include "soft-fp.h" + +void __Qp_handle_exceptions(int exceptions) +{ + if (exceptions & FP_EX_INVALID) + { + float f = 0.0; + __asm__ __volatile__ ("fdivs %0, %0, %0" : "+f" (f)); + } + if (exceptions & FP_EX_DIVZERO) + { + float f = 1.0, g = 0.0; + __asm__ __volatile__ ("fdivs %0, %1, %0" + : "+f" (f) + : "f" (g)); + } + if (exceptions & FP_EX_OVERFLOW) + { + float f = FLT_MAX; + __asm__ __volatile__("fmuls %0, %0, %0" : "+f" (f)); + exceptions &= ~FP_EX_INEXACT; + } + if (exceptions & FP_EX_UNDERFLOW) + { + float f = FLT_MIN; + __asm__ __volatile__("fmuls %0, %0, %0" : "+f" (f)); + exceptions &= ~FP_EX_INEXACT; + } + if (exceptions & FP_EX_INEXACT) + { + double d = 1.0, e = M_PI; + __asm__ __volatile__ ("fdivd %0, %1, %0" + : "+f" (d) + : "f" (e)); + } +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_uxtoq.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_uxtoq.c new file mode 100644 index 0000000000..766ca78872 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_uxtoq.c @@ -0,0 +1,34 @@ +/* Software floating-point emulation. + (*c) = (long double)(a) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +void _Qp_uxtoq(long double *c, const unsigned long a) +{ + FP_DECL_EX; + FP_DECL_Q(C); + unsigned long b = a; + + FP_FROM_INT_Q(C, b, 64, unsigned long); + FP_PACK_RAW_QP(c, C); + QP_NO_EXCEPTIONS; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_xtoq.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_xtoq.c new file mode 100644 index 0000000000..42c0bf1044 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/qp_xtoq.c @@ -0,0 +1,34 @@ +/* Software floating-point emulation. + (*c) = (long double)(*a) + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com) and + Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include "soft-fp.h" +#include "quad.h" + +void _Qp_xtoq(long double *c, const long a) +{ + FP_DECL_EX; + FP_DECL_Q(C); + long b = a; + + FP_FROM_INT_Q(C, b, 64, unsigned long); + FP_PACK_RAW_QP(c, C); + QP_NO_EXCEPTIONS; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/s_frexpl.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/s_frexpl.c new file mode 100644 index 0000000000..6f0baeb3fb --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/s_frexpl.c @@ -0,0 +1,51 @@ +/* Software floating-point emulation. + frexpl(x, exp) + Copyright (C) 1999-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +/* + * for non-zero x + * x = frexpl(arg,&exp); + * return a long double fp quantity x such that 0.5 <= |x| <1.0 + * and the corresponding binary exponent "exp". That is + * arg = x*2^exp. + * If arg is inf, 0.0, or NaN, then frexpl(arg,&exp) returns arg + * with *exp=0. + */ + +#include "soft-fp.h" +#include "quad.h" + +long double __frexpl(long double arg, int *exp) +{ + FP_DECL_EX; + FP_DECL_Q(A); + long double r; + + *exp = 0; + FP_UNPACK_Q(A, arg); + if (A_c != FP_CLS_NORMAL) + return arg; + *exp = A_e + 1; + A_e = -1; + FP_PACK_Q(r, A); + + return r; +} + +weak_alias (__frexpl, frexpl) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/s_scalblnl.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/s_scalblnl.c new file mode 100644 index 0000000000..250a8f4f0f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/s_scalblnl.c @@ -0,0 +1,52 @@ +/* Software floating-point emulation. + scalblnl(x, exp) + Copyright (C) 1999-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +/* + * scalblnl (long double x, long int n) + * scalblnl(x,n) returns x* 2**n computed by exponent + * manipulation rather than by actually performing an + * exponentiation or a multiplication. + */ + +#include "soft-fp.h" +#include "quad.h" + +long double __scalblnl(long double arg, int exp) +{ + FP_DECL_EX; + FP_DECL_Q(A); + long double r; + + FP_UNPACK_Q(A, arg); + switch (A_c) + { + case FP_CLS_ZERO: + return arg; + case FP_CLS_NAN: + case FP_CLS_INF: + FP_HANDLE_EXCEPTIONS; + return arg; + } + A_e += exp; + FP_PACK_Q(r, A); + FP_HANDLE_EXCEPTIONS; + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/s_scalbnl.c b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/s_scalbnl.c new file mode 100644 index 0000000000..c686175e97 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/s_scalbnl.c @@ -0,0 +1,52 @@ +/* Software floating-point emulation. + scalbnl(x, exp) + Copyright (C) 1999-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek (jj@ultra.linux.cz). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +/* + * scalbnl (long double x, int n) + * scalbnl(x,n) returns x* 2**n computed by exponent + * manipulation rather than by actually performing an + * exponentiation or a multiplication. + */ + +#include "soft-fp.h" +#include "quad.h" + +long double __scalbnl(long double arg, int exp) +{ + FP_DECL_EX; + FP_DECL_Q(A); + long double r; + + FP_UNPACK_Q(A, arg); + switch (A_c) + { + case FP_CLS_ZERO: + return arg; + case FP_CLS_NAN: + case FP_CLS_INF: + FP_HANDLE_EXCEPTIONS; + return arg; + } + A_e += exp; + FP_PACK_Q(r, A); + FP_HANDLE_EXCEPTIONS; + + return r; +} diff --git a/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/sfp-machine.h b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/sfp-machine.h new file mode 100644 index 0000000000..c03a6d3764 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/soft-fp/sfp-machine.h @@ -0,0 +1,147 @@ +/* Machine-dependent software floating-point definitions. + Sparc64 userland (_Q_* and _Qp_*) version. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson (rth@cygnus.com), + Jakub Jelinek (jj@ultra.linux.cz) and + David S. Miller (davem@redhat.com). + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <fpu_control.h> +#include <fenv.h> +#include <stdlib.h> + +#define _FP_W_TYPE_SIZE 64 +#define _FP_W_TYPE unsigned long +#define _FP_WS_TYPE signed long +#define _FP_I_TYPE long + +/* Helper macros for _FP_MUL_MEAT_2_120_240_double. */ +#define _FP_MUL_MEAT_SET_FE_TZ \ +do { \ + static fpu_control_t _fetz = _FPU_RC_DOWN; \ + _FPU_SETCW(_fetz); \ +} while (0) +#ifndef _FP_MUL_MEAT_RESET_FE +#define _FP_MUL_MEAT_RESET_FE _FPU_SETCW(_fcw) +#endif + +#define _FP_MUL_MEAT_S(R,X,Y) \ + _FP_MUL_MEAT_1_imm(_FP_WFRACBITS_S,R,X,Y) +#define _FP_MUL_MEAT_D(R,X,Y) \ + _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm) +#define _FP_MUL_MEAT_Q(R,X,Y) \ + _FP_MUL_MEAT_2_120_240_double(_FP_WFRACBITS_Q,R,X,Y, \ + _FP_MUL_MEAT_SET_FE_TZ, \ + _FP_MUL_MEAT_RESET_FE) + +#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_imm(S,R,X,Y,_FP_DIV_HELP_imm) +#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(D,R,X,Y) +#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y) + +#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) +#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1) +#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1 +#define _FP_NANSIGN_S 0 +#define _FP_NANSIGN_D 0 +#define _FP_NANSIGN_Q 0 + +#define _FP_KEEPNANFRACP 1 +#define _FP_QNANNEGATEDP 0 + +/* If one NaN is signaling and the other is not, + * we choose that one, otherwise we choose Y. + */ +#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \ + do { \ + if ((_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs) \ + && !(_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs)) \ + { \ + R##_s = X##_s; \ + _FP_FRAC_COPY_##wc(R,X); \ + } \ + else \ + { \ + R##_s = Y##_s; \ + _FP_FRAC_COPY_##wc(R,Y); \ + } \ + R##_c = FP_CLS_NAN; \ + } while (0) + +/* Obtain the current rounding mode. */ +#ifndef FP_ROUNDMODE +#define FP_ROUNDMODE ((_fcw >> 30) & 0x3) +#endif + +/* Exception flags. */ +#define FP_EX_INVALID (1 << 4) +#define FP_EX_OVERFLOW (1 << 3) +#define FP_EX_UNDERFLOW (1 << 2) +#define FP_EX_DIVZERO (1 << 1) +#define FP_EX_INEXACT (1 << 0) + +#define _FP_TININESS_AFTER_ROUNDING 0 + +#define _FP_DECL_EX \ + fpu_control_t _fcw __attribute__ ((unused)) = (FP_RND_NEAREST << 30) + +#define FP_INIT_ROUNDMODE \ +do { \ + _FPU_GETCW(_fcw); \ +} while (0) + +#define FP_TRAPPING_EXCEPTIONS ((_fcw >> 23) & 0x1f) +#define FP_INHIBIT_RESULTS ((_fcw >> 23) & _fex) + +/* Simulate exceptions using double arithmetics. */ +extern void __Qp_handle_exceptions(int exc); + +#define FP_HANDLE_EXCEPTIONS \ +do { \ + if (!_fex) \ + { \ + /* This is the common case, so we do it inline. \ + * We need to clear cexc bits if any. \ + */ \ + __asm__ __volatile__("fzero %%f62\n\t" \ + "faddd %%f62, %%f62, %%f62" \ + : : : "f62"); \ + } \ + else \ + { \ + __Qp_handle_exceptions (_fex); \ + } \ +} while (0) + +#define QP_HANDLE_EXCEPTIONS(_a) \ +do { \ + if ((_fcw >> 23) & _fex) \ + { \ + _a; \ + } \ + else \ + { \ + _fcw = (_fcw & ~0x1fL) | (_fex << 5) | _fex; \ + _FPU_SETCW(_fcw); \ + } \ +} while (0) + +#define QP_NO_EXCEPTIONS \ + __asm ("fzero %%f62\n\t" \ + "faddd %%f62, %%f62, %%f62" : : : "f62") + +#define QP_CLOBBER "memory", "f52", "f54", "f56", "f58", "f60", "f62" +#define QP_CLOBBER_CC QP_CLOBBER , "cc" diff --git a/REORG.TODO/sysdeps/sparc/sparc64/stackguard-macros.h b/REORG.TODO/sysdeps/sparc/sparc64/stackguard-macros.h new file mode 100644 index 0000000000..cc0c12c041 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/stackguard-macros.h @@ -0,0 +1,7 @@ +#include <stdint.h> + +#define STACK_CHK_GUARD \ + ({ uintptr_t x; asm ("ldx [%%g7+0x28], %0" : "=r" (x)); x; }) + +#define POINTER_CHK_GUARD \ + ({ uintptr_t x; asm ("ldx [%%g7+0x30], %0" : "=r" (x)); x; }) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/start.S b/REORG.TODO/sysdeps/sparc/sparc64/start.S new file mode 100644 index 0000000000..fcd4721463 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/start.S @@ -0,0 +1,100 @@ +/* Startup code for elf64-sparc + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Richard Henderson <richard@gnu.ai.mit.edu>, 1997. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + In addition to the permissions in the GNU Lesser General Public + License, the Free Software Foundation gives you unlimited + permission to link the compiled version of this file with other + programs, and to distribute those programs without any restriction + coming from the use of this file. (The GNU Lesser General Public + License restrictions do apply in other respects; for example, they + cover modification of the file, and distribution when not linked + into another program.) + + Note that people who make modified versions of this file are not + obligated to grant this special exception for their modified + versions; it is their choice whether to do so. The GNU Lesser + General Public License gives permission to release a modified + version without this exception; this exception also makes it + possible to release a modified version which carries forward this + exception. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + + .section ".text" + .align 4 + .global _start + .type _start,#function +_start: +#ifdef SHARED + SETUP_PIC_REG(l7) +#endif + + /* Terminate the stack frame, and reserve space for functions to + drop their arguments. */ + mov %g0, %fp + sub %sp, 6*8, %sp + + /* Extract the arguments and environment as encoded on the stack. The + argument info starts after one register window (16 words) past the SP, + plus the bias we added, plus the magic v9 STACK_BIAS. */ + ldx [%sp+STACK_BIAS+22*8], %o1 + add %sp, STACK_BIAS+23*8, %o2 + + /* Load the addresses of the user entry points. */ +#ifndef SHARED + sethi %hi(main), %o0 + sethi %hi(__libc_csu_init), %o3 + sethi %hi(__libc_csu_fini), %o4 + or %o0, %lo(main), %o0 + or %o3, %lo(__libc_csu_init), %o3 + or %o4, %lo(__libc_csu_fini), %o4 +#else + sethi %gdop_hix22(main), %o0 + sethi %gdop_hix22(__libc_csu_init), %o3 + sethi %gdop_hix22(__libc_csu_fini), %o4 + xor %o0, %gdop_lox10(main), %o0 + xor %o3, %gdop_lox10(__libc_csu_init), %o3 + xor %o4, %gdop_lox10(__libc_csu_fini), %o4 + ldx [%l7 + %o0], %o0, %gdop(main) + ldx [%l7 + %o3], %o3, %gdop(__libc_csu_init) + ldx [%l7 + %o4], %o4, %gdop(__libc_csu_fini) +#endif + + /* When starting a binary via the dynamic linker, %g1 contains the + address of the shared library termination function, which will be + registered with atexit(). If we are statically linked, this will + be NULL. */ + mov %g1, %o5 + + /* Let libc do the rest of the initialization, and call main. */ + call __libc_start_main + nop + + /* Die very horribly if exit returns. */ + illtrap 0 + + .size _start, .-_start + +/* Define a symbol for the first piece of initialized data. */ + .data + .globl __data_start +__data_start: + .long 0 +weak_alias (__data_start, data_start) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/stpcpy.S b/REORG.TODO/sysdeps/sparc/sparc64/stpcpy.S new file mode 100644 index 0000000000..b1593563a9 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/stpcpy.S @@ -0,0 +1,274 @@ +/* Copy SRC to DEST returning the address of the terminating '\0' in DEST. + For SPARC v9. + Copyright (C) 1998-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jan Vondrak <jvon4518@ss1000.ms.mff.cuni.cz> and + Jakub Jelinek <jj@ultra.linux.cz>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <asm/asi.h> +#ifndef XCC + .register %g2, #scratch + .register %g3, #scratch + .register %g6, #scratch +#endif + + /* Normally, this uses + ((xword - 0x0101010101010101) & 0x8080808080808080) test + to find out if any byte in xword could be zero. This is fast, but + also gives false alarm for any byte in range 0x81-0xff. It does + not matter for correctness, as if this test tells us there could + be some zero byte, we check it byte by byte, but if bytes with + high bits set are common in the strings, then this will give poor + performance. You can #define EIGHTBIT_NOT_RARE and the algorithm + will use one tick slower, but more precise test + ((xword - 0x0101010101010101) & (~xword) & 0x8080808080808080), + which does not give any false alarms (but if some bits are set, + one cannot assume from it which bytes are zero and which are not). + It is yet to be measured, what is the correct default for glibc + in these days for an average user. + */ + + .text + .align 32 +ENTRY(__stpcpy) + sethi %hi(0x01010101), %g1 /* IEU0 Group */ + or %g1, %lo(0x01010101), %g1 /* IEU0 Group */ + andcc %o0, 7, %g0 /* IEU1 */ + sllx %g1, 32, %g2 /* IEU0 Group */ + + bne,pn %icc, 12f /* CTI */ + andcc %o1, 7, %g3 /* IEU1 */ + or %g1, %g2, %g1 /* IEU0 Group */ + bne,pn %icc, 14f /* CTI */ + + sllx %g1, 7, %g2 /* IEU0 Group */ +1: ldx [%o1], %o3 /* Load */ + add %o1, 8, %o1 /* IEU1 */ +2: mov %o3, %g3 /* IEU0 Group */ + + sub %o3, %g1, %o2 /* IEU1 */ +3: ldxa [%o1] ASI_PNF, %o3 /* Load */ +#ifdef EIGHTBIT_NOT_RARE + andn %o2, %g3, %o2 /* IEU0 Group */ +#endif + add %o0, 8, %o0 /* IEU0 Group */ + andcc %o2, %g2, %g0 /* IEU1 */ + + add %o1, 8, %o1 /* IEU0 Group */ + be,a,pt %xcc, 2b /* CTI */ + stx %g3, [%o0 - 8] /* Store */ + srlx %g3, 56, %g5 /* IEU0 Group */ + + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 11f /* CTI */ + srlx %g3, 48, %g4 /* IEU0 */ + andcc %g4, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 10f /* CTI */ + srlx %g3, 40, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 9f /* CTI */ + + srlx %g3, 32, %g4 /* IEU0 */ + andcc %g4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 8f /* CTI */ + srlx %g3, 24, %g5 /* IEU0 */ + + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 7f /* CTI */ + srlx %g3, 16, %g4 /* IEU0 */ + andcc %g4, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 6f /* CTI */ + srlx %g3, 8, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 5f /* CTI */ + + sub %o3, %g1, %o2 /* IEU0 */ + stx %g3, [%o0 - 8] /* Store Group */ + andcc %g3, 0xff, %g0 /* IEU1 */ + bne,pt %icc, 3b /* CTI */ + + mov %o3, %g3 /* IEU0 Group */ +4: retl /* CTI+IEU1 Group */ + sub %o0, 1, %o0 /* IEU0 */ + + .align 16 +6: ba,pt %xcc, 23f /* CTI Group */ + sub %o0, 3, %g6 /* IEU0 */ +5: sub %o0, 2, %g6 /* IEU0 Group */ + stb %g5, [%o0 - 2] /* Store */ + + srlx %g3, 16, %g4 /* IEU0 Group */ +23: sth %g4, [%o0 - 4] /* Store */ + srlx %g3, 32, %g4 /* IEU0 Group */ + stw %g4, [%o0 - 8] /* Store */ + + retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ +8: ba,pt %xcc, 24f /* CTI Group */ + sub %o0, 5, %g6 /* IEU0 */ + +7: sub %o0, 4, %g6 /* IEU0 Group */ + stb %g5, [%o0 - 4] /* Store */ + srlx %g3, 32, %g4 /* IEU0 Group */ +24: stw %g4, [%o0 - 8] /* Store */ + + retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ +10: ba,pt %xcc, 25f /* CTI Group */ + sub %o0, 7, %g6 /* IEU0 */ + +9: sub %o0, 6, %g6 /* IEU0 Group */ + stb %g5, [%o0 - 6] /* Store */ + srlx %g3, 48, %g4 /* IEU0 */ +25: sth %g4, [%o0 - 8] /* Store Group */ + + retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ +11: stb %g5, [%o0 - 8] /* Store Group */ + retl /* CTI+IEU1 Group */ + + sub %o0, 8, %o0 /* IEU0 */ + + .align 16 +12: or %g1, %g2, %g1 /* IEU0 Group */ + ldub [%o1], %o3 /* Load */ + sllx %g1, 7, %g2 /* IEU0 Group */ + stb %o3, [%o0] /* Store Group */ + +13: add %o0, 1, %o0 /* IEU0 */ + add %o1, 1, %o1 /* IEU1 */ + andcc %o3, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 4b /* CTI */ + + lduba [%o1] ASI_PNF, %o3 /* Load */ + andcc %o0, 7, %g0 /* IEU1 Group */ + bne,a,pt %icc, 13b /* CTI */ + stb %o3, [%o0] /* Store */ + + andcc %o1, 7, %g3 /* IEU1 Group */ + be,a,pt %icc, 1b /* CTI */ + ldx [%o1], %o3 /* Load */ +14: orcc %g0, 64, %g4 /* IEU1 Group */ + + sllx %g3, 3, %g5 /* IEU0 */ + sub %o1, %g3, %o1 /* IEU0 Group */ + sub %g4, %g5, %g4 /* IEU1 */ + /* %g1 = 0101010101010101 * + * %g2 = 8080808080808080 * + * %g3 = source alignment * + * %g5 = number of bits to shift left * + * %g4 = number of bits to shift right */ + ldxa [%o1] ASI_PNF, %o5 /* Load Group */ + + addcc %o1, 8, %o1 /* IEU1 */ +15: sllx %o5, %g5, %o3 /* IEU0 Group */ + ldxa [%o1] ASI_PNF, %o5 /* Load */ + srlx %o5, %g4, %o4 /* IEU0 Group */ + + add %o0, 8, %o0 /* IEU1 */ + or %o3, %o4, %o3 /* IEU0 Group */ + add %o1, 8, %o1 /* IEU1 */ + sub %o3, %g1, %o4 /* IEU0 Group */ + +#ifdef EIGHTBIT_NOT_RARE + andn %o4, %o3, %o4 /* IEU0 Group */ +#endif + andcc %o4, %g2, %g0 /* IEU1 Group */ + be,a,pt %xcc, 15b /* CTI */ + stx %o3, [%o0 - 8] /* Store */ + srlx %o3, 56, %o4 /* IEU0 Group */ + + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 22f /* CTI */ + srlx %o3, 48, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 21f /* CTI */ + srlx %o3, 40, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 20f /* CTI */ + + srlx %o3, 32, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 19f /* CTI */ + srlx %o3, 24, %o4 /* IEU0 */ + + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 18f /* CTI */ + srlx %o3, 16, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 17f /* CTI */ + srlx %o3, 8, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 16f /* CTI */ + + andcc %o3, 0xff, %g0 /* IEU1 Group */ + bne,pn %icc, 15b /* CTI */ + stx %o3, [%o0 - 8] /* Store */ + retl /* CTI+IEU1 Group */ + + sub %o0, 1, %o0 /* IEU0 */ + + .align 16 +17: ba,pt %xcc, 26f /* CTI Group */ + subcc %o0, 3, %g6 /* IEU1 */ +18: ba,pt %xcc, 27f /* CTI Group */ + subcc %o0, 4, %g6 /* IEU1 */ + +19: ba,pt %xcc, 28f /* CTI Group */ + subcc %o0, 5, %g6 /* IEU1 */ +16: subcc %o0, 2, %g6 /* IEU1 Group */ + srlx %o3, 8, %o4 /* IEU0 */ + + stb %o4, [%o0 - 2] /* Store */ +26: srlx %o3, 16, %o4 /* IEU0 Group */ + stb %o4, [%o0 - 3] /* Store */ +27: srlx %o3, 24, %o4 /* IEU0 Group */ + + stb %o4, [%o0 - 4] /* Store */ +28: srlx %o3, 32, %o4 /* IEU0 Group */ + stw %o4, [%o0 - 8] /* Store */ + retl /* CTI+IEU1 Group */ + + mov %g6, %o0 /* IEU0 */ + + .align 16 +21: ba,pt %xcc, 29f /* CTI Group */ + subcc %o0, 7, %g6 /* IEU1 */ +22: ba,pt %xcc, 30f /* CTI Group */ + subcc %o0, 8, %g6 /* IEU1 */ + +20: subcc %o0, 6, %g6 /* IEU1 Group */ + srlx %o3, 40, %o4 /* IEU0 */ + stb %o4, [%o0 - 6] /* Store */ +29: srlx %o3, 48, %o4 /* IEU0 Group */ + + stb %o4, [%o0 - 7] /* Store */ +30: srlx %o3, 56, %o4 /* IEU0 Group */ + stb %o4, [%o0 - 8] /* Store */ + retl /* CTI+IEU1 Group */ + + mov %g6, %o0 /* IEU0 */ +END(__stpcpy) + +weak_alias (__stpcpy, stpcpy) +libc_hidden_def (__stpcpy) +libc_hidden_builtin_def (stpcpy) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/stpncpy.S b/REORG.TODO/sysdeps/sparc/sparc64/stpncpy.S new file mode 100644 index 0000000000..537d29257f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/stpncpy.S @@ -0,0 +1,424 @@ +/* stpncpy(DST, SRC, COUNT) - Copy no more than N characters of + SRC to DEST, returning the address of the terminating '\0' in + DEST, if any, or else DEST + N. + For SPARC v9. + Copyright (C) 1998-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jj@ultra.linux.cz> and + Jan Vondrak <jvon4518@ss1000.ms.mff.cuni.cz>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <asm/asi.h> +#ifndef XCC +#define XCC xcc +#define USE_BPR + .register %g2, #scratch + .register %g3, #scratch + .register %g6, #scratch +#endif + + /* Normally, this uses + ((xword - 0x0101010101010101) & 0x8080808080808080) test + to find out if any byte in xword could be zero. This is fast, but + also gives false alarm for any byte in range 0x81-0xff. It does + not matter for correctness, as if this test tells us there could + be some zero byte, we check it byte by byte, but if bytes with + high bits set are common in the strings, then this will give poor + performance. You can #define EIGHTBIT_NOT_RARE and the algorithm + will use one tick slower, but more precise test + ((xword - 0x0101010101010101) & (~xword) & 0x8080808080808080), + which does not give any false alarms (but if some bits are set, + one cannot assume from it which bytes are zero and which are not). + It is yet to be measured, what is the correct default for glibc + in these days for an average user. + */ + + .text + .align 32 +ENTRY(__stpncpy) + sethi %hi(0x01010101), %g1 /* IEU0 Group */ +#ifdef USE_BPR + brz,pn %o2, 19f /* CTI+IEU1 */ +#else + tst %o2 /* IEU1 */ + be,pn %XCC, 19f /* CTI */ +#endif + or %g1, %lo(0x01010101), %g1 /* IEU1 */ + andcc %o0, 7, %g0 /* IEU1 Group */ + + sllx %g1, 32, %g2 /* IEU0 */ + bne,pn %icc, 26f /* CTI */ + or %g1, %g2, %g1 /* IEU0 Group */ + andcc %o1, 7, %g3 /* IEU1 */ + + bne,pn %icc, 28f /* CTI */ + sllx %g1, 7, %g2 /* IEU0 Group */ + ldx [%o1], %o3 /* Load */ +1: add %o1, 8, %o1 /* IEU1 */ + +2: subcc %o2, 8, %o2 /* IEU1 Group */ + bl,pn %XCC, 18f /* CTI */ + sub %o3, %g1, %o4 /* IEU0 */ + add %o0, 8, %o0 /* IEU0 Group */ + +#ifdef EIGHTBIT_NOT_MORE + andn %o4, %o3, %o4 /* IEU1 */ +#endif + mov %o3, %g3 /* IEU1 */ + ldxa [%o1] ASI_PNF, %o3 /* Load */ + add %o1, 8, %o1 /* IEU0 Group */ + andcc %o4, %g2, %g0 /* IEU1 */ + + be,a,pt %xcc, 2b /* CTI */ + stx %g3, [%o0-8] /* Store Group */ + srlx %g3, 56, %g5 /* IEU0 Group */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 16f /* CTI */ + srlx %g3, 48, %g4 /* IEU0 */ + andcc %g4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 15f /* CTI */ + + srlx %g3, 40, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 14f /* CTI */ + srlx %g3, 32, %g4 /* IEU0 */ + + andcc %g4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 13f /* CTI */ + srlx %g3, 24, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 12f /* CTI */ + srlx %g3, 16, %g4 /* IEU0 */ + andcc %g4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 11f /* CTI */ + + srlx %g3, 8, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 10f /* CTI */ + sub %o0, 1, %g6 /* IEU0 */ + + andcc %g3, 0xff, %g0 /* IEU1 Group */ + bne,pt %icc, 2b /* CTI */ +3: stx %g3, [%o0-8] /* Store */ + andncc %o2, 31, %g3 /* IEU1 Group */ + +4: be,pn %XCC, 41f /* CTI */ + and %o2, 31, %o2 /* IEU1 Group */ +40: stx %g0, [%o0] /* Store */ + stx %g0, [%o0 + 8] /* Store Group */ + + subcc %g3, 32, %g3 /* IEU1 */ + stx %g0, [%o0 + 16] /* Store Group */ + stx %g0, [%o0 + 24] /* Store Group */ + bne,pt %XCC, 40b /* CTI */ + + add %o0, 32, %o0 /* IEU0 */ +41: subcc %o2, 8, %o2 /* IEU1 Group */ + bl,a,pn %XCC, 6f /* CTI */ + andcc %o2, 4, %g0 /* IEU1 Group */ + +5: stx %g0, [%o0] /* Store */ + subcc %o2, 8, %o2 /* IEU1 Group */ + bge,pt %XCC, 5b /* CTI */ + add %o0, 8, %o0 /* IEU0 */ + + andcc %o2, 4, %g0 /* IEU1 Group */ +6: be,a,pn %icc, 7f /* CTI */ + andcc %o2, 2, %g0 /* IEU1 Group */ + stw %g0, [%o0] /* Store */ + + add %o0, 4, %o0 /* IEU0 */ + andcc %o2, 2, %g0 /* IEU1 Group */ +7: be,a,pn %icc, 8f /* CTI */ + andcc %o2, 1, %g0 /* IEU1 Group */ + + sth %g0, [%o0] /* Store */ + add %o0, 2, %o0 /* IEU0 */ + andcc %o2, 1, %g0 /* IEU1 Group */ +8: bne,a,pn %icc, 9f /* CTI */ + + stb %g0, [%o0] /* Store */ +9: retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ +10: subcc %o0, 2, %g6 /* IEU1 Group */ + + ba,pt %xcc, 3b /* CTI */ + sllx %g5, 8, %g3 /* IEU0 */ +11: subcc %o0, 3, %g6 /* IEU1 Group */ + ba,pt %xcc, 3b /* CTI */ + + sllx %g4, 16, %g3 /* IEU0 */ +12: subcc %o0, 4, %g6 /* IEU1 Group */ + ba,pt %xcc, 3b /* CTI */ + sllx %g5, 24, %g3 /* IEU0 */ + +13: subcc %o0, 5, %g6 /* IEU1 Group */ + ba,pt %xcc, 3b /* CTI */ + sllx %g4, 32, %g3 /* IEU0 */ +14: subcc %o0, 6, %g6 /* IEU1 Group */ + + ba,pt %xcc, 3b /* CTI */ + sllx %g5, 40, %g3 /* IEU0 */ +15: subcc %o0, 7, %g6 /* IEU1 Group */ + ba,pt %xcc, 3b /* CTI */ + + sllx %g4, 48, %g3 /* IEU0 */ +16: subcc %o0, 8, %g6 /* IEU1 Group */ + ba,pt %xcc, 3b /* CTI */ + clr %g3 /* IEU0 */ + + .align 16 +17: or %o3, %o4, %o3 /* IEU0 Group */ + sub %o3, %g1, %o4 /* IEU1 */ +18: addcc %o2, 8, %o2 /* IEU1 Group */ + be,pn %XCC, 19f /* CTI */ + + andcc %o4, %g2, %g0 /* IEU1 Group */ + be,pt %xcc, 21f /* CTI */ + srlx %o3, 56, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 20f /* CTI */ + stb %g5, [%o0] /* Store */ + add %o0, 1, %o0 /* IEU0 Group */ + subcc %o2, 1, %o2 /* IEU1 */ + + be,pn %XCC, 19f /* CTI */ + srlx %o3, 48, %g5 /* IEU0 Group */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 20f /* CTI */ + + stb %g5, [%o0] /* Store */ + add %o0, 1, %o0 /* IEU0 Group */ + subcc %o2, 1, %o2 /* IEU1 */ + be,pn %XCC, 19f /* CTI */ + + srlx %o3, 40, %g5 /* IEU0 Group */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 20f /* CTI */ + stb %g5, [%o0] /* Store */ + + add %o0, 1, %o0 /* IEU0 Group */ + subcc %o2, 1, %o2 /* IEU1 */ + be,pn %XCC, 19f /* CTI */ + srlx %o3, 32, %g5 /* IEU0 Group */ + + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 20f /* CTI */ + stb %g5, [%o0] /* Store */ + add %o0, 1, %o0 /* IEU0 Group */ + + subcc %o2, 1, %o2 /* IEU1 */ + be,pn %XCC, 19f /* CTI */ + srlx %o3, 24, %g5 /* IEU0 Group */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 20f /* CTI */ + stb %g5, [%o0] /* Store */ + add %o0, 1, %o0 /* IEU0 Group */ + subcc %o2, 1, %o2 /* IEU1 */ + + be,pn %XCC, 19f /* CTI */ + srlx %o3, 16, %g5 /* IEU0 Group */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 20f /* CTI */ + + stb %g5, [%o0] /* Store */ + add %o0, 1, %o0 /* IEU0 Group */ + subcc %o2, 1, %o2 /* IEU1 */ + be,pn %XCC, 19f /* CTI */ + + srlx %o3, 8, %o3 /* IEU0 Group */ + stb %o3, [%o0] /* Store */ +59: add %o0, 1, %o2 /* IEU1 */ + andcc %o3, 0xff, %g0 /* IEU1 Group */ + + retl /* CTI+IEU1 Group */ + movne %icc, %o2, %o0 /* Single Group */ +19: retl /* CTI+IEU1 Group */ + nop /* IEU0 */ + +20: mov %o0, %g6 /* IEU0 Group */ + subcc %o2, 1, %o2 /* IEU1 */ + be,pn %XCC, 51f /* CTI */ + add %o0, 1, %o0 /* IEU0 Group */ + +50: stb %g0, [%o0] /* Store Group */ + subcc %o2, 1, %o2 /* IEU1 Group */ + bne,pt %XCC, 50b /* CTI */ + add %o0, 1, %o0 /* IEU0 */ + +51: retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ + + .align 16 +21: andcc %o2, 4, %g0 /* IEU1 Group */ + be,pn %icc, 22f /* CTI */ + srlx %o3, 32, %g5 /* IEU0 */ + stw %g5, [%o0] /* Store Group */ + + add %o0, 4, %o0 /* IEU0 */ + mov %o3, %g5 /* IEU1 */ +22: andcc %o2, 2, %g0 /* IEU1 Group */ + be,pn %icc, 23f /* CTI */ + + srlx %g5, 16, %g4 /* IEU0 */ + sth %g4, [%o0] /* Store Group */ + add %o0, 2, %o0 /* IEU0 */ + mov %g5, %g4 /* IEU1 */ + +23: srlx %g4, 8, %g4 /* IEU0 Group */ + andcc %o2, 1, %g0 /* IEU1 */ + bne,a,pn %icc, 24f /* CTI */ + stb %g4, [%o0] /* Store Group */ + + retl /* CTI+IEU1 Group */ + nop /* IEU0 */ +24: retl /* CTI+IEU1 Group */ + add %o0, 1, %o0 /* IEU0 */ + + .align 16 +55: sub %o0, 1, %g6 /* IEU0 Group */ +25: andcc %o0, 7, %g0 /* IEU1 */ + be,a,pn %icc, 4b /* CTI */ + andncc %o2, 31, %g3 /* IEU1 Group */ + + stb %g0, [%o0] /* Store Group */ + subcc %o2, 1, %o2 /* IEU1 */ + bne,pt %XCC, 25b /* CTI */ + add %o0, 1, %o0 /* IEU0 Group */ + + retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ + + .align 16 +26: ldub [%o1], %o3 /* Load */ + sllx %g1, 7, %g2 /* IEU0 Group */ + stb %o3, [%o0] /* Store */ +27: subcc %o2, 1, %o2 /* IEU1 */ + + be,pn %XCC, 59b /* CTI */ + add %o1, 1, %o1 /* IEU0 Group */ + add %o0, 1, %o0 /* IEU1 */ + andcc %o3, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 55b /* CTI */ + lduba [%o1] ASI_PNF, %o3 /* Load */ + andcc %o0, 7, %g0 /* IEU1 Group */ + bne,a,pt %icc, 27b /* CTI */ + + stb %o3, [%o0] /* Store */ + andcc %o1, 7, %g3 /* IEU1 Group */ + be,a,pt %icc, 1b /* CTI */ + ldx [%o1], %o3 /* Load */ + +28: orcc %g0, 64, %g4 /* IEU1 Group */ + sllx %g3, 3, %g5 /* IEU0 */ + sub %g4, %g5, %g4 /* IEU0 Group */ + sub %o1, %g3, %o1 /* IEU1 */ + /* %g1 = 0101010101010101 + %g2 = 8080808080808080 + %g3 = source alignment + %g5 = number of bits to shift left + %g4 = number of bits to shift right */ + + ldxa [%o1] ASI_PNF, %o5 /* Load Group */ + addcc %o1, 8, %o1 /* IEU1 */ +29: sllx %o5, %g5, %o3 /* IEU0 Group */ + ldxa [%o1] ASI_PNF, %o5 /* Load */ + + subcc %o2, 8, %o2 /* IEU1 */ + bl,pn %XCC, 17b /* CTI */ + srlx %o5, %g4, %o4 /* IEU0 Group */ + add %o1, 8, %o1 /* IEU1 */ + + or %o3, %o4, %o3 /* IEU0 Group */ + add %o0, 8, %o0 /* IEU1 */ + sub %o3, %g1, %o4 /* IEU0 Group */ +#ifdef EIGHTBIT_NOT_RARE + andn %o4, %o3, %o4 /* IEU0 Group */ +#endif + andcc %o4, %g2, %g0 /* IEU1 Group */ + + be,a,pt %xcc, 29b /* CTI */ + stx %o3, [%o0-8] /* Store */ + srlx %o3, 56, %o4 /* IEU0 Group */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 36f /* CTI */ + srlx %o3, 48, %g6 /* IEU0 */ + andcc %g6, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 35f /* CTI */ + + srlx %o3, 40, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 34f /* CTI */ + srlx %o3, 32, %g6 /* IEU0 */ + + andcc %g6, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 33f /* CTI */ + srlx %o3, 24, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 32f /* CTI */ + srlx %o3, 16, %g6 /* IEU0 */ + andcc %g6, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 31f /* CTI */ + + srlx %o3, 8, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 30f /* CTI */ + andcc %o3, 0xff, %g0 /* IEU1 Group */ + + bne,pn %icc, 29b /* CTI */ + stx %o3, [%o0-8] /* Store */ + sub %o0, 1, %g6 /* IEU0 Group */ + ba,pt %xcc, 4b /* CTI */ + + andncc %o2, 31, %g3 /* IEU1 */ +30: subcc %o0, 2, %g6 /* IEU0 */ + ba,pt %xcc, 3b /* CTI */ + sllx %o4, 8, %g3 /* IEU0 Group */ + +31: sllx %g6, 16, %g3 /* IEU0 Group */ + ba,pt %xcc, 3b /* CTI */ + sub %o0, 3, %g6 /* IEU1 */ +32: subcc %o0, 4, %g6 /* IEU1 Group */ + + ba,pt %xcc, 3b /* CTI */ + sllx %o4, 24, %g3 /* IEU0 */ +33: sllx %g6, 32, %g3 /* IEU0 Group */ + ba,pt %xcc, 3b /* CTI */ + + sub %o0, 5, %g6 /* IEU1 */ +34: subcc %o0, 6, %g6 /* IEU1 Group */ + ba,pt %xcc, 3b /* CTI */ + sllx %o4, 40, %g3 /* IEU0 */ + +35: sllx %g6, 48, %g3 /* IEU0 Group */ + ba,pt %xcc, 3b /* CTI */ + sub %o0, 7, %g6 /* IEU1 */ +36: subcc %o0, 8, %g6 /* IEU1 Group */ + + ba,pt %xcc, 3b /* CTI */ + sllx %o4, 56, %g3 /* IEU0 */ +END(__stpncpy) + +libc_hidden_def (__stpncpy) +weak_alias (__stpncpy, stpncpy) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/strcat.S b/REORG.TODO/sysdeps/sparc/sparc64/strcat.S new file mode 100644 index 0000000000..151a4e8853 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/strcat.S @@ -0,0 +1,339 @@ +/* strcat (dest, src) -- Append SRC on the end of DEST. + For SPARC v9. + Copyright (C) 1998-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jj@ultra.linux.cz> and + Jan Vondrak <jvon4518@ss1000.ms.mff.cuni.cz>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <asm/asi.h> +#ifndef XCC +#define XCC xcc +#define USE_BPR + .register %g2, #scratch + .register %g3, #scratch + .register %g6, #scratch +#endif + + /* Normally, this uses + ((xword - 0x0101010101010101) & 0x8080808080808080) test + to find out if any byte in xword could be zero. This is fast, but + also gives false alarm for any byte in range 0x81-0xff. It does + not matter for correctness, as if this test tells us there could + be some zero byte, we check it byte by byte, but if bytes with + high bits set are common in the strings, then this will give poor + performance. You can #define EIGHTBIT_NOT_RARE and the algorithm + will use one tick slower, but more precise test + ((xword - 0x0101010101010101) & (~xword) & 0x8080808080808080), + which does not give any false alarms (but if some bits are set, + one cannot assume from it which bytes are zero and which are not). + It is yet to be measured, what is the correct default for glibc + in these days for an average user. + */ + + .text + .align 32 +ENTRY(strcat) + sethi %hi(0x01010101), %g1 /* IEU0 Group */ + ldub [%o0], %o3 /* Load */ + or %g1, %lo(0x01010101), %g1 /* IEU0 Group */ + mov %o0, %g6 /* IEU1 */ + + sllx %g1, 32, %g2 /* IEU0 Group */ + andcc %o0, 7, %g0 /* IEU1 */ + or %g1, %g2, %g1 /* IEU0 Group */ + bne,pn %icc, 32f /* CTI */ + + sllx %g1, 7, %g2 /* IEU0 Group */ + brz,pn %o3, 30f /* CTI+IEU1 */ + ldx [%o0], %o3 /* Load */ +48: add %o0, 8, %o0 /* IEU0 Group */ + +49: sub %o3, %g1, %o2 /* IEU0 Group */ +#ifdef EIGHTBIT_NOT_RARE + andn %o2, %o3, %g5 /* IEU0 Group */ + ldxa [%o0] ASI_PNF, %o3 /* Load */ + andcc %g5, %g2, %g0 /* IEU1 Group */ +#else + ldxa [%o0] ASI_PNF, %o3 /* Load */ + andcc %o2, %g2, %g0 /* IEU1 Group */ +#endif + be,pt %xcc, 49b /* CTI */ + + add %o0, 8, %o0 /* IEU0 */ + addcc %o2, %g1, %g3 /* IEU1 Group */ + srlx %o2, 32, %o2 /* IEU0 */ +50: andcc %o2, %g2, %g0 /* IEU1 Group */ + + be,pn %xcc, 51f /* CTI */ + srlx %g3, 56, %o2 /* IEU0 */ + andcc %o2, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 29f /* CTI */ + + srlx %g3, 48, %o2 /* IEU0 */ + andcc %o2, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 28f /* CTI */ + srlx %g3, 40, %o2 /* IEU0 */ + + andcc %o2, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 27f /* CTI */ + srlx %g3, 32, %o2 /* IEU0 */ + andcc %o2, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 26f /* CTI */ +51: srlx %g3, 24, %o2 /* IEU0 */ + andcc %o2, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 25f /* CTI */ + + srlx %g3, 16, %o2 /* IEU0 */ + andcc %o2, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 24f /* CTI */ + srlx %g3, 8, %o2 /* IEU0 */ + + andcc %o2, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 23f /* CTI */ + sub %o3, %g1, %o2 /* IEU0 */ + andcc %g3, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 52f /* CTI */ + ldxa [%o0] ASI_PNF, %o3 /* Load */ + andcc %o2, %g2, %g0 /* IEU1 Group */ + be,pt %xcc, 49b /* CTI */ + + add %o0, 8, %o0 /* IEU0 */ + addcc %o2, %g1, %g3 /* IEU1 Group */ + ba,pt %xcc, 50b /* CTI */ + srlx %o2, 32, %o2 /* IEU0 */ + + .align 16 +52: ba,pt %xcc, 12f /* CTI Group */ + add %o0, -9, %o0 /* IEU0 */ +23: ba,pt %xcc, 12f /* CTI Group */ + add %o0, -10, %o0 /* IEU0 */ + +24: ba,pt %xcc, 12f /* CTI Group */ + add %o0, -11, %o0 /* IEU0 */ +25: ba,pt %xcc, 12f /* CTI Group */ + add %o0, -12, %o0 /* IEU0 */ + +26: ba,pt %xcc, 12f /* CTI Group */ + add %o0, -13, %o0 /* IEU0 */ +27: ba,pt %xcc, 12f /* CTI Group */ + add %o0, -14, %o0 /* IEU0 */ + +28: ba,pt %xcc, 12f /* CTI Group */ + add %o0, -15, %o0 /* IEU0 */ +29: add %o0, -16, %o0 /* IEU0 Group */ +30: andcc %o1, 7, %g3 /* IEU1 */ + +31: bne,pn %icc, 14f /* CTI */ + orcc %g0, 64, %g4 /* IEU1 Group */ +1: ldx [%o1], %o3 /* Load */ + add %o1, 8, %o1 /* IEU1 */ + +2: mov %o3, %g3 /* IEU0 Group */ +3: sub %o3, %g1, %o2 /* IEU1 */ + ldxa [%o1] ASI_PNF, %o3 /* Load */ +#ifdef EIGHTBIT_NOT_RARE + andn %o2, %g3, %o2 /* IEU0 Group */ +#endif + add %o0, 8, %o0 /* IEU0 Group */ + + andcc %o2, %g2, %g0 /* IEU1 */ + add %o1, 8, %o1 /* IEU0 Group */ + be,a,pt %xcc, 2b /* CTI */ + stx %g3, [%o0 - 8] /* Store */ + + srlx %g3, 56, %g5 /* IEU0 Group */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 11f /* CTI */ + srlx %g3, 48, %g4 /* IEU0 */ + + andcc %g4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 10f /* CTI */ + srlx %g3, 40, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 9f /* CTI */ + srlx %g3, 32, %g4 /* IEU0 */ + andcc %g4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 8f /* CTI */ + + srlx %g3, 24, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 7f /* CTI */ + srlx %g3, 16, %g4 /* IEU0 */ + + andcc %g4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 6f /* CTI */ + srlx %g3, 8, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 5f /* CTI */ + sub %o3, %g1, %o2 /* IEU0 */ + stx %g3, [%o0 - 8] /* Store Group */ + andcc %g3, 0xff, %g0 /* IEU1 */ + + bne,pt %icc, 3b /* CTI */ + mov %o3, %g3 /* IEU0 Group */ +4: retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ + + .align 16 +5: stb %g5, [%o0 - 2] /* Store Group */ + srlx %g3, 16, %g4 /* IEU0 */ +6: sth %g4, [%o0 - 4] /* Store Group */ + srlx %g3, 32, %g4 /* IEU0 */ + + stw %g4, [%o0 - 8] /* Store Group */ + retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ +7: stb %g5, [%o0 - 4] /* Store Group */ + + srlx %g3, 32, %g4 /* IEU0 */ +8: stw %g4, [%o0 - 8] /* Store Group */ + retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ + +9: stb %g5, [%o0 - 6] /* Store Group */ + srlx %g3, 48, %g4 /* IEU0 */ +10: sth %g4, [%o0 - 8] /* Store Group */ + retl /* CTI+IEU1 Group */ + + mov %g6, %o0 /* IEU0 */ +11: stb %g5, [%o0 - 8] /* Store Group */ + retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ + + .align 16 +32: andcc %o0, 7, %g0 /* IEU1 Group */ + be,a,pn %icc, 48b /* CTI */ + ldx [%o0], %o3 /* Load */ + add %o0, 1, %o0 /* IEU0 Group */ + + brnz,a,pt %o3, 32b /* CTI+IEU1 */ + lduba [%o0] ASI_PNF, %o3 /* Load */ + add %o0, -1, %o0 /* IEU0 Group */ + andcc %o0, 7, %g0 /* IEU1 Group */ + + be,a,pn %icc, 31b /* CTI */ + andcc %o1, 7, %g3 /* IEU1 Group */ +12: ldub [%o1], %o3 /* Load */ + stb %o3, [%o0] /* Store Group */ + +13: add %o0, 1, %o0 /* IEU0 */ + add %o1, 1, %o1 /* IEU1 */ + andcc %o3, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 4b /* CTI */ + + lduba [%o1] ASI_PNF, %o3 /* Load */ + andcc %o0, 7, %g0 /* IEU1 Group */ + bne,a,pt %icc, 13b /* CTI */ + stb %o3, [%o0] /* Store */ + + andcc %o1, 7, %g3 /* IEU1 Group */ + be,a,pt %icc, 1b /* CTI */ + ldx [%o1], %o3 /* Load */ + orcc %g0, 64, %g4 /* IEU1 Group */ + +14: sllx %g3, 3, %g5 /* IEU0 */ + sub %o1, %g3, %o1 /* IEU0 Group */ + sub %g4, %g5, %g4 /* IEU1 */ + /* %g1 = 0101010101010101 * + * %g2 = 8080808080808080 * + * %g3 = source alignment * + * %g5 = number of bits to shift left * + * %g4 = number of bits to shift right */ + ldxa [%o1] ASI_PNF, %o5 /* Load Group */ + + addcc %o1, 8, %o1 /* IEU1 */ +15: sllx %o5, %g5, %o3 /* IEU0 Group */ + ldxa [%o1] ASI_PNF, %o5 /* Load */ + srlx %o5, %g4, %o4 /* IEU0 Group */ + + add %o0, 8, %o0 /* IEU1 */ + or %o3, %o4, %o3 /* IEU0 Group */ + add %o1, 8, %o1 /* IEU1 */ + sub %o3, %g1, %o4 /* IEU0 Group */ + +#ifdef EIGHTBIT_NOT_RARE + andn %o4, %o3, %o4 /* IEU0 Group */ +#endif + andcc %o4, %g2, %g0 /* IEU1 Group */ + be,a,pt %xcc, 15b /* CTI */ + stx %o3, [%o0 - 8] /* Store */ + srlx %o3, 56, %o4 /* IEU0 Group */ + + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 22f /* CTI */ + srlx %o3, 48, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 21f /* CTI */ + srlx %o3, 40, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 20f /* CTI */ + + srlx %o3, 32, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 19f /* CTI */ + srlx %o3, 24, %o4 /* IEU0 */ + + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 18f /* CTI */ + srlx %o3, 16, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 17f /* CTI */ + srlx %o3, 8, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 16f /* CTI */ + + andcc %o3, 0xff, %g0 /* IEU1 Group */ + bne,pn %icc, 15b /* CTI */ + stx %o3, [%o0 - 8] /* Store */ + retl /* CTI+IEU1 Group */ + + mov %g6, %o0 /* IEU0 */ + + .align 16 +16: srlx %o3, 8, %o4 /* IEU0 Group */ + stb %o4, [%o0 - 2] /* Store */ +17: srlx %o3, 16, %o4 /* IEU0 Group */ + stb %o4, [%o0 - 3] /* Store */ + +18: srlx %o3, 24, %o4 /* IEU0 Group */ + stb %o4, [%o0 - 4] /* Store */ +19: srlx %o3, 32, %o4 /* IEU0 Group */ + stw %o4, [%o0 - 8] /* Store */ + + retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ + nop + nop + +20: srlx %o3, 40, %o4 /* IEU0 Group */ + stb %o4, [%o0 - 6] /* Store */ +21: srlx %o3, 48, %o4 /* IEU0 Group */ + stb %o4, [%o0 - 7] /* Store */ + +22: srlx %o3, 56, %o4 /* IEU0 Group */ + stb %o4, [%o0 - 8] /* Store */ + retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ +END(strcat) +libc_hidden_builtin_def (strcat) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/strchr.S b/REORG.TODO/sysdeps/sparc/sparc64/strchr.S new file mode 100644 index 0000000000..31b9e58d76 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/strchr.S @@ -0,0 +1,482 @@ +/* strchr (str, ch) -- Return pointer to first occurrence of CH in STR. + For SPARC v9. + Copyright (C) 1998-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jan Vondrak <jvon4518@ss1000.ms.mff.cuni.cz> and + Jakub Jelinek <jj@ultra.linux.cz>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <asm/asi.h> +#ifndef XCC +#define XCC xcc +#define USE_BPR + .register %g2, #scratch + .register %g3, #scratch + .register %g6, #scratch +#endif + + /* Normally, this uses + ((xword - 0x0101010101010101) & 0x8080808080808080) test + to find out if any byte in xword could be zero. This is fast, but + also gives false alarm for any byte in range 0x81-0xff. It does + not matter for correctness, as if this test tells us there could + be some zero byte, we check it byte by byte, but if bytes with + high bits set are common in the strings, then this will give poor + performance. You can #define EIGHTBIT_NOT_RARE and the algorithm + will use one tick slower, but more precise test + ((xword - 0x0101010101010101) & (~xword) & 0x8080808080808080), + which does not give any false alarms (but if some bits are set, + one cannot assume from it which bytes are zero and which are not). + It is yet to be measured, what is the correct default for glibc + in these days for an average user. + */ + + .text + .align 32 +ENTRY(strchr) + andcc %o1, 0xff, %o1 /* IEU1 Group */ + be,pn %icc, 17f /* CTI */ + sllx %o1, 8, %g3 /* IEU0 Group */ + sethi %hi(0x01010101), %g1 /* IEU1 */ + + or %g3, %o1, %g3 /* IEU0 Group */ + ldub [%o0], %o3 /* Load */ + sllx %g3, 16, %g5 /* IEU0 Group */ + or %g1, %lo(0x01010101), %g1 /* IEU1 */ + + sllx %g1, 32, %g2 /* IEU0 Group */ + brz,pn %o3, 5f /* CTI+IEU1 */ + orcc %g3, %g5, %g3 /* IEU1 Group */ + sllx %g3, 32, %g5 /* IEU0 */ + + cmp %o3, %o1 /* IEU1 Group */ + be,pn %xcc, 14f /* CTI */ + or %g1, %g2, %g1 /* IEU0 */ + andcc %o0, 7, %g0 /* IEU1 Group */ + + bne,a,pn %icc, 15f /* CTI */ + add %o0, 1, %o0 /* IEU0 */ + ldx [%o0], %o3 /* Load Group */ +1: sllx %g1, 7, %g2 /* IEU0 */ + + or %g3, %g5, %g3 /* IEU1 */ + add %o0, 8, %o0 /* IEU0 Group */ + xor %o3, %g3, %o4 /* IEU1 */ + /* %g1 = 0101010101010101 * + * %g2 = 8080088080808080 * + * %g3 = c c c c c c c c * + * %o3 = value * + * %o4 = value XOR c */ +2: sub %o3, %g1, %o2 /* IEU0 Group */ + + sub %o4, %g1, %o5 /* IEU1 */ +#ifdef EIGHTBIT_NOT_RARE + andn %o2, %o3, %g6 /* IEU0 Group */ + andn %o5, %o4, %o5 /* IEU1 */ + ldxa [%o0] ASI_PNF, %o3 /* Load */ + or %o5, %g6, %o5 /* IEU0 Group */ +#else + ldxa [%o0] ASI_PNF, %o3 /* Load */ + or %o5, %o2, %o5 /* IEU0 Group */ +#endif + add %o0, 8, %o0 /* IEU1 */ + + andcc %o5, %g2, %g0 /* IEU1 Group */ + be,a,pt %xcc, 2b /* CTI */ + xor %o3, %g3, %o4 /* IEU0 */ + srlx %o5, 32, %g5 /* IEU0 Group */ + + add %o2, %g1, %o2 /* IEU1 */ +3: andcc %g5, %g2, %g0 /* IEU1 Group */ + be,pn %xcc, 4f /* CTI */ + srlx %o2, 56, %g5 /* IEU0 */ + + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 5f /* CTI */ + srlx %o4, 56, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 6f /* CTI */ + srlx %o2, 48, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 5f /* CTI */ + + srlx %o4, 48, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 7f /* CTI */ + srlx %o2, 40, %g5 /* IEU0 */ + + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 5f /* CTI */ + srlx %o4, 40, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 8f /* CTI */ + srlx %o2, 32, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 5f /* CTI */ + + srlx %o4, 32, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 9f /* CTI */ +4: srlx %o2, 24, %g5 /* IEU0 */ + + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 5f /* CTI */ + srlx %o4, 24, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 10f /* CTI */ + srlx %o2, 16, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 5f /* CTI */ + + srlx %o4, 16, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 11f /* CTI */ + srlx %o2, 8, %g5 /* IEU0 */ + + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 5f /* CTI */ + srlx %o4, 8, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 12f /* CTI */ + andcc %o2, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 5f /* CTI */ + sub %o3, %g1, %o2 /* IEU0 */ + + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 13f /* CTI */ + xor %o3, %g3, %o4 /* IEU0 */ + ldxa [%o0] ASI_PNF, %o3 /* Load Group */ + + sub %o4, %g1, %o5 /* IEU0 */ + or %o5, %o2, %o5 /* IEU1 */ + add %o0, 8, %o0 /* IEU0 Group */ + andcc %o5, %g2, %g0 /* IEU1 */ + + be,a,pt %xcc, 2b /* CTI */ + xor %o3, %g3, %o4 /* IEU0 Group */ + srlx %o5, 32, %g5 /* IEU0 Group */ + ba,pt %xcc, 3b /* CTI */ + + add %o2, %g1, %o2 /* IEU1 */ + + .align 16 +5: retl /* CTI+IEU1 Group */ + clr %o0 /* IEU0 */ +6: retl /* CTI+IEU1 Group */ + add %o0, -16, %o0 /* IEU0 */ + +7: retl /* CTI+IEU1 Group */ + add %o0, -15, %o0 /* IEU0 */ +8: retl /* CTI+IEU1 Group */ + add %o0, -14, %o0 /* IEU0 */ + +9: retl /* CTI+IEU1 Group */ + add %o0, -13, %o0 /* IEU0 */ +10: retl /* CTI+IEU1 Group */ + add %o0, -12, %o0 /* IEU0 */ + +11: retl /* CTI+IEU1 Group */ + add %o0, -11, %o0 /* IEU0 */ +12: retl /* CTI+IEU1 Group */ + add %o0, -10, %o0 /* IEU0 */ + +13: retl /* CTI+IEU1 Group */ + add %o0, -9, %o0 /* IEU0 */ +14: retl /* CTI+IEU1 Group */ + nop /* IEU0 */ + + .align 16 +15: ldub [%o0], %o3 /* Load Group */ +16: andcc %o0, 7, %g0 /* IEU1 */ + be,a,pn %icc, 1b /* CTI */ + ldx [%o0], %o3 /* Load Group */ + + andcc %o3, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 5b /* CTI */ + add %o0, 1, %o0 /* IEU0 */ + cmp %o3, %o1 /* IEU1 Group */ + + bne,a,pn %icc, 16b /* CTI */ + ldub [%o0], %o3 /* Load */ + retl /* CTI+IEU1 Group */ + add %o0, -1, %o0 /* IEU0 */ + + /* strchr (str, 0) */ + .align 32 + nop + .align 16 +17: sethi %hi(0x01010101), %g1 /* IEU0 Group */ + ldub [%o0], %o3 /* Load */ + or %g1, %lo(0x01010101), %g1 /* IEU0 Group */ + sllx %g1, 32, %g2 /* IEU0 Group */ + + andcc %o0, 7, %g0 /* IEU1 */ + or %g1, %g2, %g1 /* IEU0 Group */ + bne,pn %icc, 32f /* CTI */ + sllx %g1, 7, %g2 /* IEU0 Group */ + + brz,pn %o3, 30f /* CTI+IEU1 */ + ldx [%o0], %o3 /* Load */ +18: add %o0, 8, %o0 /* IEU0 Group */ +19: sub %o3, %g1, %o2 /* IEU0 Group */ + +#ifdef EIGHTBIT_NOT_RARE + andn %o2, %o3, %g6 /* IEU0 Group */ + ldxa [%o0] ASI_PNF, %o3 /* Load */ + andcc %g6, %g2, %g0 /* IEU1 Group */ +#else + ldxa [%o0] ASI_PNF, %o3 /* Load */ + andcc %o2, %g2, %g0 /* IEU1 Group */ +#endif + be,pt %xcc, 19b /* CTI */ + add %o0, 8, %o0 /* IEU0 */ + + addcc %o2, %g1, %g3 /* IEU1 Group */ + srlx %o2, 32, %o2 /* IEU0 */ +20: andcc %o2, %g2, %g0 /* IEU1 Group */ + be,pn %xcc, 21f /* CTI */ + + srlx %g3, 56, %o2 /* IEU0 */ + andcc %o2, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 29f /* CTI */ + srlx %g3, 48, %o2 /* IEU0 */ + + andcc %o2, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 28f /* CTI */ + srlx %g3, 40, %o2 /* IEU0 */ + andcc %o2, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 27f /* CTI */ + srlx %g3, 32, %o2 /* IEU0 */ + andcc %o2, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 26f /* CTI */ + +21: srlx %g3, 24, %o2 /* IEU0 */ + andcc %o2, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 25f /* CTI */ + srlx %g3, 16, %o2 /* IEU0 */ + + andcc %o2, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 24f /* CTI */ + srlx %g3, 8, %o2 /* IEU0 */ + andcc %o2, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 23f /* CTI */ + sub %o3, %g1, %o2 /* IEU0 */ + andcc %g3, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 22f /* CTI */ + + ldxa [%o0] ASI_PNF, %o3 /* Load */ + andcc %o2, %g2, %g0 /* IEU1 Group */ + be,pt %xcc, 19b /* CTI */ + add %o0, 8, %o0 /* IEU0 */ + + addcc %o2, %g1, %g3 /* IEU1 Group */ + ba,pt %xcc, 20b /* CTI */ + srlx %o2, 32, %o2 /* IEU0 */ + + .align 16 +22: retl /* CTI+IEU1 Group */ + add %o0, -9, %o0 /* IEU0 */ +23: retl /* CTI+IEU1 Group */ + add %o0, -10, %o0 /* IEU0 */ + +24: retl /* CTI+IEU1 Group */ + add %o0, -11, %o0 /* IEU0 */ +25: retl /* CTI+IEU1 Group */ + add %o0, -12, %o0 /* IEU0 */ + +26: retl /* CTI+IEU1 Group */ + add %o0, -13, %o0 /* IEU0 */ +27: retl /* CTI+IEU1 Group */ + add %o0, -14, %o0 /* IEU0 */ + +28: retl /* CTI+IEU1 Group */ + add %o0, -15, %o0 /* IEU0 */ +29: retl /* CTI+IEU1 Group */ + add %o0, -16, %o0 /* IEU0 */ + +30: retl /* CTI+IEU1 Group */ + nop /* IEU0 */ + + .align 16 +32: andcc %o0, 7, %g0 /* IEU1 Group */ + be,a,pn %icc, 18b /* CTI */ + ldx [%o0], %o3 /* Load */ + add %o0, 1, %o0 /* IEU0 Group */ + + brnz,a,pt %o3, 32b /* CTI+IEU1 */ + lduba [%o0] ASI_PNF, %o3 /* Load */ + retl /* CTI+IEU1 Group */ + add %o0, -1, %o0 /* IEU0 */ +END(strchr) + + .align 32 +ENTRY(strrchr) + andcc %o1, 0xff, %o1 /* IEU1 Group */ + be,pn %icc, 17b /* CTI */ + clr %g4 /* IEU0 */ + andcc %o0, 7, %g0 /* IEU1 Group */ + + bne,pn %icc, 13f /* CTI */ + sllx %o1, 8, %g3 /* IEU0 */ + ldx [%o0], %o3 /* Load Group */ +1: sethi %hi(0x01010101), %g1 /* IEU0 */ + + or %g3, %o1, %g3 /* IEU1 */ + sllx %g3, 16, %g5 /* IEU0 Group */ + or %g1, %lo(0x01010101), %g1 /* IEU1 */ + sllx %g1, 32, %g2 /* IEU0 Group */ + + or %g3, %g5, %g3 /* IEU1 */ + sllx %g3, 32, %g5 /* IEU0 Group */ + or %g1, %g2, %g1 /* IEU1 */ + sllx %g1, 7, %g2 /* IEU0 Group */ + + or %g3, %g5, %g3 /* IEU1 */ + add %o0, 8, %o0 /* IEU0 Group */ + xor %o3, %g3, %o4 /* IEU1 */ + /* %g1 = 0101010101010101 * + * %g2 = 8080088080808080 * + * %g3 = c c c c c c c c * + * %o3 = value * + * %o4 = value XOR c */ +2: sub %o3, %g1, %o2 /* IEU0 Group */ + +3: sub %o4, %g1, %o5 /* IEU1 */ +#ifdef EIGHTBIT_NOT_RARE + andn %o2, %o3, %g6 /* IEU0 Group */ + andn %o5, %o4, %o5 /* IEU1 */ + ldxa [%o0] ASI_PNF, %o3 /* Load */ + + or %o5, %g6, %o5 /* IEU0 Group */ +#else + ldxa [%o0] ASI_PNF, %o3 /* Load */ + + or %o5, %o2, %o5 /* IEU0 Group */ +#endif + add %o0, 8, %o0 /* IEU1 */ + andcc %o5, %g2, %g0 /* IEU1 Group */ + be,a,pt %xcc, 2b /* CTI */ + + xor %o3, %g3, %o4 /* IEU0 */ + srlx %o5, 32, %g5 /* IEU0 Group */ + add %o2, %g1, %o2 /* IEU1 */ + andcc %g5, %g2, %g0 /* IEU1 Group */ + + be,pn %xcc, 7f /* CTI */ + srlx %o2, 56, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 12f /* CTI */ + + srlx %o4, 56, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + srlx %o2, 48, %g5 /* IEU0 */ + be,a,pn %icc, 4f /* CTI */ + + add %o0, -16, %g4 /* IEU0 Group */ +4: andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 12f /* CTI */ + srlx %o4, 48, %g5 /* IEU0 */ + + andcc %g5, 0xff, %g0 /* IEU1 Group */ + srlx %o2, 40, %g5 /* IEU0 */ + be,a,pn %icc, 5f /* CTI */ + add %o0, -15, %g4 /* IEU0 Group */ + +5: andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 12f /* CTI */ + srlx %o4, 40, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + + srlx %o2, 32, %g5 /* IEU0 */ + be,a,pn %icc, 6f /* CTI */ + add %o0, -14, %g4 /* IEU0 Group */ +6: andcc %g5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 12f /* CTI */ + srlx %o4, 32, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,a,pn %icc, 7f /* CTI */ + + add %o0, -13, %g4 /* IEU0 */ +7: srlx %o2, 24, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 12f /* CTI */ + + srlx %o4, 24, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + srlx %o2, 16, %g5 /* IEU0 */ + be,a,pn %icc, 8f /* CTI */ + + add %o0, -12, %g4 /* IEU0 Group */ +8: andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 12f /* CTI */ + srlx %o4, 16, %g5 /* IEU0 */ + + andcc %g5, 0xff, %g0 /* IEU1 Group */ + srlx %o2, 8, %g5 /* IEU0 */ + be,a,pn %icc, 9f /* CTI */ + add %o0, -11, %g4 /* IEU0 Group */ + +9: andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 12f /* CTI */ + srlx %o4, 8, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + + be,a,pn %icc, 10f /* CTI */ + add %o0, -10, %g4 /* IEU0 */ +10: andcc %o2, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 12f /* CTI */ + + sub %o3, %g1, %o2 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,a,pn %icc, 11f /* CTI */ + add %o0, -9, %g4 /* IEU0 */ + +11: ba,pt %xcc, 3b /* CTI Group */ + xor %o3, %g3, %o4 /* IEU0 Group */ +12: retl /* CTI+IEU1 Group */ + mov %g4, %o0 /* IEU0 */ + + .align 16 +13: ldub [%o0], %o3 /* Load Group */ + add %o0, 1, %o0 /* IEU0 */ +14: andcc %o3, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 12b /* CTI */ + + cmp %o3, %o1 /* IEU1 Group */ + ldub [%o0], %o3 /* Load */ + be,a,pn %icc, 15f /* CTI */ + add %o0, -1, %g4 /* IEU0 Group */ + +15: andcc %o0, 7, %g0 /* IEU1 Group */ + bne,a,pt %icc, 14b /* CTI */ + add %o0, 1, %o0 /* IEU0 */ + ba,pt %xcc, 1b /* CTI Group */ + + ldx [%o0], %o3 /* Load */ +END(strrchr) + +weak_alias (strchr, index) +weak_alias (strrchr, rindex) +libc_hidden_builtin_def (strchr) +libc_hidden_builtin_def (strrchr) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/strcmp.S b/REORG.TODO/sysdeps/sparc/sparc64/strcmp.S new file mode 100644 index 0000000000..d4b0a22f18 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/strcmp.S @@ -0,0 +1,232 @@ +/* Compare two strings for differences. + For SPARC v9. + Copyright (C) 2011-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net> + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <asm/asi.h> + +#ifndef XCC + .register %g2, #scratch + .register %g3, #scratch + .register %g6, #scratch +#endif + +#define rSTR1 %o0 +#define rSTR2 %o1 +#define r0101 %o2 /* 0x0101010101010101 */ +#define r8080 %o3 /* 0x8080808080808080 */ +#define rSTRXOR %o4 +#define rWORD1 %o5 +#define rTMP1 %g1 +#define rTMP2 %g2 +#define rWORD2 %g3 +#define rSLL %g4 +#define rSRL %g5 +#define rBARREL %g6 + + /* There are two cases, either the two pointers are aligned + * identically or they are not. If they have the same + * alignment we can use the normal full speed loop. Otherwise + * we have to use the barrel-shifter version. + */ + + .text + .align 32 +ENTRY(strcmp) + or rSTR2, rSTR1, rTMP1 + sethi %hi(0x80808080), r8080 + + andcc rTMP1, 0x7, %g0 + bne,pn %icc, .Lmaybe_barrel_shift + or r8080, %lo(0x80808080), r8080 + ldx [rSTR1], rWORD1 + + sub rSTR2, rSTR1, rSTR2 + sllx r8080, 32, rTMP1 + + ldx [rSTR1 + rSTR2], rWORD2 + or r8080, rTMP1, r8080 + + ba,pt %xcc, .Laligned_loop_entry + srlx r8080, 7, r0101 + + .align 32 +.Laligned_loop_entry: +.Laligned_loop: + add rSTR1, 8, rSTR1 + + sub rWORD1, r0101, rTMP2 + xorcc rWORD1, rWORD2, rSTRXOR + bne,pn %xcc, .Lcommon_endstring + + andn r8080, rWORD1, rTMP1 + + ldxa [rSTR1] ASI_PNF, rWORD1 + andcc rTMP1, rTMP2, %g0 + be,a,pt %xcc, .Laligned_loop + + ldxa [rSTR1 + rSTR2] ASI_PNF, rWORD2 + +.Lcommon_equal: + retl + mov 0, %o0 + + /* All loops terminate here once they find an unequal word. + * If a zero byte appears in the word before the first unequal + * byte, we must report zero. Otherwise we report '1' or '-1' + * depending upon whether the first mis-matching byte is larger + * in the first string or the second, respectively. + * + * First we compute a 64-bit mask value that has "0x01" in + * each byte where a zero exists in rWORD1. rSTRXOR holds the + * value (rWORD1 ^ rWORD2). Therefore, if considered as an + * unsigned quantity, our "0x01" mask value is "greater than" + * rSTRXOR then a zero terminating byte comes first and + * therefore we report '0'. + * + * The formula for this mask is: + * + * mask_tmp1 = ~rWORD1 & 0x8080808080808080; + * mask_tmp2 = ((rWORD1 & 0x7f7f7f7f7f7f7f7f) + + * 0x7f7f7f7f7f7f7f7f); + * + * mask = ((mask_tmp1 & ~mask_tmp2) >> 7); + */ +.Lcommon_endstring: + andn rWORD1, r8080, rTMP2 + or r8080, 1, %o1 + + mov 1, %o0 + sub rTMP2, %o1, rTMP2 + + cmp rWORD1, rWORD2 + andn rTMP1, rTMP2, rTMP1 + + movleu %xcc, -1, %o0 + srlx rTMP1, 7, rTMP1 + + /* In order not to be influenced by bytes after the zero byte, we + * have to retain only the highest bit in the mask for the comparison + * with rSTRXOR to work properly. + */ + mov 0, rTMP2 + andcc rTMP1, 0x0100, %g0 + + movne %xcc, 8, rTMP2 + sllx rTMP1, 63 - 16, %o1 + + movrlz %o1, 16, rTMP2 + sllx rTMP1, 63 - 24, %o1 + + movrlz %o1, 24, rTMP2 + sllx rTMP1, 63 - 32, %o1 + + movrlz %o1, 32, rTMP2 + sllx rTMP1, 63 - 40, %o1 + + movrlz %o1, 40, rTMP2 + sllx rTMP1, 63 - 48, %o1 + + movrlz %o1, 48, rTMP2 + sllx rTMP1, 63 - 56, %o1 + + movrlz %o1, 56, rTMP2 + + srlx rTMP1, rTMP2, rTMP1 + + sllx rTMP1, rTMP2, rTMP1 + + cmp rTMP1, rSTRXOR + retl + movgu %xcc, 0, %o0 + +.Lmaybe_barrel_shift: + sub rSTR2, rSTR1, rSTR2 + sllx r8080, 32, rTMP1 + + or r8080, rTMP1, r8080 + and rSTR1, 0x7, rTMP2 + + srlx r8080, 7, r0101 + andn rSTR1, 0x7, rSTR1 + + ldxa [rSTR1] ASI_PNF, rWORD1 + andcc rSTR2, 0x7, rSLL + sll rTMP2, 3, rSTRXOR + + bne,pn %icc, .Lneed_barrel_shift + mov -1, rTMP1 + ldxa [rSTR1 + rSTR2] ASI_PNF, rBARREL + + srlx rTMP1, rSTRXOR, rTMP2 + + orn rWORD1, rTMP2, rWORD1 + ba,pt %xcc, .Laligned_loop_entry + orn rBARREL, rTMP2, rWORD2 + +.Lneed_barrel_shift: + sllx rSLL, 3, rSLL + andn rSTR2, 0x7, rSTR2 + + ldxa [rSTR1 + rSTR2] ASI_PNF, rBARREL + mov 64, rTMP2 + sub rTMP2, rSLL, rSRL + + srlx rTMP1, rSTRXOR, rTMP1 + add rSTR2, 8, rSTR2 + + orn rWORD1, rTMP1, rWORD1 + sllx rBARREL, rSLL, rWORD2 + ldxa [rSTR1 + rSTR2] ASI_PNF, rBARREL + + add rSTR1, 8, rSTR1 + sub rWORD1, r0101, rTMP2 + + srlx rBARREL, rSRL, rSTRXOR + + or rWORD2, rSTRXOR, rWORD2 + + orn rWORD2, rTMP1, rWORD2 + ba,pt %xcc, .Lbarrel_shift_loop_entry + andn r8080, rWORD1, rTMP1 + +.Lbarrel_shift_loop: + sllx rBARREL, rSLL, rWORD2 + ldxa [rSTR1 + rSTR2] ASI_PNF, rBARREL + + add rSTR1, 8, rSTR1 + sub rWORD1, r0101, rTMP2 + + srlx rBARREL, rSRL, rSTRXOR + andn r8080, rWORD1, rTMP1 + + or rWORD2, rSTRXOR, rWORD2 + +.Lbarrel_shift_loop_entry: + xorcc rWORD1, rWORD2, rSTRXOR + bne,pn %xcc, .Lcommon_endstring + + andcc rTMP1, rTMP2, %g0 + be,a,pt %xcc, .Lbarrel_shift_loop + ldxa [rSTR1] ASI_PNF, rWORD1 + + retl + mov 0, %o0 +END(strcmp) +libc_hidden_builtin_def (strcmp) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/strcpy.S b/REORG.TODO/sysdeps/sparc/sparc64/strcpy.S new file mode 100644 index 0000000000..8732809f2b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/strcpy.S @@ -0,0 +1,244 @@ +/* Copy SRC to DEST returning DEST. + For SPARC v9. + Copyright (C) 1998-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jan Vondrak <jvon4518@ss1000.ms.mff.cuni.cz> and + Jakub Jelinek <jj@ultra.linux.cz>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <asm/asi.h> +#ifndef XCC + .register %g2, #scratch + .register %g3, #scratch + .register %g6, #scratch +#endif + + /* Normally, this uses + ((xword - 0x0101010101010101) & 0x8080808080808080) test + to find out if any byte in xword could be zero. This is fast, but + also gives false alarm for any byte in range 0x81-0xff. It does + not matter for correctness, as if this test tells us there could + be some zero byte, we check it byte by byte, but if bytes with + high bits set are common in the strings, then this will give poor + performance. You can #define EIGHTBIT_NOT_RARE and the algorithm + will use one tick slower, but more precise test + ((xword - 0x0101010101010101) & (~xword) & 0x8080808080808080), + which does not give any false alarms (but if some bits are set, + one cannot assume from it which bytes are zero and which are not). + It is yet to be measured, what is the correct default for glibc + in these days for an average user. + */ + + .text + .align 32 +ENTRY(strcpy) + sethi %hi(0x01010101), %g1 /* IEU0 Group */ + mov %o0, %g6 /* IEU1 */ + or %g1, %lo(0x01010101), %g1 /* IEU0 Group */ + andcc %o0, 7, %g0 /* IEU1 */ + + sllx %g1, 32, %g2 /* IEU0 Group */ + bne,pn %icc, 12f /* CTI */ + andcc %o1, 7, %g3 /* IEU1 */ + or %g1, %g2, %g1 /* IEU0 Group */ + + bne,pn %icc, 14f /* CTI */ + sllx %g1, 7, %g2 /* IEU0 Group */ +1: ldx [%o1], %o3 /* Load */ + add %o1, 8, %o1 /* IEU1 */ + +2: mov %o3, %g3 /* IEU0 Group */ +3: sub %o3, %g1, %o2 /* IEU1 */ + ldxa [%o1] ASI_PNF, %o3 /* Load */ +#ifdef EIGHTBIT_NOT_RARE + andn %o2, %g3, %o2 /* IEU0 Group */ +#endif + add %o0, 8, %o0 /* IEU0 Group */ + + andcc %o2, %g2, %g0 /* IEU1 */ + add %o1, 8, %o1 /* IEU0 Group */ + be,a,pt %xcc, 2b /* CTI */ + stx %g3, [%o0 - 8] /* Store */ + + srlx %g3, 56, %g5 /* IEU0 Group */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 11f /* CTI */ + srlx %g3, 48, %g4 /* IEU0 */ + + andcc %g4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 10f /* CTI */ + srlx %g3, 40, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 9f /* CTI */ + srlx %g3, 32, %g4 /* IEU0 */ + andcc %g4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 8f /* CTI */ + + srlx %g3, 24, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 7f /* CTI */ + srlx %g3, 16, %g4 /* IEU0 */ + + andcc %g4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 6f /* CTI */ + srlx %g3, 8, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 5f /* CTI */ + sub %o3, %g1, %o2 /* IEU0 */ + stx %g3, [%o0 - 8] /* Store Group */ + andcc %g3, 0xff, %g0 /* IEU1 */ + + bne,pt %icc, 3b /* CTI */ + mov %o3, %g3 /* IEU0 Group */ +4: retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ + + .align 16 +5: stb %g5, [%o0 - 2] /* Store Group */ + srlx %g3, 16, %g4 /* IEU0 */ +6: sth %g4, [%o0 - 4] /* Store Group */ + srlx %g3, 32, %g4 /* IEU0 */ + + stw %g4, [%o0 - 8] /* Store Group */ + retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ +7: stb %g5, [%o0 - 4] /* Store Group */ + + srlx %g3, 32, %g4 /* IEU0 */ +8: stw %g4, [%o0 - 8] /* Store Group */ + retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ + +9: stb %g5, [%o0 - 6] /* Store Group */ + srlx %g3, 48, %g4 /* IEU0 */ +10: sth %g4, [%o0 - 8] /* Store Group */ + retl /* CTI+IEU1 Group */ + + mov %g6, %o0 /* IEU0 */ +11: stb %g5, [%o0 - 8] /* Store Group */ + retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ + +12: or %g1, %g2, %g1 /* IEU0 Group */ + ldub [%o1], %o3 /* Load */ + sllx %g1, 7, %g2 /* IEU0 Group */ + stb %o3, [%o0] /* Store Group */ + +13: add %o0, 1, %o0 /* IEU0 */ + add %o1, 1, %o1 /* IEU1 */ + andcc %o3, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 4b /* CTI */ + + lduba [%o1] ASI_PNF, %o3 /* Load */ + andcc %o0, 7, %g0 /* IEU1 Group */ + bne,a,pt %icc, 13b /* CTI */ + stb %o3, [%o0] /* Store */ + + andcc %o1, 7, %g3 /* IEU1 Group */ + be,a,pt %icc, 1b /* CTI */ + ldx [%o1], %o3 /* Load */ +14: orcc %g0, 64, %g4 /* IEU1 Group */ + + sllx %g3, 3, %g5 /* IEU0 */ + sub %o1, %g3, %o1 /* IEU0 Group */ + sub %g4, %g5, %g4 /* IEU1 */ + /* %g1 = 0101010101010101 * + * %g2 = 8080808080808080 * + * %g3 = source alignment * + * %g5 = number of bits to shift left * + * %g4 = number of bits to shift right */ + ldxa [%o1] ASI_PNF, %o5 /* Load Group */ + + addcc %o1, 8, %o1 /* IEU1 */ +15: sllx %o5, %g5, %o3 /* IEU0 Group */ + ldxa [%o1] ASI_PNF, %o5 /* Load */ + srlx %o5, %g4, %o4 /* IEU0 Group */ + + add %o0, 8, %o0 /* IEU1 */ + or %o3, %o4, %o3 /* IEU0 Group */ + add %o1, 8, %o1 /* IEU1 */ + sub %o3, %g1, %o4 /* IEU0 Group */ + +#ifdef EIGHTBIT_NOT_RARE + andn %o4, %o3, %o4 /* IEU0 Group */ +#endif + andcc %o4, %g2, %g0 /* IEU1 Group */ + be,a,pt %xcc, 15b /* CTI */ + stx %o3, [%o0 - 8] /* Store */ + srlx %o3, 56, %o4 /* IEU0 Group */ + + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 22f /* CTI */ + srlx %o3, 48, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 21f /* CTI */ + srlx %o3, 40, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 20f /* CTI */ + + srlx %o3, 32, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 19f /* CTI */ + srlx %o3, 24, %o4 /* IEU0 */ + + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 18f /* CTI */ + srlx %o3, 16, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 17f /* CTI */ + srlx %o3, 8, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 16f /* CTI */ + + andcc %o3, 0xff, %g0 /* IEU1 Group */ + bne,pn %icc, 15b /* CTI */ + stx %o3, [%o0 - 8] /* Store */ + retl /* CTI+IEU1 Group */ + + mov %g6, %o0 /* IEU0 */ + + .align 16 +16: srlx %o3, 8, %o4 /* IEU0 Group */ + stb %o4, [%o0 - 2] /* Store */ +17: srlx %o3, 16, %o4 /* IEU0 Group */ + stb %o4, [%o0 - 3] /* Store */ + +18: srlx %o3, 24, %o4 /* IEU0 Group */ + stb %o4, [%o0 - 4] /* Store */ +19: srlx %o3, 32, %o4 /* IEU0 Group */ + stw %o4, [%o0 - 8] /* Store */ + + retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ + nop + nop + +20: srlx %o3, 40, %o4 /* IEU0 Group */ + stb %o4, [%o0 - 6] /* Store */ +21: srlx %o3, 48, %o4 /* IEU0 Group */ + stb %o4, [%o0 - 7] /* Store */ + +22: srlx %o3, 56, %o4 /* IEU0 Group */ + stb %o4, [%o0 - 8] /* Store */ + retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ +END(strcpy) +libc_hidden_builtin_def (strcpy) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/strcspn.S b/REORG.TODO/sysdeps/sparc/sparc64/strcspn.S new file mode 100644 index 0000000000..8b448d16e7 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/strcspn.S @@ -0,0 +1,212 @@ +/* strcspn (str, ss) -- Return the length of the initial segment of STR + which contains no characters from SS. + For SPARC v9. + Copyright (C) 1999-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jj@ultra.linux.cz> + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <asm/asi.h> +#ifndef XCC +#define XCC xcc +#define STACK_SIZE 128 +#define STACK_OFFSET 128+0x7ff + .register %g2, #scratch +#else +#define STACK_SIZE 64 +#define STACK_OFFSET 64 +#endif + + .text + .align 32 +ENTRY(strcspn) + sub %sp, STACK_SIZE+32, %sp /* IEU0 Group */ + mov 1, %o4 /* IEU1 */ + stx %o4, [%sp + STACK_OFFSET] /* Store Group */ + mov %o0, %g4 /* IEU0 */ + + stx %g0, [%sp + STACK_OFFSET + 8] /* Store Group */ + add %sp, STACK_OFFSET, %o5 /* IEU0 */ + stx %g0, [%sp + STACK_OFFSET + 16] /* Store Group */ + stx %g0, [%sp + STACK_OFFSET + 24] /* Store Group */ + +1: ldub [%o1], %o2 /* Load Group */ + brz,pn %o2, 2f /* CTI+IEU1 Group */ + srl %o2, 3, %o3 /* IEU0 */ + and %o3, 0x18, %o3 /* IEU0 Group */ + + and %o2, 0x3f, %o2 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + sllx %o4, %o2, %g1 /* IEU0 */ + add %o1, 1, %o1 /* IEU1 */ + + or %g2, %g1, %g2 /* IEU0 Group */ + ba,pt %xcc, 1b /* CTI */ + stx %g2, [%o5 + %o3] /* Store */ +2: andcc %o0, 7, %g0 /* IEU1 Group */ + + be,a,pt %xcc, 4f /* CTI */ + ldx [%o0], %o2 /* Load */ + ldub [%o0], %o2 /* Load Group */ +3: srl %o2, 3, %o3 /* IEU0 Group */ + + and %o2, 0x3f, %o2 /* IEU1 */ + and %o3, 0x18, %o3 /* IEU0 Group */ + ldx [%o5 + %o3], %g2 /* Load Group */ + sllx %o4, %o2, %g1 /* IEU0 */ + + add %o0, 1, %o0 /* IEU1 */ + andcc %g2, %g1, %g0 /* IEU1 Group */ + bne,pn %xcc, 12f /* CTI */ + andcc %o0, 7, %g0 /* IEU1 Group */ + + bne,a,pt %icc, 3b /* CTI */ + ldub [%o0], %o2 /* Load */ + ldx [%o0], %o2 /* Load Group */ +4: srlx %o2, 59, %o3 /* IEU0 Group */ + + srlx %o2, 56, %g5 /* IEU0 Group */ +5: and %o3, 0x18, %o3 /* IEU1 */ + andcc %g5, 0x3f, %g5 /* IEU1 Group */ + ldx [%o5 + %o3], %g2 /* Load */ + + srlx %o2, 51, %o3 /* IEU0 */ + sllx %o4, %g5, %g1 /* IEU0 Group */ + srlx %o2, 48, %g5 /* IEU0 Group */ + andcc %g2, %g1, %g2 /* IEU1 */ + + bne,pn %xcc, 13f /* CTI */ + and %o3, 0x18, %o3 /* IEU0 Group */ + and %g5, 0x3f, %g5 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + + srlx %o2, 43, %o3 /* IEU0 */ + sllx %o4, %g5, %g1 /* IEU0 Group */ + srlx %o2, 40, %g5 /* IEU0 Group */ + andcc %g2, %g1, %g2 /* IEU1 */ + + bne,pn %xcc, 14f /* CTI */ + and %o3, 0x18, %o3 /* IEU0 Group */ + and %g5, 0x3f, %g5 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + + srlx %o2, 35, %o3 /* IEU0 */ + sllx %o4, %g5, %g1 /* IEU0 Group */ + srlx %o2, 32, %g5 /* IEU0 Group */ + andcc %g2, %g1, %g2 /* IEU1 */ + + bne,pn %xcc, 15f /* CTI */ + and %o3, 0x18, %o3 /* IEU0 Group */ + and %g5, 0x3f, %g5 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + + srlx %o2, 27, %o3 /* IEU0 */ + sllx %o4, %g5, %g1 /* IEU0 Group */ + srlx %o2, 24, %g5 /* IEU0 Group */ + andcc %g2, %g1, %g2 /* IEU1 */ + + bne,pn %xcc, 16f /* CTI */ + and %o3, 0x18, %o3 /* IEU0 Group */ + and %g5, 0x3f, %g5 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + + srlx %o2, 19, %o3 /* IEU0 */ + sllx %o4, %g5, %g1 /* IEU0 Group */ + srlx %o2, 16, %g5 /* IEU0 Group */ + andcc %g2, %g1, %g2 /* IEU1 */ + + bne,pn %xcc, 17f /* CTI */ + and %o3, 0x18, %o3 /* IEU0 Group */ + and %g5, 0x3f, %g5 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + + srlx %o2, 11, %o3 /* IEU0 */ + sllx %o4, %g5, %g1 /* IEU0 Group */ + add %o0, 8, %o0 /* IEU1 */ + srlx %o2, 8, %g5 /* IEU0 Group */ + + andcc %g2, %g1, %g2 /* IEU1 */ + bne,pn %xcc, 18f /* CTI */ + and %o3, 0x18, %o3 /* IEU0 Group */ + and %g5, 0x3f, %g5 /* IEU1 */ + + ldx [%o5 + %o3], %g2 /* Load Group */ + sllx %o4, %g5, %g1 /* IEU0 */ + mov %o2, %g5 /* IEU1 */ + srlx %o2, 3, %o3 /* IEU0 Group */ + + ldxa [%o0] ASI_PNF, %o2 /* Load */ + andcc %g2, %g1, %g2 /* IEU1 Group */ + bne,pn %xcc, 19f /* CTI */ + and %o3, 0x18, %o3 /* IEU0 Group */ + + and %g5, 0x3f, %g5 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + sllx %o4, %g5, %g1 /* IEU0 */ + srlx %o2, 59, %o3 /* IEU0 Group */ + + andcc %g2, %g1, %g2 /* IEU1 Group */ + be,pt %xcc, 5b /* CTI */ + srlx %o2, 56, %g5 /* IEU0 Group */ + sub %o0, 1, %o0 /* IEU1 */ + + add %sp, STACK_SIZE+32, %sp /* IEU0 Group */ + retl /* CTI+IEU1 Group */ + sub %o0, %g4, %o0 /* IEU0 */ + + .align 16 +19: sub %o0, 2, %o0 /* IEU1 */ + add %sp, STACK_SIZE+32, %sp /* IEU0 Group */ + retl /* CTI+IEU1 Group */ + sub %o0, %g4, %o0 /* IEU0 */ + +18: sub %o0, 3, %o0 /* IEU1 */ + add %sp, STACK_SIZE+32, %sp /* IEU0 Group */ + retl /* CTI+IEU1 Group */ + sub %o0, %g4, %o0 /* IEU0 */ + +17: add %o0, 4, %o0 /* IEU1 */ + add %sp, STACK_SIZE+32, %sp /* IEU0 Group */ + retl /* CTI+IEU1 Group */ + sub %o0, %g4, %o0 /* IEU0 */ + +16: add %o0, 3, %o0 /* IEU1 */ + add %sp, STACK_SIZE+32, %sp /* IEU0 Group */ + retl /* CTI+IEU1 Group */ + sub %o0, %g4, %o0 /* IEU0 */ + +15: add %o0, 2, %o0 /* IEU1 */ + add %sp, STACK_SIZE+32, %sp /* IEU0 Group */ + retl /* CTI+IEU1 Group */ + sub %o0, %g4, %o0 /* IEU0 */ + +14: add %o0, 1, %o0 /* IEU1 */ + add %sp, STACK_SIZE+32, %sp /* IEU0 Group */ + retl /* CTI+IEU1 Group */ + sub %o0, %g4, %o0 /* IEU0 */ + +13: add %sp, STACK_SIZE+32, %sp /* IEU1 */ + retl /* CTI+IEU1 Group */ + sub %o0, %g4, %o0 /* IEU0 */ + + .align 16 +12: sub %o0, 1, %o0 /* IEU0 Group */ + add %sp, STACK_SIZE+32, %sp /* IEU1 */ + retl /* CTI+IEU1 Group */ + sub %o0, %g4, %o0 /* IEU0 */ +END(strcspn) +libc_hidden_builtin_def (strcspn) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/strlen.S b/REORG.TODO/sysdeps/sparc/sparc64/strlen.S new file mode 100644 index 0000000000..25a63df03a --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/strlen.S @@ -0,0 +1,85 @@ +/* Determine the length of a string. For SPARC v9. + Copyright (C) 1998-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jan Vondrak <jvon4518@ss1000.ms.mff.cuni.cz>, + Jakub Jelinek <jj@ultra.linux.cz>, and + David S. Miller <davem@davemloft.net>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + .register %g2, #scratch + .register %g3, #scratch + + .text + .align 32 +ENTRY(strlen) + mov %o0, %o1 + andn %o0, 0x7, %o0 + + ldx [%o0], %o5 + and %o1, 0x7, %g1 + mov -1, %g5 + + sethi %hi(0x01010101), %o2 + sll %g1, 3, %g1 + + or %o2, %lo(0x01010101), %o2 + srlx %g5, %g1, %o3 + + sllx %o2, 32, %g1 + sethi %hi(0x0000ff00), %g5 + + orn %o5, %o3, %o5 + or %o2, %g1, %o2 + + sllx %o2, 7, %o3 +10: add %o0, 8, %o0 + + andn %o3, %o5, %g1 + sub %o5, %o2, %g2 + + andcc %g1, %g2, %g0 + be,a,pt %xcc, 10b + ldx [%o0], %o5 + srlx %o5, 32, %g1 + + andn %o3, %g1, %o4 + sub %g1, %o2, %g2 + + add %o0, 4, %g3 + andcc %o4, %g2, %g0 + movne %icc, %g1, %o5 + + move %icc, %g3, %o0 + or %g5, %lo(0x0000ff00), %g5 + mov 3 - 8, %g2 + + andcc %o5, %g5, %g0 + srlx %o5, 16, %g1 + move %icc, 2 - 8, %g2 + + andcc %g1, 0xff, %g0 + srl %o5, 24, %o5 + move %icc, 1 - 8, %g2 + + movrz %o5, 0 - 8, %g2 + sub %o0, %o1, %o0 + + retl + add %o0, %g2, %o0 +END(strlen) +libc_hidden_builtin_def (strlen) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/strncmp.S b/REORG.TODO/sysdeps/sparc/sparc64/strncmp.S new file mode 100644 index 0000000000..f0af16155b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/strncmp.S @@ -0,0 +1,363 @@ +/* Compare no more than N characters of S1 and S2, returning less than, + equal to or greater than zero if S1 is lexicographically less than, + equal to or greater than S2. + For SPARC v9. + Copyright (C) 1997-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jan Vondrak <jvon4518@ss1000.ms.mff.cuni.cz> and + Jakub Jelinek <jj@ultra.linux.cz>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <asm/asi.h> +#ifndef XCC +#define XCC xcc +#define USE_BPR + .register %g2, #scratch + .register %g3, #scratch + .register %g6, #scratch +#endif + + /* Normally, this uses + ((xword - 0x0101010101010101) & 0x8080808080808080) test + to find out if any byte in xword could be zero. This is fast, but + also gives false alarm for any byte in range 0x81-0xff. It does + not matter for correctness, as if this test tells us there could + be some zero byte, we check it byte by byte, but if bytes with + high bits set are common in the strings, then this will give poor + performance. You can #define EIGHTBIT_NOT_RARE and the algorithm + will use one tick slower, but more precise test + ((xword - 0x0101010101010101) & (~xword) & 0x8080808080808080), + which does not give any false alarms (but if some bits are set, + one cannot assume from it which bytes are zero and which are not). + It is yet to be measured, what is the correct default for glibc + in these days for an average user. + */ + + .text + .align 32 +ENTRY(strncmp) +#ifdef USE_BPR + brz,pn %o2, 4f /* CTI+IEU1 Group */ +#else + tst %o2 /* IEU1 Group */ + be,pn %XCC, 4f /* CTI */ +#endif + sethi %hi(0x1010101), %g1 /* IEU0 */ + andcc %o0, 7, %g0 /* IEU1 Group */ + bne,pn %icc, 9f /* CTI */ + + or %g1, %lo(0x1010101), %g1 /* IEU0 */ + andcc %o1, 7, %g3 /* IEU1 Group */ + bne,pn %icc, 11f /* CTI */ + sllx %g1, 32, %g2 /* IEU0 */ + + ldx [%o0], %g4 /* Load Group */ + or %g1, %g2, %g1 /* IEU0 */ +1: ldx [%o1], %o3 /* Load Group */ + sllx %g1, 7, %g2 /* IEU0 */ + + add %o0, 8, %o0 /* IEU1 */ +2: subcc %o2, 8, %o2 /* IEU1 Group */ + bcs,pn %XCC, 5f /* CTI */ + add %o1, 8, %o1 /* IEU0 */ + + sub %g4, %g1, %g3 /* IEU0 Group */ + subcc %g4, %o3, %o4 /* IEU1 */ +#ifdef EIGHTBIT_NOT_RARE + andn %g3, %g4, %g6 /* IEU0 Group */ +#endif + bne,pn %xcc, 6f /* CTI */ + ldxa [%o0] ASI_PNF, %g4 /* Load Group */ + + add %o0, 8, %o0 /* IEU0 */ +#ifdef EIGHTBIT_NOT_RARE + andcc %g6, %g2, %g0 /* IEU1 */ +#else + andcc %g3, %g2, %g0 /* IEU1 */ +#endif + be,a,pt %xcc, 2b /* CTI */ + ldxa [%o1] ASI_PNF, %o3 /* Load Group */ + + addcc %g3, %g1, %o4 /* IEU1 */ +#ifdef EIGHTBIT_NOT_RARE + srlx %g6, 32, %g6 /* IEU0 */ + andcc %g6, %g2, %g0 /* IEU1 Group */ +#else + srlx %g3, 32, %g3 /* IEU0 */ + andcc %g3, %g2, %g0 /* IEU1 Group */ +#endif + be,pt %xcc, 3f /* CTI */ + + srlx %o4, 56, %o5 /* IEU0 */ + andcc %o5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 4f /* CTI */ + srlx %o4, 48, %o5 /* IEU0 */ + + andcc %o5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 4f /* CTI */ + srlx %o4, 40, %o5 /* IEU0 */ + andcc %o5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 4f /* CTI */ + srlx %o4, 32, %o5 /* IEU0 */ + andcc %o5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 4f /* CTI */ + +3: srlx %o4, 24, %o5 /* IEU0 */ + andcc %o5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 4f /* CTI */ + srlx %o4, 16, %o5 /* IEU0 */ + + andcc %o5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 4f /* CTI */ + srlx %o4, 8, %o5 /* IEU0 */ + andcc %o5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 4f /* CTI */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + bne,a,pn %icc, 2b /* CTI */ + ldxa [%o1] ASI_PNF, %o3 /* Load */ + +4: retl /* CTI+IEU1 Group */ + clr %o0 /* IEU0 */ + + .align 16 +5: srlx %g4, 56, %o4 /* IEU0 Group */ + cmp %o2, -8 /* IEU1 */ + be,pn %XCC, 4b /* CTI */ + srlx %o3, 56, %o5 /* IEU0 Group */ + + andcc %o4, 0xff, %g0 /* IEU1 */ + be,pn %xcc, 8f /* CTI */ + subcc %o4, %o5, %o4 /* IEU1 Group */ + bne,pn %xcc, 8f /* CTI */ + + srlx %o3, 48, %o5 /* IEU0 */ + cmp %o2, -7 /* IEU1 Group */ + be,pn %XCC, 4b /* CTI */ + srlx %g4, 48, %o4 /* IEU0 */ + + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %xcc, 8f /* CTI */ + subcc %o4, %o5, %o4 /* IEU1 Group */ + bne,pn %xcc, 8f /* CTI */ + + srlx %o3, 40, %o5 /* IEU0 */ + cmp %o2, -6 /* IEU1 Group */ + be,pn %XCC, 4b /* CTI */ + srlx %g4, 40, %o4 /* IEU0 */ + + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %xcc, 8f /* CTI */ + subcc %o4, %o5, %o4 /* IEU1 Group */ + bne,pn %xcc, 8f /* CTI */ + + srlx %o3, 32, %o5 /* IEU0 */ + cmp %o2, -5 /* IEU1 Group */ + be,pn %XCC, 4b /* CTI */ + srlx %g4, 32, %o4 /* IEU0 */ + + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %xcc, 8f /* CTI */ + subcc %o4, %o5, %o4 /* IEU1 Group */ + bne,pn %xcc, 8f /* CTI */ + + srlx %o3, 24, %o5 /* IEU0 */ + cmp %o2, -4 /* IEU1 Group */ + be,pn %XCC, 4b /* CTI */ + srlx %g4, 24, %o4 /* IEU0 */ + + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %xcc, 8f /* CTI */ + subcc %o4, %o5, %o4 /* IEU1 Group */ + bne,pn %xcc, 8f /* CTI */ + + srlx %o3, 16, %o5 /* IEU0 */ + cmp %o2, -3 /* IEU1 Group */ + be,pn %XCC, 4b /* CTI */ + srlx %g4, 16, %o4 /* IEU0 */ + + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %xcc, 8f /* CTI */ + subcc %o4, %o5, %o4 /* IEU1 Group */ + bne,pn %xcc, 8f /* CTI */ + + srlx %o3, 8, %o5 /* IEU0 */ + cmp %o2, -2 /* IEU1 Group */ + be,pn %XCC, 4b /* CTI */ + srlx %g4, 8, %o4 /* IEU0 */ + + retl /* CTI+IEU1 Group */ + sub %o4, %o5, %o0 /* IEU0 */ +6: addcc %o3, %o4, %g4 /* IEU1 */ +7: srlx %o3, 56, %o5 /* IEU0 */ + + srlx %g4, 56, %o4 /* IEU0 Group */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %xcc, 8f /* CTI */ + subcc %o4, %o5, %o4 /* IEU1 Group */ + + bne,pn %xcc, 8f /* CTI */ + srlx %o3, 48, %o5 /* IEU0 */ + srlx %g4, 48, %o4 /* IEU0 Group */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + + be,pn %xcc, 8f /* CTI */ + subcc %o4, %o5, %o4 /* IEU1 Group */ + bne,pn %xcc, 8f /* CTI */ + srlx %o3, 40, %o5 /* IEU0 */ + + srlx %g4, 40, %o4 /* IEU0 Group */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %xcc, 8f /* CTI */ + subcc %o4, %o5, %o4 /* IEU1 Group */ + + bne,pn %xcc, 8f /* CTI */ + srlx %o3, 32, %o5 /* IEU0 */ + srlx %g4, 32, %o4 /* IEU0 Group */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + + be,pn %xcc, 8f /* CTI */ + subcc %o4, %o5, %o4 /* IEU1 Group */ + bne,pn %xcc, 8f /* CTI */ + srlx %o3, 24, %o5 /* IEU0 */ + + srlx %g4, 24, %o4 /* IEU0 Group */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %xcc, 8f /* CTI */ + subcc %o4, %o5, %o4 /* IEU1 Group */ + + bne,pn %xcc, 8f /* CTI */ + srlx %o3, 16, %o5 /* IEU0 */ + srlx %g4, 16, %o4 /* IEU0 Group */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + + be,pn %xcc, 8f /* CTI */ + subcc %o4, %o5, %o4 /* IEU1 Group */ + bne,pn %xcc, 8f /* CTI */ + srlx %o3, 8, %o5 /* IEU0 */ + + srlx %g4, 8, %o4 /* IEU0 Group */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %xcc, 8f /* CTI */ + subcc %o4, %o5, %o4 /* IEU1 Group */ + + retl /* CTI+IEU1 Group */ + sub %g4, %o3, %o0 /* IEU0 */ +8: retl /* CTI+IEU1 Group */ + mov %o4, %o0 /* IEU0 */ + +9: ldub [%o0], %g4 /* Load Group */ + add %o0, 1, %o0 /* IEU0 */ + ldub [%o1], %o3 /* Load Group */ + sllx %g1, 32, %g2 /* IEU0 */ + +10: subcc %o2, 1, %o2 /* IEU1 Group */ + be,pn %XCC, 8b /* CTI */ + sub %g4, %o3, %o4 /* IEU0 */ + add %o1, 1, %o1 /* IEU0 Group */ + + cmp %g4, %o3 /* IEU1 */ + bne,pn %xcc, 8b /* CTI */ + lduba [%o0] ASI_PNF, %g4 /* Load Group */ + andcc %o3, 0xff, %g0 /* IEU1 */ + + be,pn %icc, 4b /* CTI */ + lduba [%o1] ASI_PNF, %o3 /* Load Group */ + andcc %o0, 7, %g0 /* IEU1 */ + bne,a,pn %icc, 10b /* CTI */ + + add %o0, 1, %o0 /* IEU0 Group */ + or %g1, %g2, %g1 /* IEU1 */ + andcc %o1, 7, %g3 /* IEU1 Group */ + be,pn %icc, 1b /* CTI */ + + ldxa [%o0] ASI_PNF, %g4 /* Load */ +11: sllx %g3, 3, %g5 /* IEU0 Group */ + mov 64, %g6 /* IEU1 */ + or %g1, %g2, %g1 /* IEU0 Group */ + sub %o1, %g3, %o1 /* IEU1 */ + + sub %g6, %g5, %g6 /* IEU0 Group */ + ldxa [%o1] ASI_PNF, %o4 /* Load */ + sllx %g1, 7, %g2 /* IEU1 */ + add %o1, 8, %o1 /* IEU0 Group */ + /* %g1 = 0101010101010101 + %g2 = 8080808080808080 + %g3 = %o1 alignment + %g5 = number of bits to shift left + %g6 = number of bits to shift right */ + +12: sllx %o4, %g5, %o3 /* IEU0 Group */ + ldxa [%o1] ASI_PNF, %o4 /* Load */ + add %o1, 8, %o1 /* IEU1 */ +13: ldxa [%o0] ASI_PNF, %g4 /* Load Group */ + + addcc %o0, 8, %o0 /* IEU1 */ + srlx %o4, %g6, %o5 /* IEU0 */ + subcc %o2, 8, %o2 /* IEU1 Group */ + bcs,pn %XCC, 5b /* CTI */ + + or %o3, %o5, %o3 /* IEU0 */ + cmp %g4, %o3 /* IEU1 Group */ + bne,pn %xcc, 7b /* CTI */ + sub %g4, %g1, %o5 /* IEU0 */ + +#ifdef EIGHTBIT_NOT_RARE + andn %o5, %g4, %o5 /* IEU0 Group */ +#endif + andcc %o5, %g2, %g0 /* IEU1 Group */ + be,pt %xcc, 12b /* CTI */ + srlx %o5, 32, %o5 /* IEU0 */ + andcc %o5, %g2, %g0 /* IEU1 Group */ + + be,pt %xcc, 14f /* CTI */ + srlx %g4, 56, %o5 /* IEU0 */ + andcc %o5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 4b /* CTI */ + + srlx %g4, 48, %o5 /* IEU0 */ + andcc %o5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 4b /* CTI */ + srlx %g4, 40, %o5 /* IEU0 */ + + andcc %o5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 4b /* CTI */ + srlx %g4, 32, %o5 /* IEU0 */ + andcc %o5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 4b /* CTI */ +14: srlx %g4, 24, %o5 /* IEU0 */ + andcc %o5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 4b /* CTI */ + + srlx %g4, 16, %o5 /* IEU0 */ + andcc %o5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 4b /* CTI */ + srlx %g4, 8, %o5 /* IEU0 */ + + andcc %o5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 4b /* CTI */ + andcc %g4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 4b /* CTI */ + + sllx %o4, %g5, %o3 /* IEU0 */ + ldxa [%o1] ASI_PNF, %o4 /* Load Group */ + ba,pt %xcc, 13b /* CTI */ + add %o1, 8, %o1 /* IEU0 */ +END(strncmp) +libc_hidden_builtin_def (strncmp) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/strncpy.S b/REORG.TODO/sysdeps/sparc/sparc64/strncpy.S new file mode 100644 index 0000000000..f8c801f552 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/strncpy.S @@ -0,0 +1,396 @@ +/* strncpy(DST, SRC, COUNT) - Copy no more than COUNT bytes of the + null-terminated string from SRC to DST. If SRC does not cover all of + COUNT, the balance is zeroed. + For SPARC v9. + Copyright (C) 1998-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jan Vondrak <jvon4518@ss1000.ms.mff.cuni.cz> and + Jakub Jelinek <jj@ultra.linux.cz>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <asm/asi.h> +#ifndef XCC +#define XCC xcc +#define USE_BPR + .register %g2, #scratch + .register %g3, #scratch + .register %g6, #scratch +#endif + + /* Normally, this uses + ((xword - 0x0101010101010101) & 0x8080808080808080) test + to find out if any byte in xword could be zero. This is fast, but + also gives false alarm for any byte in range 0x81-0xff. It does + not matter for correctness, as if this test tells us there could + be some zero byte, we check it byte by byte, but if bytes with + high bits set are common in the strings, then this will give poor + performance. You can #define EIGHTBIT_NOT_RARE and the algorithm + will use one tick slower, but more precise test + ((xword - 0x0101010101010101) & (~xword) & 0x8080808080808080), + which does not give any false alarms (but if some bits are set, + one cannot assume from it which bytes are zero and which are not). + It is yet to be measured, what is the correct default for glibc + in these days for an average user. + */ + + .text + .align 32 +ENTRY(strncpy) + sethi %hi(0x01010101), %g1 /* IEU0 Group */ +#ifdef USE_BPR + brz,pn %o2, 19f /* CTI+IEU1 */ +#else + tst %o2 /* IEU1 */ + be,pn %XCC, 19f /* CTI */ +#endif + mov %o0, %g6 /* IEU0 Group */ + or %g1, %lo(0x01010101), %g1 /* IEU1 */ + + andcc %o0, 7, %g0 /* IEU1 Group */ + sllx %g1, 32, %g2 /* IEU0 */ + bne,pn %icc, 26f /* CTI */ + or %g1, %g2, %g1 /* IEU0 Group */ + + andcc %o1, 7, %g3 /* IEU1 */ + bne,pn %icc, 28f /* CTI */ + sllx %g1, 7, %g2 /* IEU0 Group */ + ldx [%o1], %o3 /* Load */ + +1: add %o1, 8, %o1 /* IEU1 */ +2: subcc %o2, 8, %o2 /* IEU1 Group */ + bl,pn %XCC, 18f /* CTI */ + sub %o3, %g1, %o4 /* IEU0 */ + + add %o0, 8, %o0 /* IEU0 Group */ +#ifdef EIGHTBIT_NOT_MORE + andn %o4, %o3, %o4 /* IEU1 */ +#endif + mov %o3, %g3 /* IEU1 */ + ldxa [%o1] ASI_PNF, %o3 /* Load */ + add %o1, 8, %o1 /* IEU0 Group */ + + andcc %o4, %g2, %g0 /* IEU1 */ + be,a,pt %xcc, 2b /* CTI */ + stx %g3, [%o0-8] /* Store Group */ + srlx %g3, 56, %g5 /* IEU0 Group */ + + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 16f /* CTI */ + srlx %g3, 48, %g4 /* IEU0 */ + andcc %g4, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 15f /* CTI */ + srlx %g3, 40, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 14f /* CTI */ + + srlx %g3, 32, %g4 /* IEU0 */ + andcc %g4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 13f /* CTI */ + srlx %g3, 24, %g5 /* IEU0 */ + + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 12f /* CTI */ + srlx %g3, 16, %g4 /* IEU0 */ + andcc %g4, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 11f /* CTI */ + srlx %g3, 8, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 10f /* CTI */ + + andcc %g3, 0xff, %g0 /* IEU1 Group */ + bne,pt %icc, 2b /* CTI */ +3: stx %g3, [%o0-8] /* Store */ + andncc %o2, 31, %g3 /* IEU1 Group */ + +4: be,pn %XCC, 41f /* CTI */ + and %o2, 31, %o2 /* IEU1 Group */ +40: stx %g0, [%o0] /* Store */ + stx %g0, [%o0 + 8] /* Store Group */ + + subcc %g3, 32, %g3 /* IEU1 */ + stx %g0, [%o0 + 16] /* Store Group */ + stx %g0, [%o0 + 24] /* Store Group */ + bne,pt %XCC, 40b /* CTI */ + + add %o0, 32, %o0 /* IEU0 */ +41: subcc %o2, 8, %o2 /* IEU1 Group */ + bl,a,pn %XCC, 6f /* CTI */ + andcc %o2, 4, %g0 /* IEU1 Group */ + +5: stx %g0, [%o0] /* Store */ + subcc %o2, 8, %o2 /* IEU1 Group */ + bge,pt %XCC, 5b /* CTI */ + add %o0, 8, %o0 /* IEU0 */ + + andcc %o2, 4, %g0 /* IEU1 Group */ +6: be,a,pn %icc, 7f /* CTI */ + andcc %o2, 2, %g0 /* IEU1 Group */ + stw %g0, [%o0] /* Store */ + + add %o0, 4, %o0 /* IEU0 */ + andcc %o2, 2, %g0 /* IEU1 Group */ +7: be,a,pn %icc, 8f /* CTI */ + andcc %o2, 1, %g0 /* IEU1 Group */ + + sth %g0, [%o0] /* Store */ + add %o0, 2, %o0 /* IEU0 */ + andcc %o2, 1, %g0 /* IEU1 Group */ +8: bne,a,pn %icc, 9f /* CTI */ + + stb %g0, [%o0] /* Store */ +9: retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ + + .align 16 +10: ba,pt %xcc, 3b /* CTI */ + sllx %g5, 8, %g3 /* IEU0 */ +11: ba,pt %xcc, 3b /* CTI Group */ + sllx %g4, 16, %g3 /* IEU0 */ + +12: ba,pt %xcc, 3b /* CTI Group */ + sllx %g5, 24, %g3 /* IEU0 */ +13: ba,pt %xcc, 3b /* CTI Group */ + sllx %g4, 32, %g3 /* IEU0 */ + +14: ba,pt %xcc, 3b /* CTI Group */ + sllx %g5, 40, %g3 /* IEU0 */ +15: ba,pt %xcc, 3b /* CTI Group */ + sllx %g4, 48, %g3 /* IEU0 */ + +16: ba,pt %xcc, 3b /* CTI */ + sllx %g5, 56, %g3 /* IEU0 */ +17: or %o3, %o4, %o3 /* IEU0 Group */ + sub %o3, %g1, %o4 /* IEU1 */ + +18: addcc %o2, 8, %o2 /* IEU1 Group */ + be,pn %XCC, 19f /* CTI */ + andcc %o4, %g2, %g0 /* IEU1 Group */ + be,pt %xcc, 21f /* CTI */ + + srlx %o3, 56, %g5 /* IEU0 */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 20f /* CTI */ + stb %g5, [%o0] /* Store */ + + add %o0, 1, %o0 /* IEU0 Group */ + subcc %o2, 1, %o2 /* IEU1 */ + be,pn %XCC, 19f /* CTI */ + srlx %o3, 48, %g5 /* IEU0 Group */ + + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 20f /* CTI */ + stb %g5, [%o0] /* Store */ + add %o0, 1, %o0 /* IEU0 Group */ + + subcc %o2, 1, %o2 /* IEU1 */ + be,pn %XCC, 19f /* CTI */ + srlx %o3, 40, %g5 /* IEU0 Group */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 20f /* CTI */ + stb %g5, [%o0] /* Store */ + add %o0, 1, %o0 /* IEU0 Group */ + subcc %o2, 1, %o2 /* IEU1 */ + + be,pn %XCC, 19f /* CTI */ + srlx %o3, 32, %g5 /* IEU0 Group */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 20f /* CTI */ + + stb %g5, [%o0] /* Store */ + add %o0, 1, %o0 /* IEU0 Group */ + subcc %o2, 1, %o2 /* IEU1 */ + be,pn %XCC, 19f /* CTI */ + + srlx %o3, 24, %g5 /* IEU0 Group */ + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 20f /* CTI */ + stb %g5, [%o0] /* Store */ + + add %o0, 1, %o0 /* IEU0 Group */ + subcc %o2, 1, %o2 /* IEU1 */ + be,pn %XCC, 19f /* CTI */ + srlx %o3, 16, %g5 /* IEU0 Group */ + + andcc %g5, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 20f /* CTI */ + stb %g5, [%o0] /* Store */ + add %o0, 1, %o0 /* IEU0 Group */ + + subcc %o2, 1, %o2 /* IEU1 */ + be,pn %XCC, 19f /* CTI */ + srlx %o3, 8, %g5 /* IEU0 Group */ + stb %g5, [%o0] /* Store */ + +19: retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ +50: stb %g0, [%o0] /* Store Group */ +20: subcc %o2, 1, %o2 /* IEU1 Group */ + + bne,pt %XCC, 50b /* CTI */ + add %o0, 1, %o0 /* IEU0 */ + retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ + +21: andcc %o2, 4, %g0 /* IEU1 Group */ + be,pn %icc, 22f /* CTI */ + srlx %o3, 32, %g5 /* IEU0 */ + stw %g5, [%o0] /* Store Group */ + + add %o0, 4, %o0 /* IEU0 */ + mov %o3, %g5 /* IEU1 */ +22: andcc %o2, 2, %g0 /* IEU1 Group */ + be,pn %icc, 23f /* CTI */ + + srlx %g5, 16, %g4 /* IEU0 */ + sth %g4, [%o0] /* Store Group */ + add %o0, 2, %o0 /* IEU0 */ + mov %g5, %g4 /* IEU1 */ + +23: srlx %g4, 8, %g4 /* IEU0 Group */ + andcc %o2, 1, %g0 /* IEU1 */ + bne,a,pn %icc, 24f /* CTI */ + stb %g4, [%o0] /* Store Group */ + +24: retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ +25: andcc %o0, 7, %g0 /* IEU1 Group */ + be,a,pn %icc, 4b /* CTI */ + + andncc %o2, 31, %g3 /* IEU1 Group */ + stb %g0, [%o0] /* Store Group */ + subcc %o2, 1, %o2 /* IEU1 */ + bne,pt %XCC, 25b /* CTI */ + + add %o0, 1, %o0 /* IEU0 Group */ + retl /* CTI+IEU1 Group */ + mov %g6, %o0 /* IEU0 */ + + .align 16 +26: ldub [%o1], %o3 /* Load */ + sllx %g1, 7, %g2 /* IEU0 Group */ + stb %o3, [%o0] /* Store */ +27: subcc %o2, 1, %o2 /* IEU1 */ + + be,pn %XCC, 9b /* CTI */ + add %o1, 1, %o1 /* IEU0 Group */ + add %o0, 1, %o0 /* IEU1 */ + andcc %o3, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 25b /* CTI */ + lduba [%o1] ASI_PNF, %o3 /* Load */ + andcc %o0, 7, %g0 /* IEU1 Group */ + bne,a,pt %icc, 27b /* CTI */ + + stb %o3, [%o0] /* Store */ + andcc %o1, 7, %g3 /* IEU1 Group */ + be,a,pt %icc, 1b /* CTI */ + ldx [%o1], %o3 /* Load */ + +28: orcc %g0, 64, %g4 /* IEU1 Group */ + sllx %g3, 3, %g5 /* IEU0 */ + sub %g4, %g5, %g4 /* IEU0 Group */ + sub %o1, %g3, %o1 /* IEU1 */ + /* %g1 = 0101010101010101 + %g2 = 8080808080808080 + %g3 = source alignment + %g5 = number of bits to shift left + %g4 = number of bits to shift right */ + + ldxa [%o1] ASI_PNF, %o5 /* Load Group */ + addcc %o1, 8, %o1 /* IEU1 */ + +29: sllx %o5, %g5, %o3 /* IEU0 Group */ + ldxa [%o1] ASI_PNF, %o5 /* Load */ + subcc %o2, 8, %o2 /* IEU1 */ + bl,pn %XCC, 17b /* CTI */ + + srlx %o5, %g4, %o4 /* IEU0 Group */ + add %o1, 8, %o1 /* IEU1 */ + or %o3, %o4, %o3 /* IEU0 Group */ + add %o0, 8, %o0 /* IEU1 */ + + sub %o3, %g1, %o4 /* IEU0 Group */ +#ifdef EIGHTBIT_NOT_RARE + andn %o4, %o3, %o4 /* IEU0 Group */ +#endif + andcc %o4, %g2, %g0 /* IEU1 Group */ + be,a,pt %xcc, 29b /* CTI */ + stx %o3, [%o0-8] /* Store */ + + srlx %o3, 56, %o4 /* IEU0 Group */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 36f /* CTI */ + srlx %o3, 48, %o4 /* IEU0 */ + + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 35f /* CTI */ + srlx %o3, 40, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 34f /* CTI */ + srlx %o3, 32, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 33f /* CTI */ + + srlx %o3, 24, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 32f /* CTI */ + srlx %o3, 16, %o4 /* IEU0 */ + + andcc %o4, 0xff, %g0 /* IEU1 Group */ + be,pn %icc, 31f /* CTI */ + srlx %o3, 8, %o4 /* IEU0 */ + andcc %o4, 0xff, %g0 /* IEU1 Group */ + + be,pn %icc, 30f /* CTI */ + andcc %o3, 0xff, %g0 /* IEU1 Group */ + bne,pn %icc, 29b /* CTI */ + stx %o3, [%o0-8] /* Store */ + + ba,pt %xcc, 4b /* CTI Group */ + andncc %o2, 31, %g3 /* IEU1 */ +30: srlx %o3, 8, %o4 /* IEU0 */ + ba,pt %xcc, 3b /* CTI */ + + sllx %o4, 8, %g3 /* IEU0 Group */ +31: srlx %o3, 16, %o4 /* IEU0 Group */ + ba,pt %xcc, 3b /* CTI */ + sllx %o4, 16, %g3 /* IEU0 Group */ + +32: srlx %o3, 24, %o4 /* IEU0 Group */ + ba,pt %xcc, 3b /* CTI */ + sllx %o4, 24, %g3 /* IEU0 Group */ +33: srlx %o3, 32, %o4 /* IEU0 Group */ + + ba,pt %xcc, 3b /* CTI */ + sllx %o4, 32, %g3 /* IEU0 Group */ +34: srlx %o3, 40, %o4 /* IEU0 Group */ + ba,pt %xcc, 3b /* CTI */ + + sllx %o4, 40, %g3 /* IEU0 Group */ +35: srlx %o3, 48, %o4 /* IEU0 Group */ + ba,pt %xcc, 3b /* CTI */ + sllx %o4, 48, %g3 /* IEU0 Group */ + +36: srlx %o3, 56, %o4 /* IEU0 Group */ + ba,pt %xcc, 3b /* CTI */ + sllx %o4, 56, %g3 /* IEU0 Group */ +END(strncpy) +libc_hidden_builtin_def (strncpy) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/strpbrk.S b/REORG.TODO/sysdeps/sparc/sparc64/strpbrk.S new file mode 100644 index 0000000000..08e0c2f30f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/strpbrk.S @@ -0,0 +1,230 @@ +/* strpbrk (s, accept) -- Find the first occurrence in S of any character in + ACCEPT. + For SPARC v9. + Copyright (C) 1999-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jj@ultra.linux.cz> + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <asm/asi.h> +#ifndef XCC +#define XCC xcc +#define STACK_SIZE 128 +#define STACK_OFFSET 128+0x7ff + .register %g2, #scratch +#else +#define STACK_SIZE 64 +#define STACK_OFFSET 64 +#endif + + .text + .align 32 +ENTRY(strpbrk) + sub %sp, STACK_SIZE+32, %sp /* IEU0 Group */ + mov 1, %o4 /* IEU1 */ + stx %o4, [%sp + STACK_OFFSET] /* Store Group */ + stx %g0, [%sp + STACK_OFFSET + 8] /* Store Group */ + + add %sp, STACK_OFFSET, %o5 /* IEU0 */ + stx %g0, [%sp + STACK_OFFSET + 16] /* Store Group */ + stx %g0, [%sp + STACK_OFFSET + 24] /* Store Group */ +1: ldub [%o1], %o2 /* Load Group */ + + brz,pn %o2, 2f /* CTI+IEU1 Group */ + srl %o2, 3, %o3 /* IEU0 */ + and %o3, 0x18, %o3 /* IEU0 Group */ + and %o2, 0x3f, %o2 /* IEU1 */ + + ldx [%o5 + %o3], %g2 /* Load Group */ + sllx %o4, %o2, %g1 /* IEU0 */ + add %o1, 1, %o1 /* IEU1 */ + or %g2, %g1, %g2 /* IEU0 Group */ + + ba,pt %xcc, 1b /* CTI */ + stx %g2, [%o5 + %o3] /* Store */ +2: andcc %o0, 7, %g0 /* IEU1 Group */ + be,a,pt %xcc, 4f /* CTI */ + + ldx [%o0], %o2 /* Load */ + ldub [%o0], %o2 /* Load Group */ +3: srl %o2, 3, %o3 /* IEU0 Group */ + and %o2, 0x3f, %o2 /* IEU1 */ + + and %o3, 0x18, %o3 /* IEU0 Group */ + ldx [%o5 + %o3], %g2 /* Load Group */ + sllx %o4, %o2, %g1 /* IEU0 */ + add %o0, 1, %o0 /* IEU1 */ + + andcc %g2, %g1, %g0 /* IEU1 Group */ + bne,pn %xcc, 12f /* CTI */ + andcc %o0, 7, %g0 /* IEU1 Group */ + bne,a,pt %icc, 3b /* CTI */ + + ldub [%o0], %o2 /* Load */ + ldx [%o0], %o2 /* Load Group */ +4: srlx %o2, 59, %o3 /* IEU0 Group */ + srlx %o2, 56, %g4 /* IEU0 Group */ + +5: and %o3, 0x18, %o3 /* IEU1 */ + andcc %g4, 0x3f, %g4 /* IEU1 Group */ + ldx [%o5 + %o3], %g2 /* Load */ + srlx %o2, 51, %o3 /* IEU0 */ + + sllx %o4, %g4, %g1 /* IEU0 Group */ + srlx %o2, 48, %g4 /* IEU0 Group */ + andcc %g2, %g1, %g2 /* IEU1 */ + bne,pn %xcc, 13f /* CTI */ + + and %o3, 0x18, %o3 /* IEU0 Group */ + and %g4, 0x3f, %g4 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + srlx %o2, 43, %o3 /* IEU0 */ + + sllx %o4, %g4, %g1 /* IEU0 Group */ + srlx %o2, 40, %g4 /* IEU0 Group */ + andcc %g2, %g1, %g2 /* IEU1 */ + bne,pn %xcc, 14f /* CTI */ + + and %o3, 0x18, %o3 /* IEU0 Group */ + and %g4, 0x3f, %g4 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + srlx %o2, 35, %o3 /* IEU0 */ + + sllx %o4, %g4, %g1 /* IEU0 Group */ + srlx %o2, 32, %g4 /* IEU0 Group */ + andcc %g2, %g1, %g2 /* IEU1 */ + bne,pn %xcc, 15f /* CTI */ + + and %o3, 0x18, %o3 /* IEU0 Group */ + and %g4, 0x3f, %g4 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + srlx %o2, 27, %o3 /* IEU0 */ + + sllx %o4, %g4, %g1 /* IEU0 Group */ + srlx %o2, 24, %g4 /* IEU0 Group */ + andcc %g2, %g1, %g2 /* IEU1 */ + bne,pn %xcc, 16f /* CTI */ + + and %o3, 0x18, %o3 /* IEU0 Group */ + and %g4, 0x3f, %g4 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + srlx %o2, 19, %o3 /* IEU0 */ + + sllx %o4, %g4, %g1 /* IEU0 Group */ + srlx %o2, 16, %g4 /* IEU0 Group */ + andcc %g2, %g1, %g2 /* IEU1 */ + bne,pn %xcc, 17f /* CTI */ + + and %o3, 0x18, %o3 /* IEU0 Group */ + and %g4, 0x3f, %g4 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + srlx %o2, 11, %o3 /* IEU0 */ + + sllx %o4, %g4, %g1 /* IEU0 Group */ + add %o0, 8, %o0 /* IEU1 */ + srlx %o2, 8, %g4 /* IEU0 Group */ + andcc %g2, %g1, %g2 /* IEU1 */ + + bne,pn %xcc, 18f /* CTI */ + and %o3, 0x18, %o3 /* IEU0 Group */ + and %g4, 0x3f, %g4 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + + sllx %o4, %g4, %g1 /* IEU0 */ + mov %o2, %g5 /* IEU1 */ + srlx %o2, 3, %o3 /* IEU0 Group */ + ldxa [%o0] ASI_PNF, %o2 /* Load */ + + andcc %g2, %g1, %g2 /* IEU1 Group */ + bne,pn %xcc, 19f /* CTI */ + and %o3, 0x18, %o3 /* IEU0 Group */ + and %g5, 0x3f, %g4 /* IEU1 */ + + ldx [%o5 + %o3], %g2 /* Load Group */ + sllx %o4, %g4, %g1 /* IEU0 */ + srlx %o2, 59, %o3 /* IEU0 Group */ + andcc %g2, %g1, %g2 /* IEU1 Group */ + + be,pt %xcc, 5b /* CTI */ + srlx %o2, 56, %g4 /* IEU0 Group */ + sub %o0, 1, %o0 /* IEU1 */ + add %sp, STACK_SIZE+32, %sp /* IEU0 Group */ + + andcc %g5, 0xff, %g0 /* IEU1 */ + retl /* CTI+IEU1 Group */ + move %icc, 0, %o0 /* Single Group */ + + .align 16 +19: sub %o0, 2, %o0 /* IEU1 */ + srl %g5, 8, %g1 /* IEU0 Group */ + add %sp, STACK_SIZE+32, %sp /* IEU1 */ + andcc %g1, 0xff, %g0 /* IEU1 Group */ + + retl /* CTI+IEU1 Group */ + move %icc, 0, %o0 /* Single Group */ +18: sub %o0, 3, %o0 /* IEU1 */ + srl %o2, 16, %g1 /* IEU0 Group */ + + add %sp, STACK_SIZE+32, %sp /* IEU1 */ + andcc %g1, 0xff, %g0 /* IEU1 Group */ + retl /* CTI+IEU1 Group */ + move %icc, 0, %o0 /* Single Group */ + +17: add %o0, 4, %o0 /* IEU1 */ + srl %o2, 24, %g1 /* IEU0 Group */ + add %sp, STACK_SIZE+32, %sp /* IEU1 */ + retl /* CTI+IEU1 Group */ + + movrz %g1, 0, %o0 /* Single Group */ +16: add %o0, 3, %o0 /* IEU1 */ + srlx %o2, 32, %g1 /* IEU0 Group */ + add %sp, STACK_SIZE+32, %sp /* IEU1 */ + + andcc %g1, 0xff, %g0 /* IEU1 Group */ + retl /* CTI+IEU1 Group */ + move %icc, 0, %o0 /* Single Group */ + + .align 16 +15: add %o0, 2, %o0 /* IEU1 */ + srlx %o2, 40, %g1 /* IEU0 Group */ + add %sp, STACK_SIZE+32, %sp /* IEU1 */ + andcc %g1, 0xff, %g0 /* IEU1 Group */ + + retl /* CTI+IEU1 Group */ + move %icc, 0, %o0 /* Single Group */ +14: add %o0, 1, %o0 /* IEU1 */ + srlx %o2, 48, %g1 /* IEU0 Group */ + + add %sp, STACK_SIZE+32, %sp /* IEU1 */ + andcc %g1, 0xff, %g0 /* IEU1 Group */ + retl /* CTI+IEU1 Group */ + move %icc, 0, %o0 /* Single Group */ + +13: add %sp, STACK_SIZE+32, %sp /* IEU1 */ + srlx %o2, 56, %g1 /* IEU0 Group */ + retl /* CTI+IEU1 Group */ + movrz %g1, 0, %o0 /* Single Group */ + + .align 16 +12: sub %o0, 1, %o0 /* IEU0 Group */ + or %o3, %o2, %g1 /* IEU1 */ + add %sp, STACK_SIZE+32, %sp /* IEU0 Group */ + retl /* CTI+IEU1 Group */ + + movrz %g1, 0, %o0 /* Single Group */ +END(strpbrk) +libc_hidden_builtin_def (strpbrk) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/strrchr.c b/REORG.TODO/sysdeps/sparc/sparc64/strrchr.c new file mode 100644 index 0000000000..ec608d6ab3 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/strrchr.c @@ -0,0 +1 @@ +/* strrchr is in strchr.S */ diff --git a/REORG.TODO/sysdeps/sparc/sparc64/strspn.S b/REORG.TODO/sysdeps/sparc/sparc64/strspn.S new file mode 100644 index 0000000000..7c560b9bc2 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/strspn.S @@ -0,0 +1,212 @@ +/* strspn (str, ss) -- Return the length of the maximum initial segment + of S which contains only characters in ACCEPT. + For SPARC v9. + Copyright (C) 1999-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jj@ultra.linux.cz> + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <asm/asi.h> +#ifndef XCC +#define XCC xcc +#define STACK_SIZE 128 +#define STACK_OFFSET 128+0x7ff + .register %g2, #scratch +#else +#define STACK_SIZE 64 +#define STACK_OFFSET 64 +#endif + + .text + .align 32 +ENTRY(strspn) + sub %sp, STACK_SIZE+32, %sp /* IEU0 Group */ + mov 1, %o4 /* IEU1 */ + stx %g0, [%sp + STACK_OFFSET] /* Store Group */ + mov %o0, %g4 /* IEU0 */ + + stx %g0, [%sp + STACK_OFFSET + 8] /* Store Group */ + add %sp, STACK_OFFSET, %o5 /* IEU0 */ + stx %g0, [%sp + STACK_OFFSET + 16] /* Store Group */ + stx %g0, [%sp + STACK_OFFSET + 24] /* Store Group */ + +1: ldub [%o1], %o2 /* Load Group */ + brz,pn %o2, 2f /* CTI+IEU1 Group */ + srl %o2, 3, %o3 /* IEU0 */ + and %o3, 0x18, %o3 /* IEU0 Group */ + + and %o2, 0x3f, %o2 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + sllx %o4, %o2, %g1 /* IEU0 */ + add %o1, 1, %o1 /* IEU1 */ + + or %g2, %g1, %g2 /* IEU0 Group */ + ba,pt %xcc, 1b /* CTI */ + stx %g2, [%o5 + %o3] /* Store */ +2: andcc %o0, 7, %g0 /* IEU1 Group */ + + be,a,pt %xcc, 4f /* CTI */ + ldx [%o0], %o2 /* Load */ + ldub [%o0], %o2 /* Load Group */ +3: srl %o2, 3, %o3 /* IEU0 Group */ + + and %o2, 0x3f, %o2 /* IEU1 */ + and %o3, 0x18, %o3 /* IEU0 Group */ + ldx [%o5 + %o3], %g2 /* Load Group */ + sllx %o4, %o2, %g1 /* IEU0 */ + + add %o0, 1, %o0 /* IEU1 */ + andcc %g2, %g1, %g0 /* IEU1 Group */ + be,pn %xcc, 12f /* CTI */ + andcc %o0, 7, %g0 /* IEU1 Group */ + + bne,a,pt %icc, 3b /* CTI */ + ldub [%o0], %o2 /* Load */ + ldx [%o0], %o2 /* Load Group */ +4: srlx %o2, 59, %o3 /* IEU0 Group */ + + srlx %o2, 56, %g5 /* IEU0 Group */ +5: and %o3, 0x18, %o3 /* IEU1 */ + andcc %g5, 0x3f, %g5 /* IEU1 Group */ + ldx [%o5 + %o3], %g2 /* Load */ + + srlx %o2, 51, %o3 /* IEU0 */ + sllx %o4, %g5, %g1 /* IEU0 Group */ + srlx %o2, 48, %g5 /* IEU0 Group */ + andcc %g2, %g1, %g2 /* IEU1 */ + + be,pn %xcc, 13f /* CTI */ + and %o3, 0x18, %o3 /* IEU0 Group */ + and %g5, 0x3f, %g5 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + + srlx %o2, 43, %o3 /* IEU0 */ + sllx %o4, %g5, %g1 /* IEU0 Group */ + srlx %o2, 40, %g5 /* IEU0 Group */ + andcc %g2, %g1, %g2 /* IEU1 */ + + be,pn %xcc, 14f /* CTI */ + and %o3, 0x18, %o3 /* IEU0 Group */ + and %g5, 0x3f, %g5 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + + srlx %o2, 35, %o3 /* IEU0 */ + sllx %o4, %g5, %g1 /* IEU0 Group */ + srlx %o2, 32, %g5 /* IEU0 Group */ + andcc %g2, %g1, %g2 /* IEU1 */ + + be,pn %xcc, 15f /* CTI */ + and %o3, 0x18, %o3 /* IEU0 Group */ + and %g5, 0x3f, %g5 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + + srlx %o2, 27, %o3 /* IEU0 */ + sllx %o4, %g5, %g1 /* IEU0 Group */ + srlx %o2, 24, %g5 /* IEU0 Group */ + andcc %g2, %g1, %g2 /* IEU1 */ + + be,pn %xcc, 16f /* CTI */ + and %o3, 0x18, %o3 /* IEU0 Group */ + and %g5, 0x3f, %g5 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + + srlx %o2, 19, %o3 /* IEU0 */ + sllx %o4, %g5, %g1 /* IEU0 Group */ + srlx %o2, 16, %g5 /* IEU0 Group */ + andcc %g2, %g1, %g2 /* IEU1 */ + + be,pn %xcc, 17f /* CTI */ + and %o3, 0x18, %o3 /* IEU0 Group */ + and %g5, 0x3f, %g5 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + + srlx %o2, 11, %o3 /* IEU0 */ + sllx %o4, %g5, %g1 /* IEU0 Group */ + add %o0, 8, %o0 /* IEU1 */ + srlx %o2, 8, %g5 /* IEU0 Group */ + + andcc %g2, %g1, %g2 /* IEU1 */ + be,pn %xcc, 18f /* CTI */ + and %o3, 0x18, %o3 /* IEU0 Group */ + and %g5, 0x3f, %g5 /* IEU1 */ + + ldx [%o5 + %o3], %g2 /* Load Group */ + sllx %o4, %g5, %g1 /* IEU0 */ + mov %o2, %g5 /* IEU1 */ + srlx %o2, 3, %o3 /* IEU0 Group */ + + ldxa [%o0] ASI_PNF, %o2 /* Load */ + andcc %g2, %g1, %g2 /* IEU1 Group */ + be,pn %xcc, 19f /* CTI */ + and %o3, 0x18, %o3 /* IEU0 Group */ + + and %g5, 0x3f, %g5 /* IEU1 */ + ldx [%o5 + %o3], %g2 /* Load Group */ + sllx %o4, %g5, %g1 /* IEU0 */ + srlx %o2, 59, %o3 /* IEU0 Group */ + + andcc %g2, %g1, %g2 /* IEU1 Group */ + bne,pt %xcc, 5b /* CTI */ + srlx %o2, 56, %g5 /* IEU0 Group */ + sub %o0, 1, %o0 /* IEU1 */ + + add %sp, STACK_SIZE+32, %sp /* IEU0 Group */ + retl /* CTI+IEU1 Group */ + sub %o0, %g4, %o0 /* IEU0 */ + + .align 16 +19: sub %o0, 2, %o0 /* IEU1 */ + add %sp, STACK_SIZE+32, %sp /* IEU0 Group */ + retl /* CTI+IEU1 Group */ + sub %o0, %g4, %o0 /* IEU0 */ + +18: sub %o0, 3, %o0 /* IEU1 */ + add %sp, STACK_SIZE+32, %sp /* IEU0 Group */ + retl /* CTI+IEU1 Group */ + sub %o0, %g4, %o0 /* IEU0 */ + +17: add %o0, 4, %o0 /* IEU1 */ + add %sp, STACK_SIZE+32, %sp /* IEU0 Group */ + retl /* CTI+IEU1 Group */ + sub %o0, %g4, %o0 /* IEU0 */ + +16: add %o0, 3, %o0 /* IEU1 */ + add %sp, STACK_SIZE+32, %sp /* IEU0 Group */ + retl /* CTI+IEU1 Group */ + sub %o0, %g4, %o0 /* IEU0 */ + +15: add %o0, 2, %o0 /* IEU1 */ + add %sp, STACK_SIZE+32, %sp /* IEU0 Group */ + retl /* CTI+IEU1 Group */ + sub %o0, %g4, %o0 /* IEU0 */ + +14: add %o0, 1, %o0 /* IEU1 */ + add %sp, STACK_SIZE+32, %sp /* IEU0 Group */ + retl /* CTI+IEU1 Group */ + sub %o0, %g4, %o0 /* IEU0 */ + +13: add %sp, STACK_SIZE+32, %sp /* IEU1 */ + retl /* CTI+IEU1 Group */ + sub %o0, %g4, %o0 /* IEU0 */ + + .align 16 +12: sub %o0, 1, %o0 /* IEU0 Group */ + add %sp, STACK_SIZE+32, %sp /* IEU1 */ + retl /* CTI+IEU1 Group */ + sub %o0, %g4, %o0 /* IEU0 */ +END(strspn) +libc_hidden_builtin_def (strspn) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/sub_n.S b/REORG.TODO/sysdeps/sparc/sparc64/sub_n.S new file mode 100644 index 0000000000..006ae809c8 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/sub_n.S @@ -0,0 +1,54 @@ +/* SPARC v9 __mpn_sub_n -- Subtract two limb vectors of the same length > 0 + and store difference in a third limb vector. + + Copyright (C) 1995-2017 Free Software Foundation, Inc. + + This file is part of the GNU MP Library. + + The GNU MP Library is free software; you can redistribute it and/or modify + it under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation; either version 2.1 of the License, or (at your + option) any later version. + + The GNU MP Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with the GNU MP Library; see the file COPYING.LIB. If not, + see <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +/* INPUT PARAMETERS + res_ptr %o0 + s1_ptr %o1 + s2_ptr %o2 + size %o3 */ + +ENTRY(__mpn_sub_n) + + sub %g0,%o3,%g5 + sllx %o3,3,%g1 + add %o1,%g1,%o1 ! make s1_ptr point at end + add %o2,%g1,%o2 ! make s2_ptr point at end + add %o0,%g1,%o0 ! make res_ptr point at end + mov 0,%o4 ! clear carry variable + sllx %g5,3,%o5 ! compute initial address index + +1: ldx [%o2+%o5],%g1 ! load s2 limb + add %g5,1,%g5 ! increment loop count + ldx [%o1+%o5],%o3 ! load s1 limb + addcc %g1,%o4,%g1 ! add s2 limb and carry variable + movcc %xcc,0,%o4 ! if carry-out, o4 was 1; clear it + subcc %o3,%g1,%g1 ! subtract s1 limb from sum + stx %g1,[%o0+%o5] ! store result + add %o5,8,%o5 ! increment address index + brnz,pt %g5,1b + movcs %xcc,1,%o4 ! if s1 subtract gave carry, record it + + retl + mov %o4,%o0 + +END(__mpn_sub_n) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/submul_1.S b/REORG.TODO/sysdeps/sparc/sparc64/submul_1.S new file mode 100644 index 0000000000..03e62b668b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/submul_1.S @@ -0,0 +1,82 @@ +/* SPARC v9 __mpn_submul_1 -- Multiply a limb vector with a single limb and + subtract the product from a second limb vector. + + Copyright (C) 1996-2017 Free Software Foundation, Inc. + + This file is part of the GNU MP Library. + + The GNU MP Library is free software; you can redistribute it and/or modify + it under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation; either version 2.1 of the License, or (at your + option) any later version. + + The GNU MP Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with the GNU MP Library; see the file COPYING.LIB. If not, + see <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + +/* INPUT PARAMETERS + res_ptr o0 + s1_ptr o1 + size o2 + s2_limb o3 */ + +ENTRY(__mpn_submul_1) + save %sp,-192,%sp + + sub %g0,%i2,%o7 + mov 0,%o0 ! zero cy_limb + sllx %o7,3,%o7 + sethi %hi(0x80000000),%o2 + srl %i3,0,%o1 ! extract low 32 bits of s2_limb + sub %i1,%o7,%o3 + srlx %i3,32,%i3 ! extract high 32 bits of s2_limb + sub %i0,%o7,%o4 + add %o2,%o2,%o2 ! o2 = 0x100000000 + + ! hi ! + ! mid-1 ! + ! mid-2 ! + ! lo ! +1: + ldx [%o3+%o7],%g5 + srl %g5,0,%i0 ! zero hi bits + ldx [%o4+%o7],%l1 + srlx %g5,32,%g5 + mulx %o1,%i0,%i4 ! lo product + mulx %i3,%i0,%i1 ! mid-1 product + mulx %o1,%g5,%l2 ! mid-2 product + mulx %i3,%g5,%i5 ! hi product + srlx %i4,32,%i0 ! extract high 32 bits of lo product... + add %i1,%i0,%i1 ! ...and add it to the mid-1 product + addcc %i1,%l2,%i1 ! add mid products + mov 0,%l0 ! we need the carry from that add... + movcs %xcc,%o2,%l0 ! ...compute it and... + sllx %i1,32,%i0 ! align low bits of mid product + add %i5,%l0,%i5 ! ...add to bit 32 of the hi product + srl %i4,0,%g5 ! zero high 32 bits of lo product + add %i0,%g5,%i0 ! combine into low 64 bits of result + srlx %i1,32,%i1 ! extract high bits of mid product... + addcc %i0,%o0,%i0 ! add cy_limb to low 64 bits of result + add %i5,%i1,%i1 ! ...and add them to the high result + mov 0,%g5 + movcs %xcc,1,%g5 + subcc %l1,%i0,%i0 + stx %i0,[%o4+%o7] + add %g5,1,%l1 + movcs %xcc,%l1,%g5 + addcc %o7,8,%o7 + bne,pt %xcc,1b + add %i1,%g5,%o0 ! compute new cy_limb + + jmpl %i7+8, %g0 + restore %o0,%g0,%o0 + +END(__mpn_submul_1) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/tls-macros.h b/REORG.TODO/sysdeps/sparc/sparc64/tls-macros.h new file mode 100644 index 0000000000..bb0d8035fc --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/tls-macros.h @@ -0,0 +1,65 @@ +#define TLS_LE(x) \ + ({ int *__l; \ + asm ("sethi %%tle_hix22(" #x "), %0" : "=r" (__l)); \ + asm ("xor %1, %%tle_lox10(" #x "), %0" : "=r" (__l) : "r" (__l)); \ + asm ("add %%g7, %1, %0" : "=r" (__l) : "r" (__l)); \ + __l; }) + +#ifdef __PIC__ +# define TLS_LOAD_PIC \ + ({ long pc, got; \ + asm ("sethi %%hi(_GLOBAL_OFFSET_TABLE_-4), %1\n\t" \ + "rd %%pc, %0\n\t" \ + "add %1, %%lo(_GLOBAL_OFFSET_TABLE_+4), %1\n\t" \ + "add %1, %0, %1\n\t" \ + : "=r" (pc), "=r" (got)); \ + got; }) +#else +# define TLS_LOAD_PIC \ + ({ long got; \ + asm (".hidden _GLOBAL_OFFSET_TABLE_\n\t" \ + "sethi %%hi(_GLOBAL_OFFSET_TABLE_), %0\n\t" \ + "or %0, %%lo(_GLOBAL_OFFSET_TABLE_), %0" \ + : "=r" (got)); \ + got; }) +#endif + +#define TLS_IE(x) \ + ({ int *__l; \ + asm ("sethi %%tie_hi22(" #x "), %0" : "=r" (__l)); \ + asm ("add %1, %%tie_lo10(" #x "), %0" : "=r" (__l) : "r" (__l)); \ + asm ("ldx [%1 + %2], %0, %%tie_ldx(" #x ")" \ + : "=r" (__l) : "r" (TLS_LOAD_PIC), "r" (__l)); \ + asm ("add %%g7, %1, %0, %%tie_add(" #x ")" : "=r" (__l) : "r" (__l)); \ + __l; }) + +#define TLS_LD(x) \ + ({ int *__l; register void *__o0 asm ("%o0"); \ + long __o; \ + asm ("sethi %%tldm_hi22(" #x "), %0" : "=r" (__l)); \ + asm ("add %1, %%tldm_lo10(" #x "), %0" : "=r" (__l) : "r" (__l)); \ + asm ("add %1, %2, %0, %%tldm_add(" #x ")" \ + : "=r" (__o0) : "r" (TLS_LOAD_PIC), "r" (__l)); \ + asm ("call __tls_get_addr, %%tgd_call(" #x ")\n\t" \ + " nop" \ + : "=r" (__o0) : "0" (__o0) \ + : "g1", "g2", "g3", "g4", "g5", "g6", "o1", "o2", "o3", "o4", \ + "o5", "o7", "cc"); \ + asm ("sethi %%tldo_hix22(" #x "), %0" : "=r" (__o)); \ + asm ("xor %1, %%tldo_lox10(" #x "), %0" : "=r" (__o) : "r" (__o)); \ + asm ("add %1, %2, %0, %%tldo_add(" #x ")" : "=r" (__l) \ + : "r" (__o0), "r" (__o)); \ + __l; }) + +#define TLS_GD(x) \ + ({ int *__l; register void *__o0 asm ("%o0"); \ + asm ("sethi %%tgd_hi22(" #x "), %0" : "=r" (__l)); \ + asm ("add %1, %%tgd_lo10(" #x "), %0" : "=r" (__l) : "r" (__l)); \ + asm ("add %1, %2, %0, %%tgd_add(" #x ")" \ + : "=r" (__o0) : "r" (TLS_LOAD_PIC), "r" (__l)); \ + asm ("call __tls_get_addr, %%tgd_call(" #x ")\n\t" \ + " nop" \ + : "=r" (__o0) : "0" (__o0) \ + : "g1", "g2", "g3", "g4", "g5", "g6", "o1", "o2", "o3", "o4", \ + "o5", "o7", "cc"); \ + __o0; }) diff --git a/REORG.TODO/sysdeps/sparc/sparc64/tst-audit.h b/REORG.TODO/sysdeps/sparc/sparc64/tst-audit.h new file mode 100644 index 0000000000..f7123e0ef1 --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sparc64/tst-audit.h @@ -0,0 +1,25 @@ +/* Definitions for testing PLT entry/exit auditing. SPARC64 version. + + Copyright (C) 2012-2017 Free Software Foundation, Inc. + + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library. If not, see + <http://www.gnu.org/licenses/>. */ + +#define pltenter la_sparc64_gnu_pltenter +#define pltexit la_sparc64_gnu_pltexit +#define La_regs La_sparc64_regs +#define La_retval La_sparc64_retval +#define int_retval lrv_reg[0] diff --git a/REORG.TODO/sysdeps/sparc/stackinfo.h b/REORG.TODO/sysdeps/sparc/stackinfo.h new file mode 100644 index 0000000000..c5c1e5224b --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/stackinfo.h @@ -0,0 +1,33 @@ +/* Copyright (C) 2001-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +/* This file contains a bit of information about the stack allocation + of the processor. */ + +#ifndef _STACKINFO_H +#define _STACKINFO_H 1 + +#include <elf.h> + +/* On sparc the stack grows down. */ +#define _STACK_GROWS_DOWN 1 + +/* Default to an executable stack. PF_X can be overridden if PT_GNU_STACK is + * present, but it is presumed absent. */ +#define DEFAULT_STACK_PERMS (PF_R|PF_W|PF_X) + +#endif /* stackinfo.h */ diff --git a/REORG.TODO/sysdeps/sparc/sys/trap.h b/REORG.TODO/sysdeps/sparc/sys/trap.h new file mode 100644 index 0000000000..50be40668f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sys/trap.h @@ -0,0 +1,7 @@ +/* Include trap definitions. */ +#ifndef _SYS_TRAP_H +#define _SYS_TRAP_H 1 + +#include <machine/trap.h> + +#endif /* sys/trap.h */ diff --git a/REORG.TODO/sysdeps/sparc/sysdep.h b/REORG.TODO/sysdeps/sparc/sysdep.h new file mode 100644 index 0000000000..245e5cc57f --- /dev/null +++ b/REORG.TODO/sysdeps/sparc/sysdep.h @@ -0,0 +1,82 @@ +/* Copyright (C) 2011-2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#define _SYSDEPS_SYSDEP_H 1 +#include <bits/hwcap.h> + +#ifdef __ASSEMBLER__ + +#define SPARC_PIC_THUNK(reg) \ + .ifndef __sparc_get_pc_thunk.reg; \ + .section .text.__sparc_get_pc_thunk.reg,"axG",@progbits,__sparc_get_pc_thunk.reg,comdat; \ + .align 32; \ + .weak __sparc_get_pc_thunk.reg; \ + .hidden __sparc_get_pc_thunk.reg; \ + .type __sparc_get_pc_thunk.reg, #function; \ +__sparc_get_pc_thunk.reg: \ + jmp %o7 + 8; \ + add %o7, %reg, %##reg; \ + .previous; \ + .endif; + +/* The "-4" and "+4" offsets against _GLOBAL_OFFSET_TABLE_ are + critical since they represent the offset from the thunk call to the + instruction containing the _GLOBAL_OFFSET_TABLE_ reference. + Therefore these instructions cannot be moved around without + appropriate adjustments to those offsets. + + Furthermore, these expressions are special in another regard. When + the assembler sees a reference to _GLOBAL_OFFSET_TABLE_ inside of + a %hi() or %lo(), it emits a PC-relative relocation. This causes + R_SPARC_HI22 to turn into R_SPARC_PC22, and R_SPARC_LO10 to turn into + R_SPARC_PC10, respectively. + + Even when v9 we use a call sequence instead of using "rd %pc" because + RDPC is extremely expensive and incurs a full pipeline flush. */ + +#define SPARC_PIC_THUNK_CALL(reg) \ + sethi %hi(_GLOBAL_OFFSET_TABLE_-4), %##reg; \ + call __sparc_get_pc_thunk.reg; \ + or %##reg, %lo(_GLOBAL_OFFSET_TABLE_+4), %##reg; + +#define SETUP_PIC_REG(reg) \ + SPARC_PIC_THUNK(reg) \ + SPARC_PIC_THUNK_CALL(reg) + +#define SETUP_PIC_REG_LEAF(reg, tmp) \ + SPARC_PIC_THUNK(reg) \ + mov %o7, %##tmp; \ + SPARC_PIC_THUNK_CALL(reg); \ + mov %##tmp, %o7; + +#undef ENTRY +#define ENTRY(name) \ + .align 4; \ + .global C_SYMBOL_NAME(name); \ + .type name, @function; \ +C_LABEL(name) \ + cfi_startproc; + +#undef END +#define END(name) \ + cfi_endproc; \ + .size name, . - name + +#undef LOC +#define LOC(name) .L##name + +#endif /* __ASSEMBLER__ */ |