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+2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* sysdeps/x86/cacheinfo.c (init_cacheinfo): Count number of
+	available logical processors with SMT level type sharing L2
+	cache for Intel processors.
+
 2016-05-27  Joseph Myers  <joseph@codesourcery.com>
 
 	[BZ #20160]