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diff --git a/ChangeLog b/ChangeLog
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+2015-08-05  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	* sysdeps/aarch64/fpu/fesetenv.c (fesetenv):
+	Optimize to reduce FPCR/FPSR accesses.
+
 2015-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* locale/loadarchive.c (_nl_archive_subfreeres): Also check