diff options
| -rw-r--r-- | ChangeLog | 6 | ||||
| -rw-r--r-- | sysdeps/x86/cacheinfo.c | 2 |
2 files changed, 6 insertions, 2 deletions
@@ -1,3 +1,9 @@ +2016-05-20 H.J. Lu <hongjiu.lu@intel.com> + + [BZ #18185] + * sysdeps/x86/cacheinfo.c (init_cacheinfo): Don't limit threads + sharing L2 cache to 2 for Knights Landing. + 2016-05-20 Joseph Myers <joseph@codesourcery.com> * conform/data/ftw.h-data (struct FTW): Do not expect for [XPG3]. diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c index 020d3fd397..182426b2d0 100644 --- a/sysdeps/x86/cacheinfo.c +++ b/sysdeps/x86/cacheinfo.c @@ -573,8 +573,6 @@ init_cacheinfo (void) { switch (model) { - case 0x57: - /* Knights Landing has L2 cache shared by 2 cores. */ case 0x37: case 0x4a: case 0x4d: |