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| -rw-r--r-- | ChangeLog | 3 | ||||
| -rw-r--r-- | manual/conf.texi | 12 |
2 files changed, 15 insertions, 0 deletions
@@ -1,5 +1,8 @@ 2017-10-23 Siddhesh Poyarekar <siddhesh@sourceware.org> + * manual/conf.texi (_SC_LEVEL1_DCACHE_LINESIZE, + _SC_LEVEL1_ICACHE_LINESIZE): Document aarch64 caveat. + * manual/conf.texi (_SC_LEVEL1_ICACHE_SIZE, _SC_LEVEL1_ICACHE_ASSOC, _SC_LEVEL1_ICACHE_LINESIZE, _SC_LEVEL1_DCACHE_SIZE, _SC_LEVEL1_DCACHE_ASSOC, diff --git a/manual/conf.texi b/manual/conf.texi index 079bdb295e..62ab444139 100644 --- a/manual/conf.texi +++ b/manual/conf.texi @@ -690,6 +690,12 @@ Inquire about the associativity of the Level 1 instruction cache. @standards{GNU, unistd.h} Inquire about the line length of the Level 1 instruction cache. +On aarch64, the cache line size returned is the minimum instruction cache line +size observable by userspace. This is typically the same as the L1 icache +size but on some cores it may not be so. However, it is specified in the +architecture that operations such as cache line invalidation are consistent +with the size reported with this variable. + @item _SC_LEVEL1_DCACHE_SIZE @standards{GNU, unistd.h} Inquire about the size of the Level 1 data cache. @@ -702,6 +708,12 @@ Inquire about the associativity of the Level 1 data cache. @standards{GNU, unistd.h} Inquire about the line length of the Level 1 data cache. +On aarch64, the cache line size returned is the minimum data cache line size +observable by userspace. This is typically the same as the L1 dcache size but +on some cores it may not be so. However, it is specified in the architecture +that operations such as cache line invalidation are consistent with the size +reported with this variable. + @item _SC_LEVEL2_CACHE_SIZE @standards{GNU, unistd.h} Inquire about the size of the Level 2 cache. |