diff options
| -rw-r--r-- | ChangeLog | 7 | ||||
| -rw-r--r-- | sysdeps/i386/i686/multiarch/strcasecmp.S | 4 | ||||
| -rw-r--r-- | sysdeps/i386/i686/multiarch/strcmp.S | 4 | ||||
| -rw-r--r-- | sysdeps/i386/i686/multiarch/strncase.S | 4 |
4 files changed, 19 insertions, 0 deletions
@@ -1,3 +1,10 @@ +2013-08-21 Liubov Dmitrieva <liubov.dmitrieva@intel.com> + + * sysdeps/i386/i686/multiarch/strcmp.S: Skip SSE4_2 + version if bit_Slow_SSE4_2 is set. + * sysdeps/i386/i686/multiarch/strncase.S: Likewise. + * sysdeps/i386/i686/multiarch/strcasecmp.S: Likewise. + 2013-07-23 Adhemerval Zanella <azanella@linux.vnet.ibm.com> [BZ #15867] diff --git a/sysdeps/i386/i686/multiarch/strcasecmp.S b/sysdeps/i386/i686/multiarch/strcasecmp.S index 2444af26c3..25de4daf47 100644 --- a/sysdeps/i386/i686/multiarch/strcasecmp.S +++ b/sysdeps/i386/i686/multiarch/strcasecmp.S @@ -37,6 +37,8 @@ ENTRY(__strcasecmp) leal __strcasecmp_ssse3@GOTOFF(%ebx), %eax testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx) jz 2f + testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx) + jnz 2f leal __strcasecmp_sse4_2@GOTOFF(%ebx), %eax 2: popl %ebx cfi_adjust_cfa_offset (-4) @@ -56,6 +58,8 @@ ENTRY(__strcasecmp) leal __strcasecmp_ssse3, %eax testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features jz 2f + testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features + jnz 2f leal __strcasecmp_sse4_2, %eax 2: ret END(__strcasecmp) diff --git a/sysdeps/i386/i686/multiarch/strcmp.S b/sysdeps/i386/i686/multiarch/strcmp.S index 7dc2cefabe..41dd3b3f1c 100644 --- a/sysdeps/i386/i686/multiarch/strcmp.S +++ b/sysdeps/i386/i686/multiarch/strcmp.S @@ -68,6 +68,8 @@ ENTRY(STRCMP) leal __STRCMP_SSSE3@GOTOFF(%ebx), %eax testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx) jz 2f + testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx) + jnz 2f leal __STRCMP_SSE4_2@GOTOFF(%ebx), %eax 2: popl %ebx cfi_adjust_cfa_offset (-4) @@ -87,6 +89,8 @@ ENTRY(STRCMP) leal __STRCMP_SSSE3, %eax testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features jz 2f + testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features + jnz 2f leal __STRCMP_SSE4_2, %eax 2: ret END(STRCMP) diff --git a/sysdeps/i386/i686/multiarch/strncase.S b/sysdeps/i386/i686/multiarch/strncase.S index 939cd96ce0..de97e1b1a2 100644 --- a/sysdeps/i386/i686/multiarch/strncase.S +++ b/sysdeps/i386/i686/multiarch/strncase.S @@ -37,6 +37,8 @@ ENTRY(__strncasecmp) leal __strncasecmp_ssse3@GOTOFF(%ebx), %eax testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx) jz 2f + testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx) + jnz 2f leal __strncasecmp_sse4_2@GOTOFF(%ebx), %eax 2: popl %ebx cfi_adjust_cfa_offset (-4) @@ -56,6 +58,8 @@ ENTRY(__strncasecmp) leal __strncasecmp_ssse3, %eax testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features jz 2f + testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features + jnz 2f leal __strncasecmp_sse4_2, %eax 2: ret END(__strncasecmp) |