diff options
| -rw-r--r-- | ChangeLog | 6 | ||||
| -rw-r--r-- | sysdeps/x86/cacheinfo.c | 2 |
2 files changed, 7 insertions, 1 deletions
@@ -1,5 +1,11 @@ 2016-05-19 H.J. Lu <hongjiu.lu@intel.com> + [BZ #20119] + * sysdeps/x86/cacheinfo.c (init_cacheinfo): Correct Intel + processor level type mask for CPUID with EAX == 11. + +2016-05-19 H.J. Lu <hongjiu.lu@intel.com> + * sysdeps/x86/cacheinfo.c (init_cacheinfo): Skip counting logical threads if the HTT bit is 0. * sysdeps/x86/cpu-features.h (bit_cpu_HTT): New. diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c index 1f46d9de20..020d3fd397 100644 --- a/sysdeps/x86/cacheinfo.c +++ b/sysdeps/x86/cacheinfo.c @@ -552,7 +552,7 @@ init_cacheinfo (void) __cpuid_count (11, i++, eax, ebx, ecx, edx); int shipped = ebx & 0xff; - int type = ecx & 0xff0; + int type = ecx & 0xff00; if (shipped == 0 || type == 0) break; else if (type == 0x200) |