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| -rw-r--r-- | ChangeLog | 10 | ||||
| -rw-r--r-- | sysdeps/x86_64/fpu/s_ceill.S | 31 |
2 files changed, 41 insertions, 0 deletions
@@ -1,3 +1,13 @@ +2003-11-13 Andreas Jaeger <aj@suse.de> + + * sysdeps/unix/sysv/linux/kernel-features.h (__ASSUME_TGKILL): + Define appropriately for x86_64. + (__ASSUME_UTIMES): Likewise. + (__ASSUME_FADVISE64_64_SYSCALL): Likewise. + (__ASSUME_CLONE_THREAD_FLAGS): Likewise. + + * sysdeps/x86_64/fpu/s_ceill.S: New file. + 2003-11-13 Ulrich Drepper <drepper@redhat.com> * posix/regcomp.c (parse_expression): In BRE consecutive diff --git a/sysdeps/x86_64/fpu/s_ceill.S b/sysdeps/x86_64/fpu/s_ceill.S new file mode 100644 index 0000000000..efc8dd995e --- /dev/null +++ b/sysdeps/x86_64/fpu/s_ceill.S @@ -0,0 +1,31 @@ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Changes for long double by Ulrich Drepper <drepper@cygnus.com> + * Changes for x86-64 by Andreas Jaeger <aj@suse.de> + * Public domain. + */ + +#include <machine/asm.h> + + +ENTRY(__ceill) + fldt 8(%rsp) + + fstcw -4(%rsp) /* store fpu control word */ + + /* We use here %edx although only the low 1 bits are defined. + But none of the operations should care and they are faster + than the 16 bit operations. */ + movl $0x0800,%edx /* round towards +oo */ + orl -4(%rsp),%edx + andl $0xfbff,%edx + movl %edx,-8(%rsp) + fldcw -8(%rsp) /* load modified control word */ + + frndint /* round */ + + fldcw -4(%rsp) /* restore original control word */ + + ret +END (__ceill) +weak_alias (__ceill, ceill) |