diff options
| -rw-r--r-- | ChangeLog | 6 | ||||
| -rw-r--r-- | sysdeps/powerpc/powerpc32/fpu/s_copysignl.S | 23 | ||||
| -rw-r--r-- | sysdeps/powerpc/powerpc64/fpu/s_copysignl.S | 10 |
3 files changed, 30 insertions, 9 deletions
@@ -1,5 +1,11 @@ 2016-10-19 Joseph Myers <joseph@codesourcery.com> + [BZ #20718] + * sysdeps/powerpc/powerpc32/fpu/s_copysignl.S (__copysignl): Do + not use floating-point comparisons to test sign. + * sysdeps/powerpc/powerpc64/fpu/s_copysignl.S (__copysignl): + Likewise. + * math/bits/mathcalls.h [__GLIBC_USE (IEC_60559_BFP_EXT)] (getpayload): New declaration. * math/Versions (getpayload): New libm symbol at version diff --git a/sysdeps/powerpc/powerpc32/fpu/s_copysignl.S b/sysdeps/powerpc/powerpc32/fpu/s_copysignl.S index aed783ad59..1eec8474ed 100644 --- a/sysdeps/powerpc/powerpc32/fpu/s_copysignl.S +++ b/sysdeps/powerpc/powerpc32/fpu/s_copysignl.S @@ -24,22 +24,39 @@ ENTRY(__copysignl) /* long double [f1,f2] copysign (long double [f1,f2] x, long double [f3,f4] y); copysign(x,y) returns a value with the magnitude of x and with the sign bit of y. */ +#ifdef _ARCH_PPCGR + /* fsel available. */ stwu r1,-16(r1) cfi_adjust_cfa_offset (16) stfd fp3,8(r1) fmr fp0,fp1 fabs fp1,fp1 - fcmpu cr7,fp0,fp1 lwz r3,8+HIWORD(r1) cmpwi cr6,r3,0 addi r1,r1,16 cfi_adjust_cfa_offset (-16) - beq cr7,L(0) + fneg fp3,fp2 + fsel fp2,fp0,fp2,fp3 + bgelr cr6 + fneg fp1,fp1 fneg fp2,fp2 -L(0): bgelr cr6 + blr +#else + stwu r1,-32(r1) + cfi_adjust_cfa_offset (32) + stfd fp3,8(r1) + stfd fp1,16(r1) + lwz r3,8+HIWORD(r1) + lwz r4,16+HIWORD(r1) + xor r3,r3,r4 + cmpwi cr6,r3,0 + addi r1,r1,32 + cfi_adjust_cfa_offset (-32) + bgelr cr6 fneg fp1,fp1 fneg fp2,fp2 blr +#endif END (__copysignl) #if IS_IN (libm) diff --git a/sysdeps/powerpc/powerpc64/fpu/s_copysignl.S b/sysdeps/powerpc/powerpc64/fpu/s_copysignl.S index 1e1b9d43e6..548076d25b 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_copysignl.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_copysignl.S @@ -30,16 +30,14 @@ ENTRY(__copysignl) blt L(0) fmr fp0,fp1 fabs fp1,fp1 - fcmpu cr1,fp0,fp1 - beqlr cr1 - fneg fp2,fp2 + fneg fp3,fp2 + fsel fp2,fp0,fp2,fp3 blr L(0): fmr fp0,fp1 fnabs fp1,fp1 - fcmpu cr1,fp0,fp1 - beqlr cr1 - fneg fp2,fp2 + fneg fp3,fp2 + fsel fp2,fp0,fp3,fp2 blr END (__copysignl) |