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| author | Ulrich Drepper <drepper@redhat.com> | 2008-03-07 17:55:11 +0000 |
|---|---|---|
| committer | Ulrich Drepper <drepper@redhat.com> | 2008-03-07 17:55:11 +0000 |
| commit | 78c2bf0eb433515af766d5bbb77901b7c8f9a8cc (patch) | |
| tree | 87b78a8f96faff215404f0498676ccee2159ecf0 /sysdeps/x86_64/cacheinfo.c | |
| parent | dff375150393cf31c06010153082959438da9886 (diff) | |
| download | glibc-78c2bf0eb433515af766d5bbb77901b7c8f9a8cc.tar glibc-78c2bf0eb433515af766d5bbb77901b7c8f9a8cc.tar.gz glibc-78c2bf0eb433515af766d5bbb77901b7c8f9a8cc.tar.bz2 glibc-78c2bf0eb433515af766d5bbb77901b7c8f9a8cc.zip | |
* sysdeps/x86_64/rtld-memset.c: New file.
2008-2-26 Harsha Jagasia <harsha.jagasia@amd.com>
* sysdeps/x86_64/cacheinfo.c (NOT_USED_RIGHT_NOW): Remove ifdef guards.
* sysdeps/x86_64/memset.S: Rewrite non-SSE code path as tuned for AMD
Barcelona machine. Make default fall through branch of
__x86_64_preferred_memory_instruction check as the integer code path.
2007-10-15 H.J. Lu <hongjiu.lu@intel.com>
* sysdeps/x86_64/cacheinfo.c
(__x86_64_preferred_memory_instruction): New variable.
(init_cacheinfo): Initialize __x86_64_preferred_memory_instruction.
* sysdeps/x86_64/memset.S: Rewrite.
2008-01-08 Jakub Jelinek <jakub@redhat.com>
* malloc/malloc.c (public_cALLOc): For arenas other than
Diffstat (limited to 'sysdeps/x86_64/cacheinfo.c')
| -rw-r--r-- | sysdeps/x86_64/cacheinfo.c | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c index 6403081c90..6a3ea0f1cb 100644 --- a/sysdeps/x86_64/cacheinfo.c +++ b/sysdeps/x86_64/cacheinfo.c @@ -405,13 +405,10 @@ long int __x86_64_data_cache_size_half attribute_hidden = 32 * 1024 / 2; /* Shared cache size for use in memory and string routines, typically L2 or L3 size. */ long int __x86_64_shared_cache_size_half attribute_hidden = 1024 * 1024 / 2; -#ifdef NOT_USED_RIGHT_NOW long int __x86_64_shared_cache_size attribute_hidden = 1024 * 1024; -#endif /* PREFETCHW support flag for use in memory and string routines. */ int __x86_64_prefetchw attribute_hidden; -#ifdef NOT_USED_RIGHT_NOW /* Instructions preferred for memory and string routines. 0: Regular instructions @@ -421,7 +418,6 @@ int __x86_64_prefetchw attribute_hidden; */ int __x86_64_preferred_memory_instruction attribute_hidden; -#endif static void @@ -464,14 +460,12 @@ init_cacheinfo (void) : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) : "0" (1)); -#ifdef NOT_USED_RIGHT_NOW - /* Intel prefers SSSE3 instructions for memory/string rountines + /* Intel prefers SSSE3 instructions for memory/string routines if they are avaiable. */ if ((ecx & 0x200)) __x86_64_preferred_memory_instruction = 3; else __x86_64_preferred_memory_instruction = 2; -#endif /* Figure out the number of logical threads that share the highest cache level. */ @@ -577,8 +571,6 @@ init_cacheinfo (void) if (shared > 0) { __x86_64_shared_cache_size_half = shared / 2; -#ifdef NOT_USED_RIGHT_NOW __x86_64_shared_cache_size = shared; -#endif } } |